From nobody Fri Dec 19 08:06:29 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0D9F27E1D6 for ; Fri, 11 Apr 2025 07:04:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744355063; cv=none; b=AaM8GRj8iKIFXX8XJb1ukwZ8D2e+kMEaOd4lJssuRsJ7akLOoSJUBGjx8W8CQaj1o67t0DW0qmL64oKu6wARY0CNP1VEINwgYIWXCRuDjawZy7fEdsCHqghEuhqsrS5f74wL1tO9VU732gOtqKvKiIGQP/KX0W5EdaP+HlTJdLo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744355063; c=relaxed/simple; bh=VDxcma+ffVDfUCyYSA4dC9lEW94546qLv3OjqCFfl/8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=X6Y+xYMpYRr+KJ+R+oEkO34s3Vvzh7X1zAULA6XaynqoUwIWFM+t8PGFQGPT3FQGOSeL0+yFC0N2j6pp8vaQqDs0hGoRTl7tsVqqPeFa7oknbh+VOFSdQRmICSKzmX/Tzjovv5/cNZMkqjKIPLI1eO5Jq3+EoQSvSEgN3nrEjxE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=XBRnSoPx; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=gTqef5cX; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="XBRnSoPx"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="gTqef5cX" From: "Ahmed S. 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 1/2] x86/cpuid: Remove obsolete CPUID(0x2) iteration macro Date: Fri, 11 Apr 2025 09:04:00 +0200 Message-ID: <20250411070401.1358760-2-darwi@linutronix.de> In-Reply-To: <20250411070401.1358760-1-darwi@linutronix.de> References: <20250411070401.1358760-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The CPUID(0x2) cache descriptors iterator at : for_each_leaf_0x2_desc() has no more call sites. Remove it. Fixes: 4772304ee651 ("x86/cpu: Use consolidated CPUID leaf 0x2 descriptor t= able") Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/leaf_0x2_api.h | 23 ----------------------- 1 file changed, 23 deletions(-) diff --git a/arch/x86/include/asm/cpuid/leaf_0x2_api.h b/arch/x86/include/a= sm/cpuid/leaf_0x2_api.h index 46ecb15e92d9..09fa3070b271 100644 --- a/arch/x86/include/asm/cpuid/leaf_0x2_api.h +++ b/arch/x86/include/asm/cpuid/leaf_0x2_api.h @@ -40,29 +40,6 @@ static inline void cpuid_get_leaf_0x2_regs(union leaf_0x= 2_regs *regs) } } =20 -/** - * for_each_leaf_0x2_desc() - Iterator for CPUID leaf 0x2 descriptors - * @regs: Leaf 0x2 output, as returned by cpuid_get_leaf_0x2_regs() - * @desc: Pointer to the returned descriptor for each iteration - * - * Loop over the 1-byte descriptors in the passed leaf 0x2 output registers - * @regs. Provide each descriptor through @desc. - * - * Note that the first byte is skipped as it is not a descriptor. - * - * Sample usage:: - * - * union leaf_0x2_regs regs; - * u8 *desc; - * - * cpuid_get_leaf_0x2_regs(®s); - * for_each_leaf_0x2_desc(regs, desc) { - * // Handle *desc value - * } - */ -#define for_each_leaf_0x2_desc(regs, desc) \ - for (desc =3D &(regs).desc[1]; desc < &(regs).desc[16]; desc++) - /** * for_each_leaf_0x2_entry() - Iterator for parsed leaf 0x2 descriptors * @regs: Leaf 0x2 register output, returned by cpuid_get_leaf_0x2_regs() --=20 2.49.0 From nobody Fri Dec 19 08:06:29 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4F0527EC7D for ; Fri, 11 Apr 2025 07:04:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744355066; cv=none; b=uXq/QEmx/N49zXOi+AVZ5XwP/9157lMcWXL+FiI5KrS9aQITOsR8kyA7/WfzFazMMUaUz1lrAfeURKPG4dEh/I0VlN7xXrU8OqUBE4++4fQqy1ZHvijotZ0zrUbXLkpygGvPBQXl90zsWUvTk5Dy8yafuuwjy0OJJ3j0pLzpL9M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744355066; c=relaxed/simple; bh=ySVeJdWJuakANiYyE9FVHFeBrWSom6GjCdzvIpzIyFY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ijl1D3fTWARft31H+X9GBu76g+ja7bD+K7J6EzkkOYspR6M594uTwgq3TLJ/uKV+97fMaVIt3S1DkHeyIvWq3WCgC8gCZ1Ki2CNaP+WGtTt2FDJQeAZWPpeV0JqRXL+dDgnnLDexlaN+AWtrwjaykALNffzuWLx/aTA6kc7X9ak= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=D3FXasTP; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=VzsvHXQq; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="D3FXasTP"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="VzsvHXQq" From: "Ahmed S. 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Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 2/2] x86/cacheinfo: Standardize header files and CPUID references Date: Fri, 11 Apr 2025 09:04:01 +0200 Message-ID: <20250411070401.1358760-3-darwi@linutronix.de> In-Reply-To: <20250411070401.1358760-1-darwi@linutronix.de> References: <20250411070401.1358760-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reference header files using their canonical form . Standardize on CPUID(0xN), instead of CPUID(N), for all standard leaves. This removes ambiguity and aligns them with their extended counterparts like CPUID(0x8000001d). References: 0dd09e215a39 ("x86/cacheinfo: Apply maintainer-tip coding style= fixes") Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 52727f8c0006..cc7ae2bdcf4a 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -3,9 +3,9 @@ * x86 CPU caches detection and configuration * * Previous changes - * - Venkatesh Pallipadi: Cache identification through CPUID(4) + * - Venkatesh Pallipadi: Cache identification through CPUID(0x4) * - Ashok Raj : Work with CPU hotplug infrastructure - * - Andi Kleen / Andreas Herrmann: CPUID(4) emulation on AMD + * - Andi Kleen / Andreas Herrmann: CPUID(0x4) emulation on AMD */ =20 #include @@ -78,7 +78,7 @@ struct _cpuid4_info { unsigned long size; }; =20 -/* Map CPUID(4) EAX.cache_type to linux/cacheinfo.h types */ +/* Map CPUID(0x4) EAX.cache_type to types */ static const enum cache_type cache_type_map[] =3D { [CTYPE_NULL] =3D CACHE_TYPE_NOCACHE, [CTYPE_DATA] =3D CACHE_TYPE_DATA, @@ -87,7 +87,7 @@ static const enum cache_type cache_type_map[] =3D { }; =20 /* - * Fallback AMD CPUID(4) emulation + * Fallback AMD CPUID(0x4) emulation * AMD CPUs with TOPOEXT can just use CPUID(0x8000001d) * * @AMD_L2_L3_INVALID_ASSOC: cache info for the respective L2/L3 cache sho= uld @@ -361,7 +361,7 @@ static void intel_cacheinfo_done(struct cpuinfo_x86 *c,= unsigned int l3, { /* * If llc_id is still unset, then cpuid_level < 4, which implies - * that the only possibility left is SMT. Since CPUID(2) doesn't + * that the only possibility left is SMT. Since CPUID(0x2) doesn't * specify any shared caches and SMT shares all caches, we can * unconditionally set LLC ID to the package ID so that all * threads share it. @@ -376,7 +376,7 @@ static void intel_cacheinfo_done(struct cpuinfo_x86 *c,= unsigned int l3, } =20 /* - * Legacy Intel CPUID(2) path if CPUID(4) is not available. + * Legacy Intel CPUID(0x2) path if CPUID(0x4) is not available. */ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) { @@ -466,7 +466,7 @@ static bool intel_cacheinfo_0x4(struct cpuinfo_x86 *c) =20 void init_intel_cacheinfo(struct cpuinfo_x86 *c) { - /* Don't use CPUID(2) if CPUID(4) is supported. */ + /* Don't use CPUID(0x2) if CPUID(0x4) is supported. */ if (intel_cacheinfo_0x4(c)) return; =20 @@ -474,7 +474,7 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) } =20 /* - * linux/cacheinfo.h shared_cpu_map setup, AMD/Hygon + * shared_cpu_map setup, AMD/Hygon */ static int __cache_amd_cpumap_setup(unsigned int cpu, int index, const struct _cpuid4_info *id4) @@ -533,7 +533,7 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, i= nt index, } =20 /* - * linux/cacheinfo.h shared_cpu_map setup, Intel + fallback AMD/Hygon + * shared_cpu_map setup, Intel + fallback AMD/Hygon */ static void __cache_cpumap_setup(unsigned int cpu, int index, const struct _cpuid4_info *id4) @@ -599,7 +599,7 @@ int init_cache_level(unsigned int cpu) } =20 /* - * The max shared threads number comes from CPUID(4) EAX[25-14] with input + * The max shared threads number comes from CPUID(0x4) EAX[25-14] with inp= ut * ECX as cache index. Then right shift apicid by the number's order to get * cache id for this cache node. */ --=20 2.49.0