From nobody Thu Dec 18 15:28:15 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 140DA215184; Thu, 10 Apr 2025 09:01:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744275700; cv=none; b=aDDLBTEKMUESMgaYH+gu8QG2L/1NPmjXhynzCqsrjQuWXFjtTOVtm5/6PvzPE8zRA/0cgwxCg7COOLRGno7AEswU386MJe4ocbrY+JTYnTfPONUZCg9NxlO9PNcf8oRqxdh1SwMvKIL1bNcRVbQdQiGQFltTzoMkI1u9NOXTAVM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744275700; c=relaxed/simple; bh=jL8vmT5zoHcFuv7BurIPN/m4YXpnYGTLvGjkv6dRpo4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nlq/ZigVYb+grfwUrCYiD6HbEP4rT+aMRr9vWgkX1VjREjyPJ4i4aByWBPVSA5TLO9Gsg6ujzboyQd94ndvQoEN9FpsujUY+FI/movLvIYg1PqQeB5MOrrA6mkPVEjbHfSluScmahjTxwARRKObFLr3xwZp/Q/Mbz1Jq6AAHwcs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=CMZwxfv8; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="CMZwxfv8" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53A75Nxq010681; Thu, 10 Apr 2025 09:01:20 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=o39dImsEDMm LbzTS0Cw7u/jvlELVtoCYeKBERryd5iw=; b=CMZwxfv8UwiSfcKqHXhbELG5UUM jDkYYY2DsZx2oMaKCJleC3nyp2wL+QTG//ghFZSsky9vTU6x/TdQKO3AvU8JTjA+ 5dLygMOer3Xmcp8pNYiWB4kH0QVHyQ+4iPP9V2W37orQGXsYxqWYQ91r4AASxfbV q7AX76xHc5vHC+SLOns65pL4jq4YIMqQmJxaKXMYzTbY0I9UT6pPLZxzaD5oUtC8 EM+KxH16QHpgDe3P/gPKi1mbGY1xdRyYiB93/nr74JM8sBuPzgBrwQJbmseB7hr9 iGSiFktoOwbeB6SyYtmsMUlNUqaL6bepHy9AUexN1j9BLV1k19St2RwJ/9Q== Received: from apblrppmta01.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 45twg3p85s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Apr 2025 09:01:19 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 53A8vqjm005648; Thu, 10 Apr 2025 09:01:16 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 45ue7g3rd1-1; Thu, 10 Apr 2025 09:01:16 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 53A8vpBZ005643; Thu, 10 Apr 2025 09:01:16 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-nitirawa-hyd.qualcomm.com [10.213.109.152]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 53A91GIW009313; Thu, 10 Apr 2025 09:01:16 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2342877) id BBF5A50158F; Thu, 10 Apr 2025 14:31:15 +0530 (+0530) From: Nitin Rawat To: vkoul@kernel.org, kishon@kernel.org, manivannan.sadhasivam@linaro.org, James.Bottomley@HansenPartnership.com, martin.petersen@oracle.com, bvanassche@acm.org, bjorande@quicinc.com, neil.armstrong@linaro.org, konrad.dybcio@oss.qualcomm.com Cc: quic_rdwivedi@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, Nitin Rawat , Can Guo Subject: [PATCH V3 8/9] scsi: ufs: qcom : Introduce phy_power_on/off wrapper function Date: Thu, 10 Apr 2025 14:31:01 +0530 Message-ID: <20250410090102.20781-9-quic_nitirawa@quicinc.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250410090102.20781-1-quic_nitirawa@quicinc.com> References: <20250410090102.20781-1-quic_nitirawa@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: P2jACil0_kE8NUxYpK1Hf9Hh2QmkYD-A X-Proofpoint-ORIG-GUID: P2jACil0_kE8NUxYpK1Hf9Hh2QmkYD-A X-Authority-Analysis: v=2.4 cv=I/9lRMgg c=1 sm=1 tr=0 ts=67f788e0 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=fCbX77z8Gh-i-5kHVyEA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-10_01,2025-04-08_04,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 phishscore=0 suspectscore=0 mlxlogscore=999 lowpriorityscore=0 spamscore=0 clxscore=1015 malwarescore=0 adultscore=0 priorityscore=1501 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504100067 Content-Type: text/plain; charset="utf-8" Introduce ufs_qcom_phy_power_on and ufs_qcom_phy_power_off wrapper functions with mutex protection to ensure safe usage of is_phy_pwr_on and prevent possible race conditions. Co-developed-by: Can Guo Signed-off-by: Can Guo Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 44 +++++++++++++++++++++++++++++++------ drivers/ufs/host/ufs-qcom.h | 4 ++++ 2 files changed, 41 insertions(+), 7 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 197e84d47eec..6a7b51e0759c 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -421,6 +421,38 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba) return UFS_HS_G3; } =20 +static int ufs_qcom_phy_power_on(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); + struct phy *phy =3D host->generic_phy; + int ret =3D 0; + + guard(mutex)(&host->phy_mutex); + if (!host->is_phy_pwr_on) { + ret =3D phy_power_on(phy); + if (!ret) + host->is_phy_pwr_on =3D true; + } + + return ret; +} + +static int ufs_qcom_phy_power_off(struct ufs_hba *hba) +{ + struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); + struct phy *phy =3D host->generic_phy; + int ret =3D 0; + + guard(mutex)(&host->phy_mutex); + if (host->is_phy_pwr_on) { + ret =3D phy_power_off(phy); + if (!ret) + host->is_phy_pwr_on =3D false; + } + + return ret; +} + static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) { struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); @@ -449,7 +481,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) return ret; =20 if (phy->power_count) { - phy_power_off(phy); + ufs_qcom_phy_power_off(hba); phy_exit(phy); } =20 @@ -466,7 +498,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *h= ba) goto out_disable_phy; =20 /* power on phy - start serdes and phy's power and clocks */ - ret =3D phy_power_on(phy); + ret =3D ufs_qcom_phy_power_on(hba); if (ret) { dev_err(hba->dev, "%s: phy power on failed, ret =3D %d\n", __func__, ret); @@ -1018,7 +1050,6 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba,= bool on, enum ufs_notify_change_status status) { struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); - struct phy *phy =3D host->generic_phy; int err; =20 /* @@ -1038,7 +1069,7 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba,= bool on, /* disable device ref_clk */ ufs_qcom_dev_ref_clk_ctrl(host, false); } - err =3D phy_power_off(phy); + err =3D ufs_qcom_phy_power_off(hba); if (err) { dev_err(hba->dev, "%s: phy power off failed, ret=3D%d\n", __func__, err); @@ -1048,7 +1079,7 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba,= bool on, break; case POST_CHANGE: if (on) { - err =3D phy_power_on(phy); + err =3D ufs_qcom_phy_power_on(hba); if (err) { dev_err(hba->dev, "%s: phy power on failed, ret =3D %d\n", __func__, err); @@ -1236,10 +1267,9 @@ static int ufs_qcom_init(struct ufs_hba *hba) static void ufs_qcom_exit(struct ufs_hba *hba) { struct ufs_qcom_host *host =3D ufshcd_get_variant(hba); - struct phy *phy =3D host->generic_phy; =20 ufs_qcom_disable_lane_clks(host); - phy_power_off(phy); + ufs_qcom_phy_power_off(hba); phy_exit(host->generic_phy); } =20 diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index d0e6ec9128e7..3db29fbcd40b 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -252,6 +252,10 @@ struct ufs_qcom_host { u32 phy_gear; =20 bool esi_enabled; + /* flag to check if phy is powered on */ + bool is_phy_pwr_on; + /* Protect the usage of is_phy_pwr_on against racing */ + struct mutex phy_mutex; }; =20 struct ufs_qcom_drvdata { --=20 2.48.1