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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22ac7ccb596sm18801815ad.220.2025.04.09.18.33.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Apr 2025 18:33:45 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Tingwei Zhang , Jinlong Mao , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 1/5] coresight: tmc: Introduce new APIs to get the RWP offset of ETR buffer Date: Thu, 10 Apr 2025 09:33:26 +0800 Message-Id: <20250410013330.3609482-2-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250410013330.3609482-1-jie.gan@oss.qualcomm.com> References: <20250410013330.3609482-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: 725mY5CaT0JhdeL4opmStBDSAO3esyyO X-Proofpoint-ORIG-GUID: 725mY5CaT0JhdeL4opmStBDSAO3esyyO X-Authority-Analysis: v=2.4 cv=MpRS63ae c=1 sm=1 tr=0 ts=67f71ffb cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=QSMfYRlErQPllaMuWGUA:9 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-09_06,2025-04-08_04,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=887 clxscore=1015 priorityscore=1501 impostorscore=0 spamscore=0 bulkscore=0 suspectscore=0 malwarescore=0 adultscore=0 phishscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504100010 Content-Type: text/plain; charset="utf-8" The new functions calculate and return the offset to the write pointer of the ETR buffer based on whether the memory mode is SG, flat or reserved. The functions have the RWP offset can directly read data from ETR buffer, enabling the transfer of data to any required location. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-etr.c | 62 +++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 1 + 2 files changed, 63 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 76a8cb29b68a..ed8a89fcd3fc 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1236,6 +1236,68 @@ void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) drvdata->etr_buf =3D NULL; } =20 +static long tmc_etr_flat_resrv_get_rwp_offset(struct tmc_drvdata *drvdata) +{ + dma_addr_t paddr =3D drvdata->sysfs_buf->hwaddr; + u64 rwp; + + rwp =3D tmc_read_rwp(drvdata); + return rwp - paddr; +} + +static long tmc_etr_sg_get_rwp_offset(struct tmc_drvdata *drvdata) +{ + struct etr_buf *etr_buf =3D drvdata->sysfs_buf; + struct etr_sg_table *etr_table =3D etr_buf->private; + struct tmc_sg_table *table =3D etr_table->sg_table; + long w_offset; + u64 rwp; + + rwp =3D tmc_read_rwp(drvdata); + w_offset =3D tmc_sg_get_data_page_offset(table, rwp); + + return w_offset; +} + +/** + * tmc_etr_get_rwp_offset() - Retrieving the offset to the write pointer. + * + * @drvdata: driver data of TMC device. + * + * Retrieve the offset to the write pointer of the ETR + * buffer based on whether the memory mode is SG, flat or reserved. + * + * Return w_offset of the ETR buffer upon success, else the error number. + */ +long tmc_etr_get_rwp_offset(struct tmc_drvdata *drvdata) +{ + struct etr_buf *etr_buf; + long w_offset; + + if (WARN_ON(!drvdata) || WARN_ON(!drvdata->sysfs_buf) || + WARN_ON(drvdata->config_type !=3D TMC_CONFIG_TYPE_ETR)) + return -EINVAL; + + etr_buf =3D drvdata->sysfs_buf; + /* Disable the ETR if it is running */ + if (coresight_get_mode(drvdata->csdev) !=3D CS_MODE_DISABLED) + __tmc_etr_disable_hw(drvdata); + + if (etr_buf->mode =3D=3D ETR_MODE_ETR_SG) + w_offset =3D tmc_etr_sg_get_rwp_offset(drvdata); + else if (etr_buf->mode =3D=3D ETR_MODE_FLAT || etr_buf->mode =3D=3D ETR_M= ODE_RESRV) + w_offset =3D tmc_etr_flat_resrv_get_rwp_offset(drvdata); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22ac7ccb596sm18801815ad.220.2025.04.09.18.33.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Apr 2025 18:33:50 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Tingwei Zhang , Jinlong Mao , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 2/5] dt-bindings: arm: Add an interrupt property for Coresight CTCU Date: Thu, 10 Apr 2025 09:33:27 +0800 Message-Id: <20250410013330.3609482-3-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250410013330.3609482-1-jie.gan@oss.qualcomm.com> References: <20250410013330.3609482-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: kYzA7qnxLKbaTap0De3-E1dr8aQTJf9P X-Authority-Analysis: v=2.4 cv=T7OMT+KQ c=1 sm=1 tr=0 ts=67f72002 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=gSyxy6DGYGa4b6s9XCEA:9 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-ORIG-GUID: kYzA7qnxLKbaTap0De3-E1dr8aQTJf9P X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-09_06,2025-04-08_04,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 adultscore=0 phishscore=0 bulkscore=0 mlxscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 spamscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504100010 Content-Type: text/plain; charset="utf-8" Add an interrupt property to CTCU device. The interrupt will be triggered when the data size in the ETR buffer exceeds the threshlod of the BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register of CTCU device will enable the interrupt. Signed-off-by: Jie Gan Acked-by: Krzysztof Kozlowski --- .../bindings/arm/qcom,coresight-ctcu.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml= b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index 843b52eaf872..ea05ad8f3dd3 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -39,6 +39,16 @@ properties: items: - const: apb =20 + interrupts: + items: + - description: Byte cntr interrupt for etr0 + - description: Byte cntr interrupt for etr1 + + interrupt-names: + items: + - const: etr0 + - const: etr1 + in-ports: $ref: /schemas/graph.yaml#/properties/ports =20 @@ -56,6 +66,8 @@ additionalProperties: false =20 examples: - | + #include + ctcu@1001000 { compatible =3D "qcom,sa8775p-ctcu"; reg =3D <0x1001000 0x1000>; @@ -63,6 +75,11 @@ examples: clocks =3D <&aoss_qmp>; clock-names =3D "apb"; =20 + interrupts =3D , + ; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22ac7ccb596sm18801815ad.220.2025.04.09.18.33.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Apr 2025 18:33:57 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Tingwei Zhang , Jinlong Mao , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 3/5] coresight: ctcu: Enable byte-cntr for TMC ETR devices Date: Thu, 10 Apr 2025 09:33:28 +0800 Message-Id: <20250410013330.3609482-4-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250410013330.3609482-1-jie.gan@oss.qualcomm.com> References: <20250410013330.3609482-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=PJgP+eqC c=1 sm=1 tr=0 ts=67f72008 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=VuEiWhZmLyiD4YjWg_QA:9 a=RVmHIydaz68A:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: TdPzeeOmpOYaD3ZX5HEOh54ZEzCE-J-v X-Proofpoint-GUID: TdPzeeOmpOYaD3ZX5HEOh54ZEzCE-J-v X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-09_06,2025-04-08_04,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 clxscore=1011 adultscore=0 malwarescore=0 spamscore=0 impostorscore=0 suspectscore=0 mlxlogscore=999 bulkscore=0 mlxscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504100010 Content-Type: text/plain; charset="utf-8" The byte-cntr function provided by the CTCU device is used to transfer data from the ETR buffer to the userspace. An interrupt is triggered if the data size exceeds the threshold set in the BYTECNTRVAL register. The interrupt handler counts the number of triggered interruptions and the read function will read the data from the ETR buffer if the IRQ count is greater than 0. Each successful read process will decrement the IRQ count by 1. Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/Makefile | 2 +- .../coresight/coresight-ctcu-byte-cntr.c | 119 ++++++++++++++++++ .../hwtracing/coresight/coresight-ctcu-core.c | 88 ++++++++++++- drivers/hwtracing/coresight/coresight-ctcu.h | 49 +++++++- drivers/hwtracing/coresight/coresight-tmc.h | 1 + 5 files changed, 252 insertions(+), 7 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/cores= ight/Makefile index 8e62c3150aeb..c90a06768a18 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -52,4 +52,4 @@ coresight-cti-y :=3D coresight-cti-core.o coresight-cti-p= latform.o \ obj-$(CONFIG_ULTRASOC_SMB) +=3D ultrasoc-smb.o obj-$(CONFIG_CORESIGHT_DUMMY) +=3D coresight-dummy.o obj-$(CONFIG_CORESIGHT_CTCU) +=3D coresight-ctcu.o -coresight-ctcu-y :=3D coresight-ctcu-core.o +coresight-ctcu-y :=3D coresight-ctcu-core.o coresight-ctcu-byte-cntr.o diff --git a/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c b/drive= rs/hwtracing/coresight/coresight-ctcu-byte-cntr.c new file mode 100644 index 000000000000..db0bb5a71ed6 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include "coresight-ctcu.h" +#include "coresight-priv.h" +#include "coresight-tmc.h" + +static irqreturn_t byte_cntr_handler(int irq, void *data) +{ + struct ctcu_byte_cntr *byte_cntr_data =3D (struct ctcu_byte_cntr *)data; + + atomic_inc(&byte_cntr_data->irq_cnt); + wake_up(&byte_cntr_data->wq); + + return IRQ_HANDLED; +} + +/* Start the byte-cntr function when the path is enabled. */ +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight= _path *path) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + struct coresight_device *sink =3D coresight_get_sink(path); + struct ctcu_byte_cntr *byte_cntr_data; + struct tmc_drvdata *tmcdrvdata; + int port_num; + + if (!sink) + return; + + tmcdrvdata =3D dev_get_drvdata(sink->dev.parent); + port_num =3D ctcu_get_active_port(sink, csdev); + if (port_num < 0) + return; + + byte_cntr_data =3D &drvdata->byte_cntr_data[port_num]; + /* Don't start byte-cntr function when threshold is not set. */ + if (!byte_cntr_data->thresh_val) + return; + + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + atomic_set(&byte_cntr_data->irq_cnt, 0); + tmcdrvdata->byte_cntr_data =3D byte_cntr_data; + byte_cntr_data->enable =3D true; +} + +/* Stop the byte-cntr function when the path is disabled. */ +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_= path *path) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + struct coresight_device *sink =3D coresight_get_sink(path); + struct ctcu_byte_cntr *byte_cntr_data; + struct tmc_drvdata *tmcdrvdata; + long w_offset; + int port_num; + + if (!sink) + return; + + port_num =3D ctcu_get_active_port(sink, csdev); + if (port_num < 0) + return; + + byte_cntr_data =3D &drvdata->byte_cntr_data[port_num]; + tmcdrvdata =3D dev_get_drvdata(sink->dev.parent); + + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + /* Store the w_offset of the ETR buffer when stopping. */ + w_offset =3D tmc_etr_get_rwp_offset(tmcdrvdata); + if (w_offset >=3D 0) + byte_cntr_data->w_offset =3D w_offset; + + atomic_set(&byte_cntr_data->irq_cnt, 0); + byte_cntr_data->read_active =3D false; + byte_cntr_data->enable =3D false; + /* + * Wakeup once to force the read function to read the remaining + * data of the ETR buffer. + */ + wake_up(&byte_cntr_data->wq); +} + +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata,= int etr_num) +{ + struct ctcu_byte_cntr *byte_cntr_data; + struct device_node *nd =3D dev->of_node; + int byte_cntr_irq, ret, i; + + for (i =3D 0; i < etr_num; i++) { + byte_cntr_data =3D &drvdata->byte_cntr_data[i]; + byte_cntr_irq =3D of_irq_get_byname(nd, byte_cntr_data->irq_name); + if (byte_cntr_irq < 0) { + dev_err(dev, "Failed to get IRQ from DT for %s\n", + byte_cntr_data->irq_name); + continue; + } + + ret =3D devm_request_irq(dev, byte_cntr_irq, byte_cntr_handler, + IRQF_TRIGGER_RISING | IRQF_SHARED, + dev_name(dev), byte_cntr_data); + if (ret) { + dev_err(dev, "Failed to register IRQ for %s\n", + byte_cntr_data->irq_name); + continue; + } + + byte_cntr_data->byte_cntr_irq =3D byte_cntr_irq; + atomic_set(&byte_cntr_data->irq_cnt, 0); + init_waitqueue_head(&byte_cntr_data->wq); + } +} diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hw= tracing/coresight/coresight-ctcu-core.c index c6bafc96db96..fef516d7a474 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -46,16 +46,22 @@ DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu"); #define CTCU_ATID_REG_BIT(traceid) (traceid % 32) #define CTCU_ATID_REG_SIZE 0x10 #define CTCU_ETR0_ATID0 0xf8 +#define CTCU_ETR0_IRQCTRL 0x6c #define CTCU_ETR1_ATID0 0x108 +#define CTCU_ETR1_IRQCTRL 0x70 =20 static const struct ctcu_etr_config sa8775p_etr_cfgs[] =3D { { - .atid_offset =3D CTCU_ETR0_ATID0, - .port_num =3D 0, + .atid_offset =3D CTCU_ETR0_ATID0, + .irq_ctrl_offset =3D CTCU_ETR0_IRQCTRL, + .irq_name =3D "etr0", + .port_num =3D 0, }, { - .atid_offset =3D CTCU_ETR1_ATID0, - .port_num =3D 1, + .atid_offset =3D CTCU_ETR1_ATID0, + .irq_ctrl_offset =3D CTCU_ETR1_IRQCTRL, + .irq_name =3D "etr1", + .port_num =3D 1, }, }; =20 @@ -64,6 +70,69 @@ static const struct ctcu_config sa8775p_cfgs =3D { .num_etr_config =3D ARRAY_SIZE(sa8775p_etr_cfgs), }; =20 +static ssize_t byte_cntr_val_show(struct device *dev, struct device_attrib= ute *attr, + char *buf) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + int i, len =3D 0; + + for (i =3D 0; i < ETR_MAX_NUM; i++) { + if (drvdata->byte_cntr_data[i].irq_ctrl_offset) + len +=3D scnprintf(buf + len, PAGE_SIZE - len, "%u ", + drvdata->byte_cntr_data[i].thresh_val); + } + + len +=3D scnprintf(buf + len, PAGE_SIZE - len, "\n"); + + return len; +} + +static ssize_t byte_cntr_val_store(struct device *dev, struct device_attri= bute *attr, + const char *buf, size_t size) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + u32 thresh_vals[ETR_MAX_NUM] =3D { 0 }; + u32 irq_ctrl_offset; + int num, i; + + num =3D sscanf(buf, "%i %i", &thresh_vals[0], &thresh_vals[1]); + if (num <=3D 0 || num > ETR_MAX_NUM) + return -EINVAL; + + /* Threshold 0 disables the interruption. */ + guard(raw_spinlock_irqsave)(&drvdata->spin_lock); + for (i =3D 0; i < num; i++) { + /* A small threshold will result in a large number of interruptions */ + if (thresh_vals[i] && thresh_vals[i] < 4096) + return -EINVAL; + + if (drvdata->byte_cntr_data[i].irq_ctrl_offset) { + drvdata->byte_cntr_data[i].thresh_val =3D thresh_vals[i]; + irq_ctrl_offset =3D drvdata->byte_cntr_data[i].irq_ctrl_offset; + CS_UNLOCK(drvdata->base); + writel_relaxed(thresh_vals[i], drvdata->base + irq_ctrl_offset); + CS_LOCK(drvdata->base); + } + } + + return size; +} +static DEVICE_ATTR_RW(byte_cntr_val); + +static struct attribute *ctcu_attrs[] =3D { + &dev_attr_byte_cntr_val.attr, + NULL, +}; + +static struct attribute_group ctcu_attr_grp =3D { + .attrs =3D ctcu_attrs, +}; + +static const struct attribute_group *ctcu_attr_grps[] =3D { + &ctcu_attr_grp, + NULL, +}; + static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 r= eg_offset, u8 bit, bool enable) { @@ -122,7 +191,7 @@ static int __ctcu_set_etr_traceid(struct coresight_devi= ce *csdev, u8 traceid, in * Searching the sink device from helper's view in case there are multiple= helper devices * connected to the sink device. */ -static int ctcu_get_active_port(struct coresight_device *sink, struct core= sight_device *helper) +int ctcu_get_active_port(struct coresight_device *sink, struct coresight_d= evice *helper) { struct coresight_platform_data *pdata =3D helper->pdata; int i; @@ -160,6 +229,8 @@ static int ctcu_enable(struct coresight_device *csdev, = enum cs_mode mode, void * { struct coresight_path *path =3D (struct coresight_path *)data; =20 + ctcu_byte_cntr_start(csdev, path); + return ctcu_set_etr_traceid(csdev, path, true); } =20 @@ -167,6 +238,8 @@ static int ctcu_disable(struct coresight_device *csdev,= void *data) { struct coresight_path *path =3D (struct coresight_path *)data; =20 + ctcu_byte_cntr_stop(csdev, path); + return ctcu_set_etr_traceid(csdev, path, false); } =20 @@ -217,7 +290,11 @@ static int ctcu_probe(struct platform_device *pdev) for (i =3D 0; i < cfgs->num_etr_config; i++) { etr_cfg =3D &cfgs->etr_cfgs[i]; drvdata->atid_offset[i] =3D etr_cfg->atid_offset; + drvdata->byte_cntr_data[i].irq_name =3D etr_cfg->irq_name; + drvdata->byte_cntr_data[i].irq_ctrl_offset =3D + etr_cfg->irq_ctrl_offset; } + ctcu_byte_cntr_init(dev, drvdata, cfgs->num_etr_config); } } =20 @@ -229,6 +306,7 @@ static int ctcu_probe(struct platform_device *pdev) desc.subtype.helper_subtype =3D CORESIGHT_DEV_SUBTYPE_HELPER_CTCU; desc.pdata =3D pdata; desc.dev =3D dev; + desc.groups =3D ctcu_attr_grps; desc.ops =3D &ctcu_ops; desc.access =3D CSDEV_ACCESS_IOMEM(base); =20 diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/hwtraci= ng/coresight/coresight-ctcu.h index e9594c38dd91..bc54cce358da 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu.h +++ b/drivers/hwtracing/coresight/coresight-ctcu.h @@ -5,6 +5,7 @@ =20 #ifndef _CORESIGHT_CTCU_H #define _CORESIGHT_CTCU_H + #include "coresight-trace-id.h" =20 /* Maximum number of supported ETR devices for a single CTCU. */ @@ -13,10 +14,14 @@ /** * struct ctcu_etr_config * @atid_offset: offset to the ATID0 Register. - * @port_num: in-port number of CTCU device that connected to ETR. + * @irq_ctrl_offset: offset to the BYTECNTRVAL register. + * @irq_name: IRQ name in dt node. + * @port_num: in-port number of the CTCU device that connected to ETR. */ struct ctcu_etr_config { const u32 atid_offset; + const u32 irq_ctrl_offset; + const char *irq_name; const u32 port_num; }; =20 @@ -25,15 +30,57 @@ struct ctcu_config { int num_etr_config; }; =20 +/** + * struct ctcu_byte_cntr + * @enable: indicates that byte_cntr function is enabled or not. + * @read_active: indicates that byte-cntr node is opened or not. + * @thresh_val: threshold to trigger a interruption. + * @total_size total size of transferred data. + * @byte_cntr_irq: IRQ number. + * @irq_cnt: IRQ count. + * @wq: workqueue of reading ETR data. + * @read_work: work of reading ETR data. + * @spin_lock: spinlock of byte cntr data. + * @r_offset: offset of the pointer where reading begins. + * @w_offset: offset of the write pointer in the ETR buffer when + * the byte cntr is stopped. + * @irq_ctrl_offset: offset to the BYTECNTVAL Register. + * @irq_name: IRQ name in DT. + */ +struct ctcu_byte_cntr { + bool enable; + bool read_active; + u32 thresh_val; + u64 total_size; + int byte_cntr_irq; + atomic_t irq_cnt; + wait_queue_head_t wq; + struct work_struct read_work; + raw_spinlock_t spin_lock; + long r_offset; + long w_offset; + u32 irq_ctrl_offset; + const char *irq_name; +}; + struct ctcu_drvdata { void __iomem *base; struct clk *apb_clk; struct device *dev; struct coresight_device *csdev; + struct ctcu_byte_cntr byte_cntr_data[ETR_MAX_NUM]; raw_spinlock_t spin_lock; u32 atid_offset[ETR_MAX_NUM]; /* refcnt for each traceid of each sink */ u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; }; =20 +/* Generic functions */ +int ctcu_get_active_port(struct coresight_device *sink, struct coresight_d= evice *helper); + +/* Byte-cntr functions */ +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight= _path *path); +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_= path *path); +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata,= int port_num); + #endif diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 945c69f6e6ca..015592863352 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -271,6 +271,7 @@ struct tmc_drvdata { struct etr_buf *perf_buf; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22ac7ccb596sm18801815ad.220.2025.04.09.18.33.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Apr 2025 18:34:02 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Tingwei Zhang , Jinlong Mao , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 4/5] coresight: tmc: add functions for byte-cntr operation Date: Thu, 10 Apr 2025 09:33:29 +0800 Message-Id: <20250410013330.3609482-5-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250410013330.3609482-1-jie.gan@oss.qualcomm.com> References: <20250410013330.3609482-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: jgJHdKBas0yQsfyOaiwG6SkU2IZHt8ow X-Authority-Analysis: v=2.4 cv=Q4vS452a c=1 sm=1 tr=0 ts=67f7200d cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=vnqp29LrZxOKxJPgRI8A:9 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-GUID: jgJHdKBas0yQsfyOaiwG6SkU2IZHt8ow X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-09_06,2025-04-08_04,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 lowpriorityscore=0 spamscore=0 clxscore=1015 phishscore=0 bulkscore=0 adultscore=0 malwarescore=0 mlxscore=0 suspectscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504100010 Content-Type: text/plain; charset="utf-8" The byte-cntr function only copy trace data from etr_buf based on the IRQ count number. The system will call byte-cntr realted functions when the BYTECNTRVAL register has configured. Signed-off-by: Jie Gan --- .../hwtracing/coresight/coresight-tmc-core.c | 29 ++++- .../hwtracing/coresight/coresight-tmc-etr.c | 113 ++++++++++++++++++ drivers/hwtracing/coresight/coresight-tmc.h | 8 +- 3 files changed, 146 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index a7814e8e657b..42707b5b6349 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -229,6 +229,7 @@ static int tmc_prepare_crashdata(struct tmc_drvdata *dr= vdata) =20 static int tmc_read_prepare(struct tmc_drvdata *drvdata) { + struct ctcu_byte_cntr *byte_cntr_data =3D drvdata->byte_cntr_data; int ret =3D 0; =20 switch (drvdata->config_type) { @@ -237,7 +238,10 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdat= a) ret =3D tmc_read_prepare_etb(drvdata); break; case TMC_CONFIG_TYPE_ETR: - ret =3D tmc_read_prepare_etr(drvdata); + if (byte_cntr_data && byte_cntr_data->thresh_val) + ret =3D tmc_read_byte_cntr_prepare(drvdata); + else + ret =3D tmc_read_prepare_etr(drvdata); break; default: ret =3D -EINVAL; @@ -251,6 +255,7 @@ static int tmc_read_prepare(struct tmc_drvdata *drvdata) =20 static int tmc_read_unprepare(struct tmc_drvdata *drvdata) { + struct ctcu_byte_cntr *byte_cntr_data =3D drvdata->byte_cntr_data; int ret =3D 0; =20 switch (drvdata->config_type) { @@ -259,7 +264,10 @@ static int tmc_read_unprepare(struct tmc_drvdata *drvd= ata) ret =3D tmc_read_unprepare_etb(drvdata); break; case TMC_CONFIG_TYPE_ETR: - ret =3D tmc_read_unprepare_etr(drvdata); + if (byte_cntr_data && byte_cntr_data->thresh_val) + ret =3D tmc_read_byte_cntr_unprepare(drvdata); + else + ret =3D tmc_read_unprepare_etr(drvdata); break; default: ret =3D -EINVAL; @@ -290,11 +298,16 @@ static int tmc_open(struct inode *inode, struct file = *file) static inline ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos, size_t len, char **bufpp) { + struct ctcu_byte_cntr *byte_cntr_data =3D drvdata->byte_cntr_data; + switch (drvdata->config_type) { case TMC_CONFIG_TYPE_ETB: case TMC_CONFIG_TYPE_ETF: return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp); case TMC_CONFIG_TYPE_ETR: + if (byte_cntr_data && byte_cntr_data->thresh_val) + return tmc_byte_cntr_get_data(drvdata, &len, bufpp); + return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); } =20 @@ -308,6 +321,8 @@ static ssize_t tmc_read(struct file *file, char __user = *data, size_t len, ssize_t actual; struct tmc_drvdata *drvdata =3D container_of(file->private_data, struct tmc_drvdata, miscdev); + struct ctcu_byte_cntr *byte_cntr_data =3D drvdata->byte_cntr_data; + actual =3D tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp); if (actual <=3D 0) return 0; @@ -318,7 +333,15 @@ static ssize_t tmc_read(struct file *file, char __user= *data, size_t len, return -EFAULT; } =20 - *ppos +=3D actual; + if (byte_cntr_data && byte_cntr_data->thresh_val) { + byte_cntr_data->total_size +=3D actual; + if (byte_cntr_data->r_offset + actual >=3D drvdata->size) + byte_cntr_data->r_offset =3D 0; + else + byte_cntr_data->r_offset +=3D actual; + } else + *ppos +=3D actual; + dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual); =20 return actual; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index ed8a89fcd3fc..dd9c6b541b60 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -18,6 +18,7 @@ #include "coresight-etm-perf.h" #include "coresight-priv.h" #include "coresight-tmc.h" +#include "coresight-ctcu.h" =20 struct etr_flat_buf { struct device *dev; @@ -1148,6 +1149,77 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *drv= data, return rc; } =20 +/* Read the data from ETR's DDR buffer. */ +static ssize_t __tmc_byte_cntr_get_data(struct tmc_drvdata *drvdata, size_= t *len, + char **bufpp) +{ + struct ctcu_byte_cntr *byte_cntr_data =3D drvdata->byte_cntr_data; + size_t actual, bytes =3D byte_cntr_data->thresh_val; + struct etr_buf *etr_buf =3D drvdata->sysfs_buf; + long r_offset =3D byte_cntr_data->r_offset; + + if (*len >=3D bytes) + *len =3D bytes; + else if ((r_offset % bytes) + *len > bytes) + *len =3D bytes - (r_offset % bytes); + + actual =3D tmc_etr_buf_get_data(etr_buf, r_offset, *len, bufpp); + if (actual =3D=3D bytes || (actual + r_offset) % bytes =3D=3D 0) + atomic_dec(&byte_cntr_data->irq_cnt); + + return actual; +} + +/* Flush the remaining data in the ETR buffer after the byte-cntr has stop= ped. */ +static ssize_t tmc_byte_cntr_flush_buffer(struct tmc_drvdata *drvdata, siz= e_t len, + char **bufpp) +{ + struct ctcu_byte_cntr *byte_cntr_data =3D drvdata->byte_cntr_data; + struct etr_buf *etr_buf =3D drvdata->sysfs_buf; + long r_offset =3D byte_cntr_data->r_offset; + long w_offset =3D byte_cntr_data->w_offset; + ssize_t read_len =3D 0, remaining_len; + + if (w_offset < r_offset) + remaining_len =3D drvdata->size + w_offset - r_offset; + else + remaining_len =3D w_offset - r_offset; + + if (remaining_len > len) + remaining_len =3D len; + + if (remaining_len > 0) + read_len =3D tmc_etr_buf_get_data(etr_buf, r_offset, remaining_len, bufp= p); + + return read_len; +} + +ssize_t tmc_byte_cntr_get_data(struct tmc_drvdata *drvdata, size_t *len, c= har **bufpp) +{ + struct ctcu_byte_cntr *byte_cntr_data =3D drvdata->byte_cntr_data; + ssize_t read_len; + + /* + * Flush the remaining data in the ETR buffer based on the write + * offset of the ETR buffer when the byte cntr function has stopped. + */ + if (!byte_cntr_data->read_active || !byte_cntr_data->enable) { + read_len =3D tmc_byte_cntr_flush_buffer(drvdata, *len, bufpp); + if (read_len > 0) + return read_len; + + return -EINVAL; + } + + if (!atomic_read(&byte_cntr_data->irq_cnt)) + if (wait_event_interruptible(byte_cntr_data->wq, + atomic_read(&byte_cntr_data->irq_cnt) > 0 || + !byte_cntr_data->enable)) + return -ERESTARTSYS; + + return __tmc_byte_cntr_get_data(drvdata, len, bufpp); +} + /* * Return the available trace data in the buffer (starts at etr_buf->offse= t, * limited by etr_buf->len) from @pos, with a maximum limit of @len, @@ -1963,6 +2035,32 @@ const struct coresight_ops tmc_etr_cs_ops =3D { .panic_ops =3D &tmc_etr_sync_ops, }; =20 +int tmc_read_byte_cntr_prepare(struct tmc_drvdata *drvdata) +{ + struct ctcu_byte_cntr *byte_cntr_data =3D drvdata->byte_cntr_data; + long r_offset; + + if (byte_cntr_data->read_active) + return -EBUSY; + + /* + * The original r_offset is the w_offset of the ETR buffer at the + * start of the byte-cntr. + */ + r_offset =3D tmc_etr_get_rwp_offset(drvdata); + if (r_offset < 0) { + dev_err(&drvdata->csdev->dev, "failed to get r_offset\n"); + return r_offset; + } + + enable_irq_wake(byte_cntr_data->byte_cntr_irq); + byte_cntr_data->r_offset =3D r_offset; + byte_cntr_data->total_size =3D 0; + byte_cntr_data->read_active =3D true; + + return 0; +} + int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) { int ret =3D 0; @@ -1999,6 +2097,21 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) return ret; } =20 +int tmc_read_byte_cntr_unprepare(struct tmc_drvdata *drvdata) +{ + struct ctcu_byte_cntr *byte_cntr_data =3D drvdata->byte_cntr_data; + struct device *dev =3D &drvdata->csdev->dev; + + disable_irq_wake(byte_cntr_data->byte_cntr_irq); + atomic_set(&byte_cntr_data->irq_cnt, 0); + byte_cntr_data->read_active =3D false; + dev_dbg(dev, "send data total size: %llu bytes, r_offset: %ld w_offset: %= ld\n", + byte_cntr_data->total_size, byte_cntr_data->r_offset, + byte_cntr_data->w_offset); + + return 0; +} + int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata) { unsigned long flags; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 015592863352..1b838e4fc9e8 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -14,6 +14,8 @@ #include #include =20 +#include "coresight-ctcu.h" + #define TMC_RSZ 0x004 #define TMC_STS 0x00c #define TMC_RRD 0x010 @@ -334,11 +336,15 @@ ssize_t tmc_etb_get_sysfs_trace(struct tmc_drvdata *d= rvdata, /* ETR functions */ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata); int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata); +int tmc_read_prepare_etr(struct tmc_drvdata *drvdata); +int tmc_read_byte_cntr_prepare(struct tmc_drvdata *drvdata); +int tmc_read_byte_cntr_unprepare(struct tmc_drvdata *drvdata); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22ac7ccb596sm18801815ad.220.2025.04.09.18.34.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Apr 2025 18:34:08 -0700 (PDT) From: Jie Gan To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: Tingwei Zhang , Jinlong Mao , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 5/5] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device Date: Thu, 10 Apr 2025 09:33:30 +0800 Message-Id: <20250410013330.3609482-6-jie.gan@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250410013330.3609482-1-jie.gan@oss.qualcomm.com> References: <20250410013330.3609482-1-jie.gan@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=B5+50PtM c=1 sm=1 tr=0 ts=67f72012 cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=wB5yJZRArZ6K3lEFQq8A:9 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-GUID: z5yOKdrbsFRVuLL8S-S-JRheOJ7hWmTz X-Proofpoint-ORIG-GUID: z5yOKdrbsFRVuLL8S-S-JRheOJ7hWmTz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-09_06,2025-04-08_04,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=754 suspectscore=0 malwarescore=0 bulkscore=0 phishscore=0 spamscore=0 priorityscore=1501 adultscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504100010 Content-Type: text/plain; charset="utf-8" Add interrupts to enable byte-cntr function for TMC ETR devices. Signed-off-by: Jie Gan Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qc= om/sa8775p.dtsi index a904960359d7..b091e941aa21 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -2427,6 +2427,11 @@ ctcu@4001000 { clocks =3D <&aoss_qmp>; clock-names =3D "apb"; =20 + interrupts =3D , + ; + interrupt-names =3D "etr0", + "etr1"; + in-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1