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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Re-organize the platform support core into a gen1 catalog C file declaring common platform structure and include platform headers containing platform specific entries and iris_platform_data structure. The goal is to share most of the structure while having clear and separate per-SoC catalog files. The organization is based on the current drm/msm dpu1 catalog entries. Signed-off-by: Neil Armstrong Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/iris/Makefile | 2 +- .../media/platform/qcom/iris/iris_catalog_gen1.c | 83 ++++++++++++++++++= ++++ ...ris_platform_sm8250.c =3D> iris_catalog_sm8250.h} | 80 ++--------------= ----- 3 files changed, 89 insertions(+), 76 deletions(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 35390534534e93f4617c1036a05ca0921567ba1d..7e7bc5ca81e0f0119846ccaff7f= 79fd17b8298ca 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -25,7 +25,7 @@ qcom-iris-objs +=3D \ iris_vpu_common.o \ =20 ifeq ($(CONFIG_VIDEO_QCOM_VENUS),) -qcom-iris-objs +=3D iris_platform_sm8250.o +qcom-iris-objs +=3D iris_catalog_gen1.o endif =20 obj-$(CONFIG_VIDEO_QCOM_IRIS) +=3D qcom-iris.o diff --git a/drivers/media/platform/qcom/iris/iris_catalog_gen1.c b/drivers= /media/platform/qcom/iris/iris_catalog_gen1.c new file mode 100644 index 0000000000000000000000000000000000000000..c4590f8996431eb5103d45f01c6= bee2b38b848c2 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_catalog_gen1.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#include "iris_core.h" +#include "iris_ctrls.h" +#include "iris_platform_common.h" +#include "iris_resources.h" +#include "iris_hfi_gen1.h" +#include "iris_hfi_gen1_defines.h" +#include "iris_vpu_common.h" + +/* Common SM8250 & variants */ +static struct platform_inst_fw_cap inst_fw_cap_sm8250[] =3D { + { + .cap_id =3D PIPE, + .min =3D PIPE_1, + .max =3D PIPE_4, + .step_or_mask =3D 1, + .value =3D PIPE_4, + .hfi_id =3D HFI_PROPERTY_PARAM_WORK_ROUTE, + .set =3D iris_set_pipe, + }, + { + .cap_id =3D STAGE, + .min =3D STAGE_1, + .max =3D STAGE_2, + .step_or_mask =3D 1, + .value =3D STAGE_2, + .hfi_id =3D HFI_PROPERTY_PARAM_WORK_MODE, + .set =3D iris_set_stage, + }, + { + .cap_id =3D DEBLOCK, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + .hfi_id =3D HFI_PROPERTY_CONFIG_VDEC_POST_LOOP_DEBLOCKER, + .set =3D iris_set_u32, + }, +}; + +static struct platform_inst_caps platform_inst_cap_sm8250 =3D { + .min_frame_width =3D 128, + .max_frame_width =3D 8192, + .min_frame_height =3D 128, + .max_frame_height =3D 8192, + .max_mbpf =3D 138240, + .mb_cycles_vsp =3D 25, + .mb_cycles_vpp =3D 200, +}; + +static struct tz_cp_config tz_cp_config_sm8250 =3D { + .cp_start =3D 0, + .cp_size =3D 0x25800000, + .cp_nonpixel_start =3D 0x01000000, + .cp_nonpixel_size =3D 0x24800000, +}; + +static const u32 sm8250_vdec_input_config_param_default[] =3D { + HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE, + HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT, + HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_CONSTRAINTS_INFO, + HFI_PROPERTY_PARAM_BUFFER_COUNT_ACTUAL, + HFI_PROPERTY_PARAM_VDEC_MULTI_STREAM, + HFI_PROPERTY_PARAM_FRAME_SIZE, + HFI_PROPERTY_PARAM_BUFFER_SIZE_ACTUAL, + HFI_PROPERTY_PARAM_BUFFER_ALLOC_MODE, +}; + +static const u32 sm8250_dec_ip_int_buf_tbl[] =3D { + BUF_BIN, + BUF_SCRATCH_1, +}; + +static const u32 sm8250_dec_op_int_buf_tbl[] =3D { + BUF_DPB, +}; + +/* platforms catalogs */ +#include "iris_catalog_sm8250.h" diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_catalog_sm8250.h similarity index 59% rename from drivers/media/platform/qcom/iris/iris_platform_sm8250.c rename to drivers/media/platform/qcom/iris/iris_catalog_sm8250.h index 5c86fd7b7b6fd36dc2d57a1705d915308b4c0f92..4d2df669b3e1df2ef2b0d2f88fc= 5f309b27546db 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c +++ b/drivers/media/platform/qcom/iris/iris_catalog_sm8250.h @@ -1,55 +1,10 @@ -// SPDX-License-Identifier: GPL-2.0-only +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 -#include "iris_core.h" -#include "iris_ctrls.h" -#include "iris_platform_common.h" -#include "iris_resources.h" -#include "iris_hfi_gen1.h" -#include "iris_hfi_gen1_defines.h" -#include "iris_vpu_common.h" - -static struct platform_inst_fw_cap inst_fw_cap_sm8250[] =3D { - { - .cap_id =3D PIPE, - .min =3D PIPE_1, - .max =3D PIPE_4, - .step_or_mask =3D 1, - .value =3D PIPE_4, - .hfi_id =3D HFI_PROPERTY_PARAM_WORK_ROUTE, - .set =3D iris_set_pipe, - }, - { - .cap_id =3D STAGE, - .min =3D STAGE_1, - .max =3D STAGE_2, - .step_or_mask =3D 1, - .value =3D STAGE_2, - .hfi_id =3D HFI_PROPERTY_PARAM_WORK_MODE, - .set =3D iris_set_stage, - }, - { - .cap_id =3D DEBLOCK, - .min =3D 0, - .max =3D 1, - .step_or_mask =3D 1, - .value =3D 0, - .hfi_id =3D HFI_PROPERTY_CONFIG_VDEC_POST_LOOP_DEBLOCKER, - .set =3D iris_set_u32, - }, -}; - -static struct platform_inst_caps platform_inst_cap_sm8250 =3D { - .min_frame_width =3D 128, - .max_frame_width =3D 8192, - .min_frame_height =3D 128, - .max_frame_height =3D 8192, - .max_mbpf =3D 138240, - .mb_cycles_vsp =3D 25, - .mb_cycles_vpp =3D 200, -}; +#ifndef _IRIS_CATALOG_SM8250_H +#define _IRIS_CATALOG_SM8250_H =20 static void iris_set_sm8250_preset_registers(struct iris_core *core) { @@ -80,33 +35,6 @@ static const struct platform_clk_data sm8250_clk_table[]= =3D { {IRIS_HW_CLK, "vcodec0_core" }, }; =20 -static struct tz_cp_config tz_cp_config_sm8250 =3D { - .cp_start =3D 0, - .cp_size =3D 0x25800000, - .cp_nonpixel_start =3D 0x01000000, - .cp_nonpixel_size =3D 0x24800000, -}; - -static const u32 sm8250_vdec_input_config_param_default[] =3D { - HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE, - HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT, - HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_CONSTRAINTS_INFO, - HFI_PROPERTY_PARAM_BUFFER_COUNT_ACTUAL, - HFI_PROPERTY_PARAM_VDEC_MULTI_STREAM, - HFI_PROPERTY_PARAM_FRAME_SIZE, - HFI_PROPERTY_PARAM_BUFFER_SIZE_ACTUAL, - HFI_PROPERTY_PARAM_BUFFER_ALLOC_MODE, -}; - -static const u32 sm8250_dec_ip_int_buf_tbl[] =3D { - BUF_BIN, - BUF_SCRATCH_1, -}; - -static const u32 sm8250_dec_op_int_buf_tbl[] =3D { - BUF_DPB, -}; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Re-organize the platform support core into a gen2 catalog C file declaring common platform structure and include platform headers containing platform specific entries and iris_platform_data structure. The goal is to share most of the structure while having clear and separate per-SoC catalog files. The organization is based on the current drm/msm dpu1 catalog entries. Signed-off-by: Neil Armstrong Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/iris/Makefile | 2 +- ...{iris_platform_sm8550.c =3D> iris_catalog_gen2.c} | 84 +---------------= ---- .../media/platform/qcom/iris/iris_catalog_sm8550.h | 91 ++++++++++++++++++= ++++ 3 files changed, 95 insertions(+), 82 deletions(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 7e7bc5ca81e0f0119846ccaff7f79fd17b8298ca..379359c5c7e1e4ca39b1216335c= d8cf2317b6308 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -10,7 +10,7 @@ qcom-iris-objs +=3D \ iris_hfi_gen2_packet.o \ iris_hfi_gen2_response.o \ iris_hfi_queue.o \ - iris_platform_sm8550.o \ + iris_catalog_gen2.o \ iris_power.o \ iris_probe.o \ iris_resources.o \ diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.c b/driv= ers/media/platform/qcom/iris/iris_catalog_gen2.c similarity index 61% rename from drivers/media/platform/qcom/iris/iris_platform_sm8550.c rename to drivers/media/platform/qcom/iris/iris_catalog_gen2.c index 35d278996c430f2856d0fe59586930061a271c3e..c3f8ad004cb7f9317859b259464= 0c7138dbb6534 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8550.c +++ b/drivers/media/platform/qcom/iris/iris_catalog_gen2.c @@ -10,8 +10,7 @@ #include "iris_platform_common.h" #include "iris_vpu_common.h" =20 -#define VIDEO_ARCH_LX 1 - +/* Common SM8550 & variants */ static struct platform_inst_fw_cap inst_fw_cap_sm8550[] =3D { { .cap_id =3D PROFILE, @@ -132,35 +131,6 @@ static struct platform_inst_caps platform_inst_cap_sm8= 550 =3D { .num_comv =3D 0, }; =20 -static void iris_set_sm8550_preset_registers(struct iris_core *core) -{ - writel(0x0, core->reg_base + 0xB0088); -} - -static const struct icc_info sm8550_icc_table[] =3D { - { "cpu-cfg", 1000, 1000 }, - { "video-mem", 1000, 15000000 }, -}; - -static const char * const sm8550_clk_reset_table[] =3D { "bus" }; - -static const struct bw_info sm8550_bw_table_dec[] =3D { - { ((4096 * 2160) / 256) * 60, 1608000 }, - { ((4096 * 2160) / 256) * 30, 826000 }, - { ((1920 * 1080) / 256) * 60, 567000 }, - { ((1920 * 1080) / 256) * 30, 294000 }, -}; - -static const char * const sm8550_pmdomain_table[] =3D { "venus", "vcodec0"= }; - -static const char * const sm8550_opp_pd_table[] =3D { "mxc", "mmcx" }; - -static const struct platform_clk_data sm8550_clk_table[] =3D { - {IRIS_AXI_CLK, "iface" }, - {IRIS_CTRL_CLK, "core" }, - {IRIS_HW_CLK, "vcodec0_core" }, -}; - static struct ubwc_config_data ubwc_config_sm8550 =3D { .max_channels =3D 8, .mal_length =3D 32, @@ -214,53 +184,5 @@ static const u32 sm8550_dec_op_int_buf_tbl[] =3D { BUF_DPB, }; =20 -struct iris_platform_data sm8550_data =3D { - .get_instance =3D iris_hfi_gen2_get_instance, - .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, - .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, - .vpu_ops =3D &iris_vpu3_ops, - .set_preset_registers =3D iris_set_sm8550_preset_registers, - .icc_tbl =3D sm8550_icc_table, - .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), - .clk_rst_tbl =3D sm8550_clk_reset_table, - .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), - .bw_tbl_dec =3D sm8550_bw_table_dec, - .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), - .pmdomain_tbl =3D sm8550_pmdomain_table, - .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), - .opp_pd_tbl =3D sm8550_opp_pd_table, - .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), - .clk_tbl =3D sm8550_clk_table, - .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), - /* Upper bound of DMA address range */ - .dma_mask =3D 0xe0000000 - 1, - .fwname =3D "qcom/vpu/vpu30_p4.mbn", - .pas_id =3D IRIS_PAS_ID, - .inst_caps =3D &platform_inst_cap_sm8550, - .inst_fw_caps =3D inst_fw_cap_sm8550, - .inst_fw_caps_size =3D ARRAY_SIZE(inst_fw_cap_sm8550), - .tz_cp_config_data =3D &tz_cp_config_sm8550, - .core_arch =3D VIDEO_ARCH_LX, - .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, - .ubwc_config =3D &ubwc_config_sm8550, - .num_vpp_pipe =3D 4, - .max_session_count =3D 16, - .max_core_mbpf =3D ((8192 * 4352) / 256) * 2, - .input_config_params =3D - sm8550_vdec_input_config_params, - .input_config_params_size =3D - ARRAY_SIZE(sm8550_vdec_input_config_params), - .output_config_params =3D - sm8550_vdec_output_config_params, - .output_config_params_size =3D - ARRAY_SIZE(sm8550_vdec_output_config_params), - .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, - .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), - .dec_output_prop =3D sm8550_vdec_subscribe_output_properties, - .dec_output_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_output_propert= ies), - - .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, - .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), - .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, - .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), -}; +/* platforms catalogs */ +#include "iris_catalog_sm8550.h" diff --git a/drivers/media/platform/qcom/iris/iris_catalog_sm8550.h b/drive= rs/media/platform/qcom/iris/iris_catalog_sm8550.h new file mode 100644 index 0000000000000000000000000000000000000000..e101eed6568bfc7c62651491daa= d0e9e5b0224e5 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_catalog_sm8550.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#ifndef _IRIS_CATALOG_SM8550_H +#define _IRIS_CATALOG_SM8550_H + +#define VIDEO_ARCH_LX 1 + +static void iris_set_sm8550_preset_registers(struct iris_core *core) +{ + writel(0x0, core->reg_base + 0xB0088); +} + +static const struct icc_info sm8550_icc_table[] =3D { + { "cpu-cfg", 1000, 1000 }, + { "video-mem", 1000, 15000000 }, +}; + +static const char * const sm8550_clk_reset_table[] =3D { "bus" }; + +static const struct bw_info sm8550_bw_table_dec[] =3D { + { ((4096 * 2160) / 256) * 60, 1608000 }, + { ((4096 * 2160) / 256) * 30, 826000 }, + { ((1920 * 1080) / 256) * 60, 567000 }, + { ((1920 * 1080) / 256) * 30, 294000 }, +}; + +static const char * const sm8550_pmdomain_table[] =3D { "venus", "vcodec0"= }; + +static const char * const sm8550_opp_pd_table[] =3D { "mxc", "mmcx" }; + +static const struct platform_clk_data sm8550_clk_table[] =3D { + {IRIS_AXI_CLK, "iface" }, + {IRIS_CTRL_CLK, "core" }, + {IRIS_HW_CLK, "vcodec0_core" }, +}; + +struct iris_platform_data sm8550_data =3D { + .get_instance =3D iris_hfi_gen2_get_instance, + .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, + .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, + .vpu_ops =3D &iris_vpu3_ops, + .set_preset_registers =3D iris_set_sm8550_preset_registers, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D sm8550_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8550_clk_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D sm8550_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu30_p4.mbn", + .pas_id =3D IRIS_PAS_ID, + .inst_caps =3D &platform_inst_cap_sm8550, + .inst_fw_caps =3D inst_fw_cap_sm8550, + .inst_fw_caps_size =3D ARRAY_SIZE(inst_fw_cap_sm8550), + .tz_cp_config_data =3D &tz_cp_config_sm8550, + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .ubwc_config =3D &ubwc_config_sm8550, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D ((8192 * 4352) / 256) * 2, + .input_config_params =3D + sm8550_vdec_input_config_params, + .input_config_params_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_params), + .output_config_params =3D + sm8550_vdec_output_config_params, + .output_config_params_size =3D + ARRAY_SIZE(sm8550_vdec_output_config_params), + .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, + .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), + .dec_output_prop =3D sm8550_vdec_subscribe_output_properties, + .dec_output_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_output_propert= ies), + + .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), +}; 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Thu, 10 Apr 2025 09:30:11 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39d8936129dsm5350663f8f.18.2025.04.10.09.30.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Apr 2025 09:30:10 -0700 (PDT) From: Neil Armstrong Date: Thu, 10 Apr 2025 18:30:02 +0200 Subject: [PATCH RFC v5 3/8] dt-bindings: media: qcom,sm8550-iris: document SM8650 IRIS accelerator Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250410-topic-sm8x50-upstream-iris-catalog-v5-3-44a431574c25@linaro.org> References: <20250410-topic-sm8x50-upstream-iris-catalog-v5-0-44a431574c25@linaro.org> In-Reply-To: <20250410-topic-sm8x50-upstream-iris-catalog-v5-0-44a431574c25@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Document the IRIS video decoder and encoder accelerator found in the SM8650 platform, it requires 2 more reset lines in addition to the properties required for the SM8550 platform. Reviewed-by: Rob Herring (Arm) Reviewed-by: Vikash Garodia Reviewed-by: Bryan O'Donoghue Tested-by: Bryan O'Donoghue # x1e Dell Signed-off-by: Neil Armstrong --- .../bindings/media/qcom,sm8550-iris.yaml | 33 ++++++++++++++++++= ---- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml = b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml index e424ea84c211f473a799481fd5463a16580187ed..536cf458dcb08141e5a1ec8c3df= 964196e599a57 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml @@ -14,12 +14,11 @@ description: The iris video processing unit is a video encode and decode accelerator present on Qualcomm platforms. =20 -allOf: - - $ref: qcom,venus-common.yaml# - properties: compatible: - const: qcom,sm8550-iris + enum: + - qcom,sm8550-iris + - qcom,sm8650-iris =20 power-domains: maxItems: 4 @@ -49,11 +48,15 @@ properties: - const: video-mem =20 resets: - maxItems: 1 + minItems: 1 + maxItems: 3 =20 reset-names: + minItems: 1 items: - const: bus + - const: xo + - const: core =20 iommus: maxItems: 2 @@ -75,6 +78,26 @@ required: - iommus - dma-coherent =20 +allOf: + - $ref: qcom,venus-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm8650-iris + then: + properties: + resets: + minItems: 3 + reset-names: + minItems: 3 + else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 + unevaluatedProperties: false =20 examples: --=20 2.34.1 From nobody Fri Dec 19 08:08:57 2025 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3A291EFF9A for ; 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Thu, 10 Apr 2025 09:30:11 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39d8936129dsm5350663f8f.18.2025.04.10.09.30.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Apr 2025 09:30:11 -0700 (PDT) From: Neil Armstrong Date: Thu, 10 Apr 2025 18:30:03 +0200 Subject: [PATCH RFC v5 4/8] media: platform: qcom/iris: add power_off_controller to vpu_ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250410-topic-sm8x50-upstream-iris-catalog-v5-4-44a431574c25@linaro.org> References: <20250410-topic-sm8x50-upstream-iris-catalog-v5-0-44a431574c25@linaro.org> In-Reply-To: <20250410-topic-sm8x50-upstream-iris-catalog-v5-0-44a431574c25@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE In order to support the SM8650 iris33 hardware, we need to provide a specific constoller power off sequences via the vpu_ops callbacks. Add the callback, and use the current helper for currently supported platforms. Reviewed-by: Bryan O'Donoghue Reviewed-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e Dell Reviewed-by: Vikash Garodia Signed-off-by: Neil Armstrong --- drivers/media/platform/qcom/iris/iris_vpu2.c | 1 + drivers/media/platform/qcom/iris/iris_vpu3.c | 1 + drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 ++-- drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 ++ 4 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/p= latform/qcom/iris/iris_vpu2.c index 8f502aed43ce2fa6a272a2ce14ff1ca54d3e63a2..7cf1bfc352d34b897451061b5c1= 4fbe90276433d 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c @@ -34,5 +34,6 @@ static u64 iris_vpu2_calc_freq(struct iris_inst *inst, si= ze_t data_size) =20 const struct vpu_ops iris_vpu2_ops =3D { .power_off_hw =3D iris_vpu_power_off_hw, + .power_off_controller =3D iris_vpu_power_off_controller, .calc_freq =3D iris_vpu2_calc_freq, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu3.c b/drivers/media/p= latform/qcom/iris/iris_vpu3.c index b484638e6105a69319232f667ee7ae95e3853698..13dab61427b8bd0491b69a9bc5f= 5144d27d17362 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3.c @@ -118,5 +118,6 @@ static u64 iris_vpu3_calculate_frequency(struct iris_in= st *inst, size_t data_siz =20 const struct vpu_ops iris_vpu3_ops =3D { .power_off_hw =3D iris_vpu3_power_off_hardware, + .power_off_controller =3D iris_vpu_power_off_controller, .calc_freq =3D iris_vpu3_calculate_frequency, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index fe9896d66848cdcd8c67bd45bbf3b6ce4a01ab10..268e45acaa7c0e3fe237123c62f= 0133d9dface14 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -211,7 +211,7 @@ int iris_vpu_prepare_pc(struct iris_core *core) return -EAGAIN; } =20 -static int iris_vpu_power_off_controller(struct iris_core *core) +int iris_vpu_power_off_controller(struct iris_core *core) { u32 val =3D 0; int ret; @@ -264,7 +264,7 @@ void iris_vpu_power_off(struct iris_core *core) { dev_pm_opp_set_rate(core->dev, 0); core->iris_platform_data->vpu_ops->power_off_hw(core); - iris_vpu_power_off_controller(core); + core->iris_platform_data->vpu_ops->power_off_controller(core); iris_unset_icc_bw(core); =20 if (!iris_vpu_watchdog(core, core->intr_status)) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index 63fa1fa5a4989e48aebdb6c7619c140000c0b44c..f8965661c602f990d5a7057565f= 79df4112d097e 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -13,6 +13,7 @@ extern const struct vpu_ops iris_vpu3_ops; =20 struct vpu_ops { void (*power_off_hw)(struct iris_core *core); + int (*power_off_controller)(struct iris_core *core); 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Introduce an optional controller_rst_tbl use to store reset lines used to reset part of the controller. This is necessary for the vpu3 support, when the xo reset line must be asserted separately from the other reset line on power off operation. Factor the iris_init_resets() logic to allow requesting multiple reset tables. Reviewed-by: Bryan O'Donoghue Tested-by: Bryan O'Donoghue # x1e Dell Signed-off-by: Neil Armstrong --- drivers/media/platform/qcom/iris/iris_core.h | 1 + .../platform/qcom/iris/iris_platform_common.h | 2 ++ drivers/media/platform/qcom/iris/iris_probe.c | 39 +++++++++++++++---= ---- 3 files changed, 30 insertions(+), 12 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/p= latform/qcom/iris/iris_core.h index 37fb4919fecc62182784b4dca90fcab47dd38a80..78143855b277cd3ebdc7a1e7f35= f6df284aa364c 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -82,6 +82,7 @@ struct iris_core { struct clk_bulk_data *clock_tbl; u32 clk_count; struct reset_control_bulk_data *resets; + struct reset_control_bulk_data *controller_resets; const struct iris_platform_data *iris_platform_data; enum iris_core_state state; dma_addr_t iface_q_table_daddr; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index f6b15d2805fb2004699709bb12cd7ce9b052180c..fdd40fd80178c4c66b37e392d07= a0a62f492f108 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -156,6 +156,8 @@ struct iris_platform_data { unsigned int clk_tbl_size; const char * const *clk_rst_tbl; unsigned int clk_rst_tbl_size; + const char * const *controller_rst_tbl; + unsigned int controller_rst_tbl_size; u64 dma_mask; const char *fwname; u32 pas_id; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index aca442dcc153830e6252d1dca87afb38c0b9eb8f..4f8bce6e2002bffee4c93dcaaf6= e52bf4e40992e 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -91,25 +91,40 @@ static int iris_init_clocks(struct iris_core *core) return 0; } =20 -static int iris_init_resets(struct iris_core *core) +static int iris_init_reset_table(struct iris_core *core, + struct reset_control_bulk_data **resets, + const char * const *rst_tbl, u32 rst_tbl_size) { - const char * const *rst_tbl; - u32 rst_tbl_size; u32 i =3D 0; =20 - rst_tbl =3D core->iris_platform_data->clk_rst_tbl; - rst_tbl_size =3D core->iris_platform_data->clk_rst_tbl_size; - - core->resets =3D devm_kzalloc(core->dev, - sizeof(*core->resets) * rst_tbl_size, - GFP_KERNEL); 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Thu, 10 Apr 2025 09:30:13 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39d8936129dsm5350663f8f.18.2025.04.10.09.30.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Apr 2025 09:30:13 -0700 (PDT) From: Neil Armstrong Date: Thu, 10 Apr 2025 18:30:05 +0200 Subject: [PATCH RFC v5 6/8] media: platform: qcom/iris: rename iris_vpu3 to iris_vpu3x Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250410-topic-sm8x50-upstream-iris-catalog-v5-6-44a431574c25@linaro.org> References: <20250410-topic-sm8x50-upstream-iris-catalog-v5-0-44a431574c25@linaro.org> In-Reply-To: <20250410-topic-sm8x50-upstream-iris-catalog-v5-0-44a431574c25@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The vpu33 HW is very close to vpu3, and shares most of the operations, so rename file to vpu3x since we'll handle all vpu3 variants in it. Reviewed-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e Dell Reviewed-by: Vikash Garodia Signed-off-by: Neil Armstrong Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/iris/Makefile | 2 +- drivers/media/platform/qcom/iris/{iris_vpu3.c =3D> iris_vpu3x.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 379359c5c7e1e4ca39b1216335cd8cf2317b6308..15ca63084ddc5c5ca34a79ff370= 64c5f7c5bfa7e 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -20,7 +20,7 @@ qcom-iris-objs +=3D \ iris_vb2.o \ iris_vdec.o \ iris_vpu2.o \ - iris_vpu3.o \ + iris_vpu3x.o \ iris_vpu_buffer.o \ iris_vpu_common.o \ =20 diff --git a/drivers/media/platform/qcom/iris/iris_vpu3.c b/drivers/media/p= latform/qcom/iris/iris_vpu3x.c similarity index 100% rename from drivers/media/platform/qcom/iris/iris_vpu3.c rename to drivers/media/platform/qcom/iris/iris_vpu3x.c --=20 2.34.1 From nobody Fri Dec 19 08:08:57 2025 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09DA11EEA28 for ; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The IRIS acceleration found in the SM8650 platforms uses the vpu33 hardware version, and requires a slighly different reset and power off sequences in order to properly get out of runtime suspend. Tested-by: Bryan O'Donoghue # x1e Dell Signed-off-by: Neil Armstrong Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 160 +++++++++++++++++= +++- drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + 2 files changed, 157 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index 13dab61427b8bd0491b69a9bc5f5144d27d17362..9b7c9a1495ee2f51c60b1142b2e= d4680ff798f0a 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -4,20 +4,39 @@ */ =20 #include +#include =20 #include "iris_instance.h" #include "iris_vpu_common.h" #include "iris_vpu_register_defines.h" =20 +#define WRAPPER_TZ_BASE_OFFS 0x000C0000 +#define AON_BASE_OFFS 0x000E0000 #define AON_MVP_NOC_RESET 0x0001F000 =20 +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54) +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) +#define REQ_POWER_DOWN_PREP BIT(0) +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) #define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) #define CORE_CLK_RUN 0x0 =20 +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14) +#define CTL_AXI_CLK_HALT BIT(0) +#define CTL_CLK_HALT BIT(1) + +#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18) +#define RESET_HIGH BIT(0) + #define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) #define CORE_BRIDGE_SW_RESET BIT(0) #define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) =20 +#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) +#define MSK_SIGNAL_FROM_TENSILICA BIT(0) +#define MSK_CORE_POWER_ON BIT(1) + #define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) #define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1)) =20 @@ -25,7 +44,16 @@ =20 #define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) =20 -static bool iris_vpu3_hw_power_collapsed(struct iris_core *core) +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) + +#define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18) +#define SW_RESET BIT(0) +#define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20) +#define NOC_HALT BIT(0) +#define AON_WRAPPER_SPARE (AON_BASE_OFFS + 0x28) + +static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core) { u32 value, pwr_status; =20 @@ -40,7 +68,7 @@ static void iris_vpu3_power_off_hardware(struct iris_core= *core) u32 reg_val =3D 0, value, i; int ret; =20 - if (iris_vpu3_hw_power_collapsed(core)) + if (iris_vpu3x_hw_power_collapsed(core)) goto disable_power; =20 dev_err(core->dev, "video hw is power on\n"); @@ -79,7 +107,125 @@ static void iris_vpu3_power_off_hardware(struct iris_c= ore *core) iris_vpu_power_off_hw(core); } =20 -static u64 iris_vpu3_calculate_frequency(struct iris_inst *inst, size_t da= ta_size) +static void iris_vpu33_power_off_hardware(struct iris_core *core) +{ + u32 reg_val =3D 0, value, i; + int ret; + + if (iris_vpu3x_hw_power_collapsed(core)) + goto disable_power; + + dev_err(core->dev, "video hw is power on\n"); + + value =3D readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + if (value) + writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + + for (i =3D 0; i < core->iris_platform_data->num_vpp_pipe; i++) { + ret =3D readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN + 4 *= i, + reg_val, reg_val & 0x400000, 2000, 20000); + if (ret) + goto disable_power; + } + + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATU= S, + reg_val, reg_val & BIT(0), 200, 2000); + if (ret) + goto disable_power; + + /* set MNoC to low power, set PD_NOC_QREQ (bit 0) */ + writel(BIT(0), core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + + writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, + core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_S= YNC_RESET); + writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + +disable_power: + iris_vpu_power_off_hw(core); +} + +static int iris_vpu33_power_off_controller(struct iris_core *core) +{ + u32 xo_rst_tbl_size =3D core->iris_platform_data->controller_rst_tbl_size; + u32 clk_rst_tbl_size =3D core->iris_platform_data->clk_rst_tbl_size; + u32 val =3D 0; + int ret; + + writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CP= U_CS_X2RPMH); + + writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CON= TROL); + + ret =3D readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STAT= US, + val, val & BIT(0), 200, 2000); + if (ret) + goto disable_power; + + writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL); + + ret =3D readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STAT= US, + val, val =3D=3D 0, 200, 2000); + if (ret) + goto disable_power; + + writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT, + core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); + writel(RESET_HIGH, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET); + writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET); + writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); + + reset_control_bulk_reset(clk_rst_tbl_size, core->resets); + + /* Disable MVP NoC clock */ + val =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + val |=3D NOC_HALT; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + + /* enable MVP NoC reset */ + val =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + val |=3D SW_RESET; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + + /* poll AON spare register bit0 to become zero with 50ms timeout */ + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_SPARE, + val, (val & BIT(0)) =3D=3D 0, 1000, 50000); + if (ret) + goto disable_power; + + /* enable bit(1) to avoid cvp noc xo reset */ + val =3D readl(core->reg_base + AON_WRAPPER_SPARE); + val |=3D BIT(1); + writel(val, core->reg_base + AON_WRAPPER_SPARE); + + reset_control_bulk_assert(xo_rst_tbl_size, core->controller_resets); + + /* De-assert MVP NoC reset */ + val =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + val &=3D ~SW_RESET; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + + usleep_range(80, 100); + + reset_control_bulk_deassert(xo_rst_tbl_size, core->controller_resets); + + /* reset AON spare register */ + writel(0, core->reg_base + AON_WRAPPER_SPARE); + + /* Enable MVP NoC clock */ + val =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + val &=3D ~NOC_HALT; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); + +disable_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + + return 0; +} + +static u64 iris_vpu3x_calculate_frequency(struct iris_inst *inst, size_t d= ata_size) { struct platform_inst_caps *caps =3D inst->core->iris_platform_data->inst_= caps; struct v4l2_format *inp_f =3D inst->fmt_src; @@ -119,5 +265,11 @@ static u64 iris_vpu3_calculate_frequency(struct iris_i= nst *inst, size_t data_siz const struct vpu_ops iris_vpu3_ops =3D { .power_off_hw =3D iris_vpu3_power_off_hardware, .power_off_controller =3D iris_vpu_power_off_controller, - .calc_freq =3D iris_vpu3_calculate_frequency, + .calc_freq =3D iris_vpu3x_calculate_frequency, +}; + +const struct vpu_ops iris_vpu33_ops =3D { + .power_off_hw =3D iris_vpu33_power_off_hardware, + .power_off_controller =3D iris_vpu33_power_off_controller, + .calc_freq =3D iris_vpu3x_calculate_frequency, }; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add support for the SM8650 platform by re-using the SM8550 definitions and using the vpu33 ops. The SM8650/vpu33 requires more reset lines, but the H.264 decoder capabilities are identical. Tested-by: Bryan O'Donoghue # x1e Dell Signed-off-by: Neil Armstrong Reviewed-by: Bryan O'Donoghue --- .../media/platform/qcom/iris/iris_catalog_gen2.c | 1 + .../media/platform/qcom/iris/iris_catalog_sm8650.h | 68 ++++++++++++++++++= ++++ .../platform/qcom/iris/iris_platform_common.h | 1 + drivers/media/platform/qcom/iris/iris_probe.c | 4 ++ 4 files changed, 74 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_catalog_gen2.c b/drivers= /media/platform/qcom/iris/iris_catalog_gen2.c index c3f8ad004cb7f9317859b2594640c7138dbb6534..ad559351f1125d266dedac7eb6e= 91cda90bbae72 100644 --- a/drivers/media/platform/qcom/iris/iris_catalog_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_catalog_gen2.c @@ -186,3 +186,4 @@ static const u32 sm8550_dec_op_int_buf_tbl[] =3D { =20 /* platforms catalogs */ #include "iris_catalog_sm8550.h" +#include "iris_catalog_sm8650.h" diff --git a/drivers/media/platform/qcom/iris/iris_catalog_sm8650.h b/drive= rs/media/platform/qcom/iris/iris_catalog_sm8650.h new file mode 100644 index 0000000000000000000000000000000000000000..be8737dd4f3d9ec20a457d50076= be1b4d841787c --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_catalog_sm8650.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#ifndef _IRIS_CATALOG_SM8650_H +#define _IRIS_CATALOG_SM8650_H + +#define VIDEO_ARCH_LX 1 + +static const char * const sm8650_clk_reset_table[] =3D { "bus", "core" }; + +static const char * const sm8650_controller_reset_table[] =3D { "xo" }; + +struct iris_platform_data sm8650_data =3D { + .get_instance =3D iris_hfi_gen2_get_instance, + .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, + .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, + .vpu_ops =3D &iris_vpu33_ops, + .set_preset_registers =3D iris_set_sm8550_preset_registers, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D sm8650_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8650_clk_reset_table), + .controller_rst_tbl =3D sm8650_controller_reset_table, + .controller_rst_tbl_size =3D ARRAY_SIZE(sm8650_controller_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D sm8550_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu33_p4.mbn", + .pas_id =3D IRIS_PAS_ID, + .inst_caps =3D &platform_inst_cap_sm8550, + .inst_fw_caps =3D inst_fw_cap_sm8550, + .inst_fw_caps_size =3D ARRAY_SIZE(inst_fw_cap_sm8550), + .tz_cp_config_data =3D &tz_cp_config_sm8550, + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .ubwc_config =3D &ubwc_config_sm8550, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D ((8192 * 4352) / 256) * 2, + .input_config_params =3D + sm8550_vdec_input_config_params, + .input_config_params_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_params), + .output_config_params =3D + sm8550_vdec_output_config_params, + .output_config_params_size =3D + ARRAY_SIZE(sm8550_vdec_output_config_params), + .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, + .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), + .dec_output_prop =3D sm8550_vdec_subscribe_output_properties, + .dec_output_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_output_propert= ies), + + .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), +}; + +#endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index fdd40fd80178c4c66b37e392d07a0a62f492f108..6bc3a7975b04d612f6c89206eae= 95dac678695fc 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -35,6 +35,7 @@ enum pipe_type { =20 extern struct iris_platform_data sm8250_data; extern struct iris_platform_data sm8550_data; +extern struct iris_platform_data sm8650_data; =20 enum platform_clk_type { IRIS_AXI_CLK, diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index 4f8bce6e2002bffee4c93dcaaf6e52bf4e40992e..7cd8650fbe9c09598670530103e= 3d5edf32953e7 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -345,6 +345,10 @@ static const struct of_device_id iris_dt_match[] =3D { .data =3D &sm8250_data, }, #endif + { + .compatible =3D "qcom,sm8650-iris", + .data =3D &sm8650_data, + }, { }, }; MODULE_DEVICE_TABLE(of, iris_dt_match); --=20 2.34.1