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Thu, 10 Apr 2025 10:55:32 +0100 (BST) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.6.134) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 10 Apr 2025 10:55:30 +0100 From: Matt Coster Date: Thu, 10 Apr 2025 10:55:17 +0100 Subject: [PATCH DO NOT MERGE v6 18/18] arm64: dts: ti: k3-j721s2: Add GPU node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250410-sets-bxs-4-64-patch-v1-v6-18-eda620c5865f@imgtec.com> References: <20250410-sets-bxs-4-64-patch-v1-v6-0-eda620c5865f@imgtec.com> In-Reply-To: <20250410-sets-bxs-4-64-patch-v1-v6-0-eda620c5865f@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge , "Michal Wilczynski" , Alessio Belle , Alexandru Dadu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2186; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=1O63fHvP1rG7PVltXz7KlpJwSIz+erZooO4dk0p95co=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaR/n9p8a0HOjOfKd+NWnMyoj+i6HMs3OW+y5ETJk9dOT o1o9bv4raOUhUGMg0FWTJFlxwrLFWp/1LQkbvwqhpnDygQyhIGLUwAm4tjOyLDuy3Xvh0Gia8+K TN2kb6+TMPHZ9cayNX6T/q90X7flXuUzhv/BVVs+u+jcNVhm7Hnmfa9g9qOclrpffy0fiJ1k2PX 1hRgzAA== X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Authority-Analysis: v=2.4 cv=MLNgmNZl c=1 sm=1 tr=0 ts=67f79594 cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=UtEzwyU9vMAA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=sozttTNsAAAA:8 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=hJ1mkiiSfvO0DrLeNb8A:9 a=QEXdDO2ut3YA:10 a=S-JV1fTmrHgA:10 a=j2-svP0xy3wA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: N5519SmxWGqsd3s5LI3Y6WBlzLJsD_E8 X-Proofpoint-ORIG-GUID: N5519SmxWGqsd3s5LI3Y6WBlzLJsD_E8 The J721S2 binding is based on the TI downstream binding in 54b0f2a00d92 ("arm64: dts: ti: k3-j721s2-main: add gpu node") from [1] but with updated compatible strings. The clock[2] and power[3] indices were verified from docs, but the source of the interrupt index remains elusive. [1]: https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel [2]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/clocks.html [3]: https://downloads.ti.com/tisci/esd/latest/5_soc_doc/j721s2/devices.html Signed-off-by: Matt Coster --- Changes in v6: - None - Link to v5: https://lore.kernel.org/r/20250326-sets-bxs-4-64-patch-v1-v5-= 18-e4c46e8280a9@imgtec.com Changes in v5: - None - Link to v4: https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-= 18-d987cf4ca439@imgtec.com Changes in v4: - None - Link to v3: https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-= 18-143b3dbef02f@imgtec.com Changes in v3: - None - Link to v2: https://lore.kernel.org/r/20241118-sets-bxs-4-64-patch-v1-v2-= 21-3fd45d9fb0cf@imgtec.com Changes in v2: - Use normal reg syntax for 64-bit values - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 21-4ed30e865892@imgtec.com --- arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/d= ts/ti/k3-j721s2-main.dtsi index 92bf48fdbeba45ecca8c854db5f72fd3666239c5..a79ac41b2c1f51b7193e6133864= 428bd35a5e835 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -2048,4 +2048,16 @@ watchdog8: watchdog@23f0000 { /* reserved for MAIN_R5F1_1 */ status =3D "reserved"; }; + + gpu: gpu@4e20000000 { + compatible =3D "ti,j721s2-gpu", "img,img-bxs-4-64", "img,img-rogue"; + reg =3D <0x4e 0x20000000 0x00 0x80000>; + clocks =3D <&k3_clks 130 1>; + clock-names =3D "core"; + interrupts =3D ; + power-domains =3D <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 373 TI_SCI_PD_EXCLUSIVE>; + power-domain-names =3D "a", "b"; + dma-coherent; + }; }; --=20 2.49.0