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Thu, 10 Apr 2025 10:55:27 +0100 (BST) Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa (172.25.6.134) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Thu, 10 Apr 2025 10:55:24 +0100 From: Matt Coster Date: Thu, 10 Apr 2025 10:55:10 +0100 Subject: [PATCH v6 11/18] drm/imagination: Use a lookup table for fw defs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250410-sets-bxs-4-64-patch-v1-v6-11-eda620c5865f@imgtec.com> References: <20250410-sets-bxs-4-64-patch-v1-v6-0-eda620c5865f@imgtec.com> In-Reply-To: <20250410-sets-bxs-4-64-patch-v1-v6-0-eda620c5865f@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge , "Michal Wilczynski" , Alessio Belle , Alexandru Dadu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3937; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=4jkPAyYdwNoLCo7GjAAli7ATT33RV/WwXY0qHasYKqo=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaR/n9o0cd8FyS8sFwQPlQcIrdC4u/HNo5572v+qoi7n1 P3O5ezy7ChlYRDjYJAVU2TZscJyhdofNS2JG7+KYeawMoEMYeDiFICJ2H5i+Ke/pSsoNi/nZ/qM FzurmVdtnhzIXdYw5SFLtsfFtbtrix4yMszdMv9fzG+vfWtU393Z1865qqkmxkXyj6j6vrylTgs 2/uMCAA== X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Authority-Analysis: v=2.4 cv=MLNgmNZl c=1 sm=1 tr=0 ts=67f7958f cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=UtEzwyU9vMAA:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=iYL5nd4a90DRai7o0HQA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 X-Proofpoint-GUID: bThOd9AZWJK-0uluZi-NeFm8Sw4f7kFx X-Proofpoint-ORIG-GUID: bThOd9AZWJK-0uluZi-NeFm8Sw4f7kFx With more than two firmware processor types, the if/else chain in pvr_fw_init() gets a bit ridiculous. Use a static array indexed on pvr_fw_processor_type (which is now a proper enum instead of #defines) instead. Signed-off-by: Matt Coster Reviewed-by: Frank Binns --- Changes in v6: - Add Frank's Rb - Link to v5: https://lore.kernel.org/r/20250326-sets-bxs-4-64-patch-v1-v5-= 11-e4c46e8280a9@imgtec.com Changes in v5: - None - Link to v4: https://lore.kernel.org/r/20250320-sets-bxs-4-64-patch-v1-v4-= 11-d987cf4ca439@imgtec.com Changes in v4: - None - Link to v3: https://lore.kernel.org/r/20250310-sets-bxs-4-64-patch-v1-v3-= 11-143b3dbef02f@imgtec.com Changes in v3: - None - Link to v2: https://lore.kernel.org/r/20241118-sets-bxs-4-64-patch-v1-v2-= 13-3fd45d9fb0cf@imgtec.com Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 13-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_device.h | 4 ---- drivers/gpu/drm/imagination/pvr_fw.c | 21 ++++++++++++++++----- drivers/gpu/drm/imagination/pvr_fw.h | 7 +++++++ 3 files changed, 23 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/ima= gination/pvr_device.h index 6c01d96657de6dc3904ef5ca28365f06cfe0f40b..12bf0b9e5bfb48ef9e5ed9faa44= e0896b7555f49 100644 --- a/drivers/gpu/drm/imagination/pvr_device.h +++ b/drivers/gpu/drm/imagination/pvr_device.h @@ -739,8 +739,4 @@ pvr_ioctl_union_padding_check(void *instance, size_t un= ion_offset, __union_size, __member_size); \ }) =20 -#define PVR_FW_PROCESSOR_TYPE_META 0 -#define PVR_FW_PROCESSOR_TYPE_MIPS 1 -#define PVR_FW_PROCESSOR_TYPE_RISCV 2 - #endif /* PVR_DEVICE_H */ diff --git a/drivers/gpu/drm/imagination/pvr_fw.c b/drivers/gpu/drm/imagina= tion/pvr_fw.c index 3441c378d91c61df704bfbfee23488b89b1d4569..962b8cb2119ec5e177fa2a8225e= 3387d113dcd03 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.c +++ b/drivers/gpu/drm/imagination/pvr_fw.c @@ -938,16 +938,27 @@ pvr_fw_validate_init_device_info(struct pvr_device *p= vr_dev) int pvr_fw_init(struct pvr_device *pvr_dev) { + static const struct pvr_fw_defs *fw_defs[PVR_FW_PROCESSOR_TYPE_COUNT] =3D= { + [PVR_FW_PROCESSOR_TYPE_META] =3D &pvr_fw_defs_meta, + [PVR_FW_PROCESSOR_TYPE_MIPS] =3D &pvr_fw_defs_mips, + [PVR_FW_PROCESSOR_TYPE_RISCV] =3D NULL, + }; + u32 kccb_size_log2 =3D ROGUE_FWIF_KCCB_NUMCMDS_LOG2_DEFAULT; u32 kccb_rtn_size =3D (1 << kccb_size_log2) * sizeof(*pvr_dev->kccb.rtn); struct pvr_fw_device *fw_dev =3D &pvr_dev->fw_dev; int err; =20 - if (fw_dev->processor_type =3D=3D PVR_FW_PROCESSOR_TYPE_META) - fw_dev->defs =3D &pvr_fw_defs_meta; - else if (fw_dev->processor_type =3D=3D PVR_FW_PROCESSOR_TYPE_MIPS) - fw_dev->defs =3D &pvr_fw_defs_mips; - else + if (fw_dev->processor_type >=3D PVR_FW_PROCESSOR_TYPE_COUNT) + return -EINVAL; + + fw_dev->defs =3D fw_defs[fw_dev->processor_type]; + + /* + * Not all firmware processor types are currently supported. + * Once they are, this check can be removed. + */ + if (!fw_dev->defs) return -EINVAL; =20 err =3D fw_dev->defs->init(pvr_dev); diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagina= tion/pvr_fw.h index 180d310074e3585c641e540a9e2576b5ab2a5705..88ad713468ce3a1ee459b04dde5= 363c24791a4f1 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -402,6 +402,13 @@ struct pvr_fw_device { #define pvr_fw_irq_clear(pvr_dev) \ pvr_fw_irq_write_reg(pvr_dev, clear, (pvr_dev)->fw_dev.defs->irq.clear_ma= sk) =20 +enum pvr_fw_processor_type { + PVR_FW_PROCESSOR_TYPE_META =3D 0, + PVR_FW_PROCESSOR_TYPE_MIPS, + PVR_FW_PROCESSOR_TYPE_RISCV, + PVR_FW_PROCESSOR_TYPE_COUNT, +}; + extern const struct pvr_fw_defs pvr_fw_defs_meta; extern const struct pvr_fw_defs pvr_fw_defs_mips; =20 --=20 2.49.0