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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-2d0969589basm958677fac.19.2025.04.10.20.50.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Apr 2025 20:50:23 -0700 (PDT) From: Bjorn Andersson Date: Thu, 10 Apr 2025 22:50:12 -0500 Subject: [PATCH v6 1/6] usb: dwc3: qcom: Snapshot driver for backwards compatibilty Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250410-dwc3-refactor-v6-1-dc0d1b336135@oss.qualcomm.com> References: <20250410-dwc3-refactor-v6-0-dc0d1b336135@oss.qualcomm.com> In-Reply-To: <20250410-dwc3-refactor-v6-0-dc0d1b336135@oss.qualcomm.com> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Wesley Cheng , Saravana Kannan , Thinh Nguyen , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Frank Li Cc: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Andersson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=27803; i=bjorn.andersson@oss.qualcomm.com; h=from:subject:message-id; bh=z/c5mHlakGwcNQh0aVh7d+jvsmOAQoUhJv6FMedly7s=; b=owEBgwJ8/ZANAwAIAQsfOT8Nma3FAcsmYgBn+JF96vuNVIzq6Tl8lMjaItd8LXE59ITDLA4WB R2YeHQfbpGJAkkEAAEIADMWIQQF3gPMXzXqTwlm1SULHzk/DZmtxQUCZ/iRfRUcYW5kZXJzc29u QGtlcm5lbC5vcmcACgkQCx85Pw2ZrcVPMxAAt3AKCix07Hfxl8W+KS10eccj0YCmQAaRRhu+xQM HIFtpR7z3fpCjtOGFcLfa0X+AmabekKGcg1tS4PDrkRzFtVB+WQIZJO8MX+GTsF5T7xIAbGNBX7 VeUVt9lDBSTqhfp7O1UuVXZAOP7CUURGR8c3eUDkBLf7xzNVvQjSVmjjCOC4G0cabcjTcYEMb/0 Nx4pS1IXQQQVApt4UbspeS0vW3S50ITSwimWjWkW0KUnv764j4Trsf5sa7xp4v5RonxfvcOgH3c JWRYcje4uSQYyqfmWEfVbyfvNHgEH0proymh7v0rPjENZkerODBBkjJo5TtROKYb8E27+Bi+iOz OPNqlmVITOHRvcvKfIWyP/mtYckHJDas0TOKZQz4FlzuAkp1HI521oGztCTmvRKBRwDZf/pcDm6 8SLgSMQODb1hkJvqfc1g6GNzTt6a08dU0prz9eLTHnGKJPrGsW5bHbn08RATd5QFhfY7FHJTpas MxnTQRgDNyZv/Qzt3WHG3QTMdxPkU4OlvW11IMki5Jf1dDWDsK9gqzEzUHm+VZYkaZqSfRNQTw5 I8VSwn3R5Hat9aDt5j24lz7CN0uLBtkcDVw8jjvtPhtCGEEJa2skadpIOsnJwg6dViXlJQz+rlA Ut1VL1cH5nEQFWZow1HrYIsQjA3xyChaR3q5feKROUAU= X-Developer-Key: i=bjorn.andersson@oss.qualcomm.com; a=openpgp; fpr=05DE03CC5F35EA4F0966D5250B1F393F0D99ADC5 X-Proofpoint-GUID: JpO2YBJLhLQxikWRlTec-bU7EQZxdKgP X-Authority-Analysis: v=2.4 cv=LLlmQIW9 c=1 sm=1 tr=0 ts=67f89182 cx=c_pps a=AKZTfHrQPB8q3CcvmcIuDA==:117 a=DaeiM5VmU20ml6RIjrOvYw==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=jIQo8A4GAAAA:8 a=EUspDBNiAAAA:8 a=5k_pm2BD3DQxMjm8UnsA:9 a=QEXdDO2ut3YA:10 a=RVmHIydaz68A:10 a=pF_qn-MSjDawc0seGVz6:22 X-Proofpoint-ORIG-GUID: JpO2YBJLhLQxikWRlTec-bU7EQZxdKgP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-11_01,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 clxscore=1015 mlxlogscore=999 malwarescore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 spamscore=0 adultscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504110026 In order to more tightly integrate the Qualcomm glue driver with the dwc3 core the driver is redesigned to avoid splitting the implementation using the driver model. But due to the strong coupling to the Devicetree binding needs to be updated as well. Various ways to provide backwards compatibility with existing Devicetree blobs has been explored, but migrating the Devicetree information between the old and the new binding is non-trivial. For the vast majority of boards out there, the kernel and Devicetree are generated and handled together, which in practice means that backwards compatibility needs to be managed across about 1 kernel release. For some though, such as the various Snapdragon laptops, the Devicetree blobs live a life separate of the kernel. In each one of these, with the continued extension of new features, it's recommended that users would upgrade their Devicetree somewhat frequently. With this in mind, simply carrying a snapshot/copy of the current driver is simpler than creating and maintaining the migration code. The driver is kept under the same Kconfig option, to ensure that Linux distributions doesn't drop USB support on these platforms. The driver, which is going to be refactored to handle the newly introduced qcom,snps-dwc3 compatible, is updated to temporarily not match against any compatible. This driver should be removed after the next LTS release. Acked-by: Thinh Nguyen Signed-off-by: Bjorn Andersson Tested-by: Neil Armstrong # on SM8650-QRD --- drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-qcom-legacy.c | 935 ++++++++++++++++++++++++++++++++= ++++ drivers/usb/dwc3/dwc3-qcom.c | 1 - 3 files changed, 936 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 124eda2522d9c1f4caab222ec9770d0deaf655fc..830e6c9e5fe073c1f662ce34b6a= 4a2da34c407a2 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_USB_DWC3_MESON_G12A) +=3D dwc3-meson-g12a.o obj-$(CONFIG_USB_DWC3_OF_SIMPLE) +=3D dwc3-of-simple.o obj-$(CONFIG_USB_DWC3_ST) +=3D dwc3-st.o obj-$(CONFIG_USB_DWC3_QCOM) +=3D dwc3-qcom.o +obj-$(CONFIG_USB_DWC3_QCOM) +=3D dwc3-qcom-legacy.o obj-$(CONFIG_USB_DWC3_IMX8MP) +=3D dwc3-imx8mp.o obj-$(CONFIG_USB_DWC3_XILINX) +=3D dwc3-xilinx.o obj-$(CONFIG_USB_DWC3_OCTEON) +=3D dwc3-octeon.o diff --git a/drivers/usb/dwc3/dwc3-qcom-legacy.c b/drivers/usb/dwc3/dwc3-qc= om-legacy.c new file mode 100644 index 0000000000000000000000000000000000000000..d3fad0fcfdac33ffbd75933f480= 3a023423bc4f4 --- /dev/null +++ b/drivers/usb/dwc3/dwc3-qcom-legacy.c @@ -0,0 +1,935 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. + * + * Inspired by dwc3-of-simple.c + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "core.h" + +/* USB QSCRATCH Hardware registers */ +#define QSCRATCH_HS_PHY_CTRL 0x10 +#define UTMI_OTG_VBUS_VALID BIT(20) +#define SW_SESSVLD_SEL BIT(28) + +#define QSCRATCH_SS_PHY_CTRL 0x30 +#define LANE0_PWR_PRESENT BIT(24) + +#define QSCRATCH_GENERAL_CFG 0x08 +#define PIPE_UTMI_CLK_SEL BIT(0) +#define PIPE3_PHYSTATUS_SW BIT(3) +#define PIPE_UTMI_CLK_DIS BIT(8) + +#define PWR_EVNT_LPM_IN_L2_MASK BIT(4) +#define PWR_EVNT_LPM_OUT_L2_MASK BIT(5) + +#define SDM845_QSCRATCH_BASE_OFFSET 0xf8800 +#define SDM845_QSCRATCH_SIZE 0x400 +#define SDM845_DWC3_CORE_SIZE 0xcd00 + +/* Interconnect path bandwidths in MBps */ +#define USB_MEMORY_AVG_HS_BW MBps_to_icc(240) +#define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700) +#define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000) +#define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500) +#define APPS_USB_AVG_BW 0 +#define APPS_USB_PEAK_BW MBps_to_icc(40) + +/* Qualcomm SoCs with multiport support has up to 4 ports */ +#define DWC3_QCOM_MAX_PORTS 4 + +static const u32 pwr_evnt_irq_stat_reg[DWC3_QCOM_MAX_PORTS] =3D { + 0x58, + 0x1dc, + 0x228, + 0x238, +}; + +struct dwc3_qcom_port { + int qusb2_phy_irq; + int dp_hs_phy_irq; + int dm_hs_phy_irq; + int ss_phy_irq; + enum usb_device_speed usb2_speed; +}; + +struct dwc3_qcom { + struct device *dev; + void __iomem *qscratch_base; + struct platform_device *dwc3; + struct clk **clks; + int num_clocks; + struct reset_control *resets; + struct dwc3_qcom_port ports[DWC3_QCOM_MAX_PORTS]; + u8 num_ports; + + struct extcon_dev *edev; + struct extcon_dev *host_edev; + struct notifier_block vbus_nb; + struct notifier_block host_nb; + + enum usb_dr_mode mode; + bool is_suspended; + bool pm_suspended; + struct icc_path *icc_path_ddr; + struct icc_path *icc_path_apps; +}; + +static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 v= al) +{ + u32 reg; + + reg =3D readl(base + offset); + reg |=3D val; + writel(reg, base + offset); + + /* ensure that above write is through */ + readl(base + offset); +} + +static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 v= al) +{ + u32 reg; + + reg =3D readl(base + offset); + reg &=3D ~val; + writel(reg, base + offset); + + /* ensure that above write is through */ + readl(base + offset); +} + +static void dwc3_qcom_vbus_override_enable(struct dwc3_qcom *qcom, bool en= able) +{ + if (enable) { + dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, + LANE0_PWR_PRESENT); + dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, + UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL); + } else { + dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, + LANE0_PWR_PRESENT); + dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, + UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL); + } +} + +static int dwc3_qcom_vbus_notifier(struct notifier_block *nb, + unsigned long event, void *ptr) +{ + struct dwc3_qcom *qcom =3D container_of(nb, struct dwc3_qcom, vbus_nb); + + /* enable vbus override for device mode */ + dwc3_qcom_vbus_override_enable(qcom, event); + qcom->mode =3D event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST; + + return NOTIFY_DONE; +} + +static int dwc3_qcom_host_notifier(struct notifier_block *nb, + unsigned long event, void *ptr) +{ + struct dwc3_qcom *qcom =3D container_of(nb, struct dwc3_qcom, host_nb); + + /* disable vbus override in host mode */ + dwc3_qcom_vbus_override_enable(qcom, !event); + qcom->mode =3D event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL; + + return NOTIFY_DONE; +} + +static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom) +{ + struct device *dev =3D qcom->dev; + struct extcon_dev *host_edev; + int ret; + + if (!of_property_present(dev->of_node, "extcon")) + return 0; + + qcom->edev =3D extcon_get_edev_by_phandle(dev, 0); + if (IS_ERR(qcom->edev)) + return dev_err_probe(dev, PTR_ERR(qcom->edev), + "Failed to get extcon\n"); + + qcom->vbus_nb.notifier_call =3D dwc3_qcom_vbus_notifier; + + qcom->host_edev =3D extcon_get_edev_by_phandle(dev, 1); + if (IS_ERR(qcom->host_edev)) + qcom->host_edev =3D NULL; + + ret =3D devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB, + &qcom->vbus_nb); + if (ret < 0) { + dev_err(dev, "VBUS notifier register failed\n"); + return ret; + } + + if (qcom->host_edev) + host_edev =3D qcom->host_edev; + else + host_edev =3D qcom->edev; + + qcom->host_nb.notifier_call =3D dwc3_qcom_host_notifier; + ret =3D devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST, + &qcom->host_nb); + if (ret < 0) { + dev_err(dev, "Host notifier register failed\n"); + return ret; + } + + /* Update initial VBUS override based on extcon state */ + if (extcon_get_state(qcom->edev, EXTCON_USB) || + !extcon_get_state(host_edev, EXTCON_USB_HOST)) + dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev); + else + dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev); + + return 0; +} + +static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom) +{ + int ret; + + ret =3D icc_enable(qcom->icc_path_ddr); + if (ret) + return ret; + + ret =3D icc_enable(qcom->icc_path_apps); + if (ret) + icc_disable(qcom->icc_path_ddr); + + return ret; +} + +static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom) +{ + int ret; + + ret =3D icc_disable(qcom->icc_path_ddr); + if (ret) + return ret; + + ret =3D icc_disable(qcom->icc_path_apps); + if (ret) + icc_enable(qcom->icc_path_ddr); + + return ret; +} + +/** + * dwc3_qcom_interconnect_init() - Get interconnect path handles + * and set bandwidth. + * @qcom: Pointer to the concerned usb core. + * + */ +static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom) +{ + enum usb_device_speed max_speed; + struct device *dev =3D qcom->dev; + int ret; + + qcom->icc_path_ddr =3D of_icc_get(dev, "usb-ddr"); + if (IS_ERR(qcom->icc_path_ddr)) { + return dev_err_probe(dev, PTR_ERR(qcom->icc_path_ddr), + "failed to get usb-ddr path\n"); + } + + qcom->icc_path_apps =3D of_icc_get(dev, "apps-usb"); + if (IS_ERR(qcom->icc_path_apps)) { + ret =3D dev_err_probe(dev, PTR_ERR(qcom->icc_path_apps), + "failed to get apps-usb path\n"); + goto put_path_ddr; + } + + max_speed =3D usb_get_maximum_speed(&qcom->dwc3->dev); + if (max_speed >=3D USB_SPEED_SUPER || max_speed =3D=3D USB_SPEED_UNKNOWN)= { + ret =3D icc_set_bw(qcom->icc_path_ddr, + USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW); + } else { + ret =3D icc_set_bw(qcom->icc_path_ddr, + USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW); + } + if (ret) { + dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret); + goto put_path_apps; + } + + ret =3D icc_set_bw(qcom->icc_path_apps, APPS_USB_AVG_BW, APPS_USB_PEAK_BW= ); + if (ret) { + dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret); + goto put_path_apps; + } + + return 0; + +put_path_apps: + icc_put(qcom->icc_path_apps); +put_path_ddr: + icc_put(qcom->icc_path_ddr); + return ret; +} + +/** + * dwc3_qcom_interconnect_exit() - Release interconnect path handles + * @qcom: Pointer to the concerned usb core. + * + * This function is used to release interconnect path handle. + */ +static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom) +{ + icc_put(qcom->icc_path_ddr); + icc_put(qcom->icc_path_apps); +} + +/* Only usable in contexts where the role can not change. */ +static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom) +{ + struct dwc3 *dwc; + + /* + * FIXME: Fix this layering violation. + */ + dwc =3D platform_get_drvdata(qcom->dwc3); + + /* Core driver may not have probed yet. */ + if (!dwc) + return false; + + return dwc->xhci; +} + +static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *q= com, int port_index) +{ + struct dwc3 *dwc =3D platform_get_drvdata(qcom->dwc3); + struct usb_device *udev; + struct usb_hcd __maybe_unused *hcd; + + /* + * FIXME: Fix this layering violation. + */ + hcd =3D platform_get_drvdata(dwc->xhci); + +#ifdef CONFIG_USB + udev =3D usb_hub_find_child(hcd->self.root_hub, port_index + 1); +#else + udev =3D NULL; +#endif + if (!udev) + return USB_SPEED_UNKNOWN; + + return udev->speed; +} + +static void dwc3_qcom_enable_wakeup_irq(int irq, unsigned int polarity) +{ + if (!irq) + return; + + if (polarity) + irq_set_irq_type(irq, polarity); + + enable_irq(irq); + enable_irq_wake(irq); +} + +static void dwc3_qcom_disable_wakeup_irq(int irq) +{ + if (!irq) + return; + + disable_irq_wake(irq); + disable_irq_nosync(irq); +} + +static void dwc3_qcom_disable_port_interrupts(struct dwc3_qcom_port *port) +{ + dwc3_qcom_disable_wakeup_irq(port->qusb2_phy_irq); + + if (port->usb2_speed =3D=3D USB_SPEED_LOW) { + dwc3_qcom_disable_wakeup_irq(port->dm_hs_phy_irq); + } else if ((port->usb2_speed =3D=3D USB_SPEED_HIGH) || + (port->usb2_speed =3D=3D USB_SPEED_FULL)) { + dwc3_qcom_disable_wakeup_irq(port->dp_hs_phy_irq); + } else { + dwc3_qcom_disable_wakeup_irq(port->dp_hs_phy_irq); + dwc3_qcom_disable_wakeup_irq(port->dm_hs_phy_irq); + } + + dwc3_qcom_disable_wakeup_irq(port->ss_phy_irq); +} + +static void dwc3_qcom_enable_port_interrupts(struct dwc3_qcom_port *port) +{ + dwc3_qcom_enable_wakeup_irq(port->qusb2_phy_irq, 0); + + /* + * Configure DP/DM line interrupts based on the USB2 device attached to + * the root hub port. When HS/FS device is connected, configure the DP li= ne + * as falling edge to detect both disconnect and remote wakeup scenarios.= When + * LS device is connected, configure DM line as falling edge to detect bo= th + * disconnect and remote wakeup. When no device is connected, configure b= oth + * DP and DM lines as rising edge to detect HS/HS/LS device connect scena= rio. + */ + + if (port->usb2_speed =3D=3D USB_SPEED_LOW) { + dwc3_qcom_enable_wakeup_irq(port->dm_hs_phy_irq, + IRQ_TYPE_EDGE_FALLING); + } else if ((port->usb2_speed =3D=3D USB_SPEED_HIGH) || + (port->usb2_speed =3D=3D USB_SPEED_FULL)) { + dwc3_qcom_enable_wakeup_irq(port->dp_hs_phy_irq, + IRQ_TYPE_EDGE_FALLING); + } else { + dwc3_qcom_enable_wakeup_irq(port->dp_hs_phy_irq, + IRQ_TYPE_EDGE_RISING); + dwc3_qcom_enable_wakeup_irq(port->dm_hs_phy_irq, + IRQ_TYPE_EDGE_RISING); + } + + dwc3_qcom_enable_wakeup_irq(port->ss_phy_irq, 0); +} + +static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) +{ + int i; + + for (i =3D 0; i < qcom->num_ports; i++) + dwc3_qcom_disable_port_interrupts(&qcom->ports[i]); +} + +static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) +{ + int i; + + for (i =3D 0; i < qcom->num_ports; i++) + dwc3_qcom_enable_port_interrupts(&qcom->ports[i]); +} + +static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) +{ + u32 val; + int i, ret; + + if (qcom->is_suspended) + return 0; + + for (i =3D 0; i < qcom->num_ports; i++) { + val =3D readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i]); + if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) + dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1); + } + + for (i =3D qcom->num_clocks - 1; i >=3D 0; i--) + clk_disable_unprepare(qcom->clks[i]); + + ret =3D dwc3_qcom_interconnect_disable(qcom); + if (ret) + dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret); + + /* + * The role is stable during suspend as role switching is done from a + * freezable workqueue. + */ + if (dwc3_qcom_is_host(qcom) && wakeup) { + for (i =3D 0; i < qcom->num_ports; i++) + qcom->ports[i].usb2_speed =3D dwc3_qcom_read_usb2_speed(qcom, i); + dwc3_qcom_enable_interrupts(qcom); + } + + qcom->is_suspended =3D true; + + return 0; +} + +static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup) +{ + int ret; + int i; + + if (!qcom->is_suspended) + return 0; + + if (dwc3_qcom_is_host(qcom) && wakeup) + dwc3_qcom_disable_interrupts(qcom); + + for (i =3D 0; i < qcom->num_clocks; i++) { + ret =3D clk_prepare_enable(qcom->clks[i]); + if (ret < 0) { + while (--i >=3D 0) + clk_disable_unprepare(qcom->clks[i]); + return ret; + } + } + + ret =3D dwc3_qcom_interconnect_enable(qcom); + if (ret) + dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret); + + /* Clear existing events from PHY related to L2 in/out */ + for (i =3D 0; i < qcom->num_ports; i++) { + dwc3_qcom_setbits(qcom->qscratch_base, + pwr_evnt_irq_stat_reg[i], + PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); + } + + qcom->is_suspended =3D false; + + return 0; +} + +static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data) +{ + struct dwc3_qcom *qcom =3D data; + struct dwc3 *dwc =3D platform_get_drvdata(qcom->dwc3); + + /* If pm_suspended then let pm_resume take care of resuming h/w */ + if (qcom->pm_suspended) + return IRQ_HANDLED; + + /* + * This is safe as role switching is done from a freezable workqueue + * and the wakeup interrupts are disabled as part of resume. + */ + if (dwc3_qcom_is_host(qcom)) + pm_runtime_resume(&dwc->xhci->dev); + + return IRQ_HANDLED; +} + +static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom) +{ + /* Configure dwc3 to use UTMI clock as PIPE clock not present */ + dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, + PIPE_UTMI_CLK_DIS); + + usleep_range(100, 1000); + + dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, + PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW); + + usleep_range(100, 1000); + + dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG, + PIPE_UTMI_CLK_DIS); +} + +static int dwc3_qcom_request_irq(struct dwc3_qcom *qcom, int irq, + const char *name) +{ + int ret; + + /* Keep wakeup interrupts disabled until suspend */ + ret =3D devm_request_threaded_irq(qcom->dev, irq, NULL, + qcom_dwc3_resume_irq, + IRQF_ONESHOT | IRQF_NO_AUTOEN, + name, qcom); + if (ret) + dev_err(qcom->dev, "failed to request irq %s: %d\n", name, ret); + + return ret; +} + +static int dwc3_qcom_setup_port_irq(struct platform_device *pdev, int port= _index, bool is_multiport) +{ + struct dwc3_qcom *qcom =3D platform_get_drvdata(pdev); + const char *irq_name; + int irq; + int ret; + + if (is_multiport) + irq_name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, "dp_hs_phy_%d", port= _index + 1); + else + irq_name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, "dp_hs_phy_irq"); + if (!irq_name) + return -ENOMEM; + + irq =3D platform_get_irq_byname_optional(pdev, irq_name); + if (irq > 0) { + ret =3D dwc3_qcom_request_irq(qcom, irq, irq_name); + if (ret) + return ret; + qcom->ports[port_index].dp_hs_phy_irq =3D irq; + } + + if (is_multiport) + irq_name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, "dm_hs_phy_%d", port= _index + 1); + else + irq_name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, "dm_hs_phy_irq"); + if (!irq_name) + return -ENOMEM; + + irq =3D platform_get_irq_byname_optional(pdev, irq_name); + if (irq > 0) { + ret =3D dwc3_qcom_request_irq(qcom, irq, irq_name); + if (ret) + return ret; + qcom->ports[port_index].dm_hs_phy_irq =3D irq; + } + + if (is_multiport) + irq_name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, "ss_phy_%d", port_in= dex + 1); + else + irq_name =3D devm_kasprintf(&pdev->dev, GFP_KERNEL, "ss_phy_irq"); + if (!irq_name) + return -ENOMEM; + + irq =3D platform_get_irq_byname_optional(pdev, irq_name); + if (irq > 0) { + ret =3D dwc3_qcom_request_irq(qcom, irq, irq_name); + if (ret) + return ret; + qcom->ports[port_index].ss_phy_irq =3D irq; + } + + if (is_multiport) + return 0; + + irq =3D platform_get_irq_byname_optional(pdev, "qusb2_phy"); + if (irq > 0) { + ret =3D dwc3_qcom_request_irq(qcom, irq, "qusb2_phy"); + if (ret) + return ret; + qcom->ports[port_index].qusb2_phy_irq =3D irq; + } + + return 0; +} + +static int dwc3_qcom_find_num_ports(struct platform_device *pdev) +{ + char irq_name[14]; + int port_num; + int irq; + + irq =3D platform_get_irq_byname_optional(pdev, "dp_hs_phy_1"); + if (irq <=3D 0) + return 1; + + for (port_num =3D 2; port_num <=3D DWC3_QCOM_MAX_PORTS; port_num++) { + sprintf(irq_name, "dp_hs_phy_%d", port_num); + + irq =3D platform_get_irq_byname_optional(pdev, irq_name); + if (irq <=3D 0) + return port_num - 1; + } + + return DWC3_QCOM_MAX_PORTS; +} + +static int dwc3_qcom_setup_irq(struct platform_device *pdev) +{ + struct dwc3_qcom *qcom =3D platform_get_drvdata(pdev); + bool is_multiport; + int ret; + int i; + + qcom->num_ports =3D dwc3_qcom_find_num_ports(pdev); + is_multiport =3D (qcom->num_ports > 1); + + for (i =3D 0; i < qcom->num_ports; i++) { + ret =3D dwc3_qcom_setup_port_irq(pdev, i, is_multiport); + if (ret) + return ret; + } + + return 0; +} + +static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count) +{ + struct device *dev =3D qcom->dev; + struct device_node *np =3D dev->of_node; + int i; + + if (!np || !count) + return 0; + + if (count < 0) + return count; + + qcom->num_clocks =3D count; + + qcom->clks =3D devm_kcalloc(dev, qcom->num_clocks, + sizeof(struct clk *), GFP_KERNEL); + if (!qcom->clks) + return -ENOMEM; + + for (i =3D 0; i < qcom->num_clocks; i++) { + struct clk *clk; + int ret; + + clk =3D of_clk_get(np, i); + if (IS_ERR(clk)) { + while (--i >=3D 0) + clk_put(qcom->clks[i]); + return PTR_ERR(clk); + } + + ret =3D clk_prepare_enable(clk); + if (ret < 0) { + while (--i >=3D 0) { + clk_disable_unprepare(qcom->clks[i]); + clk_put(qcom->clks[i]); + } + clk_put(clk); + + return ret; + } + + qcom->clks[i] =3D clk; + } + + return 0; +} + +static int dwc3_qcom_of_register_core(struct platform_device *pdev) +{ + struct dwc3_qcom *qcom =3D platform_get_drvdata(pdev); + struct device_node *np =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; + int ret; + + struct device_node *dwc3_np __free(device_node) =3D of_get_compatible_chi= ld(np, + "snps,dwc3"); + if (!dwc3_np) { + dev_err(dev, "failed to find dwc3 core child\n"); + return -ENODEV; + } + + ret =3D of_platform_populate(np, NULL, NULL, dev); + if (ret) { + dev_err(dev, "failed to register dwc3 core - %d\n", ret); + return ret; + } + + qcom->dwc3 =3D of_find_device_by_node(dwc3_np); + if (!qcom->dwc3) { + ret =3D -ENODEV; + dev_err(dev, "failed to get dwc3 platform device\n"); + of_platform_depopulate(dev); + } + + return ret; +} + +static int dwc3_qcom_probe(struct platform_device *pdev) +{ + struct device_node *np =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; + struct dwc3_qcom *qcom; + int ret, i; + bool ignore_pipe_clk; + bool wakeup_source; + + qcom =3D devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL); + if (!qcom) + return -ENOMEM; + + platform_set_drvdata(pdev, qcom); + qcom->dev =3D &pdev->dev; + + qcom->resets =3D devm_reset_control_array_get_optional_exclusive(dev); + if (IS_ERR(qcom->resets)) { + return dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets), + "failed to get resets\n"); + } + + ret =3D reset_control_assert(qcom->resets); + if (ret) { + dev_err(&pdev->dev, "failed to assert resets, err=3D%d\n", ret); + return ret; + } + + usleep_range(10, 1000); + + ret =3D reset_control_deassert(qcom->resets); + if (ret) { + dev_err(&pdev->dev, "failed to deassert resets, err=3D%d\n", ret); + goto reset_assert; + } + + ret =3D dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np)); + if (ret) { + dev_err_probe(dev, ret, "failed to get clocks\n"); + goto reset_assert; + } + + qcom->qscratch_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(qcom->qscratch_base)) { + ret =3D PTR_ERR(qcom->qscratch_base); + goto clk_disable; + } + + ret =3D dwc3_qcom_setup_irq(pdev); + if (ret) { + dev_err(dev, "failed to setup IRQs, err=3D%d\n", ret); + goto clk_disable; + } + + /* + * Disable pipe_clk requirement if specified. Used when dwc3 + * operates without SSPHY and only HS/FS/LS modes are supported. + */ + ignore_pipe_clk =3D device_property_read_bool(dev, + "qcom,select-utmi-as-pipe-clk"); + if (ignore_pipe_clk) + dwc3_qcom_select_utmi_clk(qcom); + + ret =3D dwc3_qcom_of_register_core(pdev); + if (ret) { + dev_err(dev, "failed to register DWC3 Core, err=3D%d\n", ret); + goto clk_disable; + } + + ret =3D dwc3_qcom_interconnect_init(qcom); + if (ret) + goto depopulate; + + qcom->mode =3D usb_get_dr_mode(&qcom->dwc3->dev); + + /* enable vbus override for device mode */ + if (qcom->mode !=3D USB_DR_MODE_HOST) + dwc3_qcom_vbus_override_enable(qcom, true); + + /* register extcon to override sw_vbus on Vbus change later */ + ret =3D dwc3_qcom_register_extcon(qcom); + if (ret) + goto interconnect_exit; + + wakeup_source =3D of_property_read_bool(dev->of_node, "wakeup-source"); + device_init_wakeup(&pdev->dev, wakeup_source); + device_init_wakeup(&qcom->dwc3->dev, wakeup_source); + + qcom->is_suspended =3D false; + pm_runtime_set_active(dev); + pm_runtime_enable(dev); + pm_runtime_forbid(dev); + + return 0; + +interconnect_exit: + dwc3_qcom_interconnect_exit(qcom); +depopulate: + of_platform_depopulate(&pdev->dev); + platform_device_put(qcom->dwc3); +clk_disable: + for (i =3D qcom->num_clocks - 1; i >=3D 0; i--) { + clk_disable_unprepare(qcom->clks[i]); + clk_put(qcom->clks[i]); + } +reset_assert: + reset_control_assert(qcom->resets); + + return ret; +} + +static void dwc3_qcom_remove(struct platform_device *pdev) +{ + struct dwc3_qcom *qcom =3D platform_get_drvdata(pdev); + struct device *dev =3D &pdev->dev; + int i; + + of_platform_depopulate(&pdev->dev); + platform_device_put(qcom->dwc3); + + for (i =3D qcom->num_clocks - 1; i >=3D 0; i--) { + clk_disable_unprepare(qcom->clks[i]); + clk_put(qcom->clks[i]); + } + qcom->num_clocks =3D 0; + + dwc3_qcom_interconnect_exit(qcom); + reset_control_assert(qcom->resets); + + pm_runtime_allow(dev); + pm_runtime_disable(dev); +} + +static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev) +{ + struct dwc3_qcom *qcom =3D dev_get_drvdata(dev); + bool wakeup =3D device_may_wakeup(dev); + int ret; + + ret =3D dwc3_qcom_suspend(qcom, wakeup); + if (ret) + return ret; + + qcom->pm_suspended =3D true; + + return 0; +} + +static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev) +{ + struct dwc3_qcom *qcom =3D dev_get_drvdata(dev); + bool wakeup =3D device_may_wakeup(dev); + int ret; + + ret =3D dwc3_qcom_resume(qcom, wakeup); + if (ret) + return ret; + + qcom->pm_suspended =3D false; + + return 0; +} + +static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev) +{ + struct dwc3_qcom *qcom =3D dev_get_drvdata(dev); + + return dwc3_qcom_suspend(qcom, true); +} + +static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev) +{ + struct dwc3_qcom *qcom =3D dev_get_drvdata(dev); + + return dwc3_qcom_resume(qcom, true); +} + +static const struct dev_pm_ops dwc3_qcom_dev_pm_ops =3D { + SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume) + SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume, + NULL) +}; + +static const struct of_device_id dwc3_qcom_of_match[] =3D { + { .compatible =3D "qcom,dwc3" }, + { } +}; +MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match); + +static struct platform_driver dwc3_qcom_driver =3D { + .probe =3D dwc3_qcom_probe, + .remove =3D dwc3_qcom_remove, + .driver =3D { + .name =3D "dwc3-qcom-legacy", + .pm =3D &dwc3_qcom_dev_pm_ops, + .of_match_table =3D dwc3_qcom_of_match, + }, +}; + +module_platform_driver(dwc3_qcom_driver); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("DesignWare DWC3 QCOM legacy glue Driver"); diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 58683bb672e9522deb321c38daffd856c0d9029c..79f3600f25c41a5ed770f164a03= c7dc424b01440 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -914,7 +914,6 @@ static const struct dev_pm_ops dwc3_qcom_dev_pm_ops =3D= { }; =20 static const struct of_device_id dwc3_qcom_of_match[] =3D { - { .compatible =3D "qcom,dwc3" }, { } }; MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match); 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-2d0969589basm958677fac.19.2025.04.10.20.50.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Apr 2025 20:50:24 -0700 (PDT) From: Bjorn Andersson Date: Thu, 10 Apr 2025 22:50:13 -0500 Subject: [PATCH v6 2/6] dt-bindings: usb: Introduce qcom,snps-dwc3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250410-dwc3-refactor-v6-2-dc0d1b336135@oss.qualcomm.com> References: <20250410-dwc3-refactor-v6-0-dc0d1b336135@oss.qualcomm.com> In-Reply-To: <20250410-dwc3-refactor-v6-0-dc0d1b336135@oss.qualcomm.com> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Wesley Cheng , Saravana Kannan , Thinh Nguyen , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Frank Li Cc: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Andersson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=19926; i=bjorn.andersson@oss.qualcomm.com; h=from:subject:message-id; bh=5aUIi72laSNrHqd1zHvVj7+Gq/d3mQuTesLOpmQ/75o=; b=owEBgwJ8/ZANAwAIAQsfOT8Nma3FAcsmYgBn+JF9SaTPj+murRo/NjRYwPaAS4c9PO6LaP0oG B47hKS0YkOJAkkEAAEIADMWIQQF3gPMXzXqTwlm1SULHzk/DZmtxQUCZ/iRfRUcYW5kZXJzc29u QGtlcm5lbC5vcmcACgkQCx85Pw2ZrcWKtQ/9E0l1BNvv7XzzDGhzyxCd4xGO7+4GKDBfb5QOo6h Kee+2kqxJPMw0qOxAdQhikPBo6dpxN/EFU2Nl21zselYuJTIC6NCstxStgoPn1Z2ezMVS3n9Jpw kJICzas9jfFh0eg/3qekZZ7bUisUyO+qlrZ6IOupF8CKKWeFBeUbZRx9/ukJMUbUtSPh1TZHIGt FPacKPc66J4Ay+uDf2+007RBEZJ6sVwg6uuwl9dYqPWgJ+usPbiW/te56K92IIMhXz9nJmGEoFm h4RkM2fY9WVeR9cdziI9uiHn8/OpxPWkKiMHPhSEIQ1mjxeH2JKsyZgqm46ByeUHRR2jsVhM7T5 0Y/89odfaBpMQ5Isls0792t5tDzkafaFTZoDaWcXavt3FyLVfQL2RtS8rdEiXTBbcpJ9p9S7pgh K7ch827IywD0GcVvnxPabTgShsExVsHlWJSLU9YOKoDCxjY3MucVwRrwnglYE7TnN1Mpq9d/hBF DwT+s4gRK9ri98n1RqodRIfbiG8n/k8gkQHylPsjDLpFT6cQAuaIrh46/Ae+9VZvXP+Gj1FF6vK rZZ3coK4Vb00VFpmGhqH1cFLswg79Lrui7I4hSYdRvVZhE+Vwv1oW3IIVCJ2eXEMtQvPIs+Qh00 qnlFdYMzIOMvU6OGNgQsg7uR0pQbMT/4fMXOWWjLNk6Y= X-Developer-Key: i=bjorn.andersson@oss.qualcomm.com; a=openpgp; fpr=05DE03CC5F35EA4F0966D5250B1F393F0D99ADC5 X-Proofpoint-GUID: OTilboVa7Cn0yup2XcDCshnSlGXpcpRk X-Proofpoint-ORIG-GUID: OTilboVa7Cn0yup2XcDCshnSlGXpcpRk X-Authority-Analysis: v=2.4 cv=MpRS63ae c=1 sm=1 tr=0 ts=67f89182 cx=c_pps a=Z3eh007fzM5o9awBa1HkYQ==:117 a=DaeiM5VmU20ml6RIjrOvYw==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=gEfo2CItAAAA:8 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=sxEQ-6IQeHkip0RCg1sA:9 a=QEXdDO2ut3YA:10 a=eBU8X_Hb5SQ8N-bgNfv4:22 a=sptkURWiP4Gy88Gu7hUp:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-11_01,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 impostorscore=0 spamscore=0 bulkscore=0 suspectscore=0 malwarescore=0 adultscore=0 phishscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504110026 The Qualcomm USB glue is not separate of the Synopsys DWC3 core and several of the snps,dwc3 properties (such as clocks and reset) conflicts in expectation with the Qualcomm integration. Using the newly split out Synopsys DWC3 core properties, describe the Qualcomm USB block in a single block. The new binding is a copy of qcom,dwc3 with the needed modifications. It would have been convenient to retain the two structures with the same compatibles, but as there exist no way to select a binding based on the absence of a subnode/patternProperty, a new generic compatible is introduced to describe this binding. To avoid redefining all the platform-specific compatibles, "select" is used to tell the DeviceTree validator which binding to use solely on the generic compatible. (Otherwise if the specific compatible matches during validation, the generic one must match as well) Mark qcom,dwc3 deprecated, to favor expressing future platforms using the new combined binding. Reviewed-by: Rob Herring (Arm) Signed-off-by: Bjorn Andersson Tested-by: Neil Armstrong # on SM8650-QRD --- .../devicetree/bindings/usb/qcom,dwc3.yaml | 13 +- .../devicetree/bindings/usb/qcom,snps-dwc3.yaml | 622 +++++++++++++++++= ++++ 2 files changed, 634 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documen= tation/devicetree/bindings/usb/qcom,dwc3.yaml index 64137c1619a635a5a4f96fc49bd75c5fb757febb..ffb8f9c654b7ae6c3ff29ead24b= fe1e721d25afc 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -4,11 +4,22 @@ $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Qualcomm SuperSpeed DWC3 USB SoC controller +title: Legacy Qualcomm SuperSpeed DWC3 USB SoC controller =20 maintainers: - Wesley Cheng =20 +# Use the combined qcom,snps-dwc3 instead +deprecated: true + +select: + properties: + compatible: + contains: + const: qcom,dwc3 + required: + - compatible + properties: compatible: items: diff --git a/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml b/Do= cumentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml new file mode 100644 index 0000000000000000000000000000000000000000..8dac5eba61b45bc2ea78b23ff38= 678f909e21317 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/qcom,snps-dwc3.yaml @@ -0,0 +1,622 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/qcom,snps-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SuperSpeed DWC3 USB SoC controller + +maintainers: + - Wesley Cheng + +description: + Describes the Qualcomm USB block, based on Synopsys DWC3. + +select: + properties: + compatible: + contains: + const: qcom,snps-dwc3 + required: + - compatible + +properties: + compatible: + items: + - enum: + - qcom,ipq4019-dwc3 + - qcom,ipq5018-dwc3 + - qcom,ipq5332-dwc3 + - qcom,ipq5424-dwc3 + - qcom,ipq6018-dwc3 + - qcom,ipq8064-dwc3 + - qcom,ipq8074-dwc3 + - qcom,ipq9574-dwc3 + - qcom,msm8953-dwc3 + - qcom,msm8994-dwc3 + - qcom,msm8996-dwc3 + - qcom,msm8998-dwc3 + - qcom,qcm2290-dwc3 + - qcom,qcs404-dwc3 + - qcom,qcs615-dwc3 + - qcom,qcs8300-dwc3 + - qcom,qdu1000-dwc3 + - qcom,sa8775p-dwc3 + - qcom,sar2130p-dwc3 + - qcom,sc7180-dwc3 + - qcom,sc7280-dwc3 + - qcom,sc8180x-dwc3 + - qcom,sc8180x-dwc3-mp + - qcom,sc8280xp-dwc3 + - qcom,sc8280xp-dwc3-mp + - qcom,sdm660-dwc3 + - qcom,sdm670-dwc3 + - qcom,sdm845-dwc3 + - qcom,sdx55-dwc3 + - qcom,sdx65-dwc3 + - qcom,sdx75-dwc3 + - qcom,sm4250-dwc3 + - qcom,sm6115-dwc3 + - qcom,sm6125-dwc3 + - qcom,sm6350-dwc3 + - qcom,sm6375-dwc3 + - qcom,sm8150-dwc3 + - qcom,sm8250-dwc3 + - qcom,sm8350-dwc3 + - qcom,sm8450-dwc3 + - qcom,sm8550-dwc3 + - qcom,sm8650-dwc3 + - qcom,x1e80100-dwc3 + - const: qcom,snps-dwc3 + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + required-opps: + maxItems: 1 + + clocks: + description: | + Several clocks are used, depending on the variant. Typical ones are:: + - cfg_noc:: System Config NOC clock. + - core:: Master/Core clock, has to be >=3D 125 MHz for SS operation= and >=3D + 60MHz for HS operation. + - iface:: System bus AXI clock. + - sleep:: Sleep clock, used for wakeup when USB3 core goes into low + power mode (U3). + - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host + mode. Its frequency should be 19.2MHz. + minItems: 1 + maxItems: 9 + + clock-names: + minItems: 1 + maxItems: 9 + + dma-coherent: true + + iommus: + maxItems: 1 + + resets: + maxItems: 1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: usb-ddr + - const: apps-usb + + interrupts: + description: | + Different types of interrupts are used based on HS PHY used on targe= t: + - dwc_usb3: Core DWC3 interrupt + - pwr_event: Used for wakeup based on other power events. + - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is + hs_phy_irq which is not triggered by default and its + functionality is mutually exclusive to that of + {dp/dm}_hs_phy_irq and qusb2_phy_irq. + - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs a= nd + expose only a single IRQ whose behavior can be modif= ied + by the QUSB2PHY_INTR_CTRL register. The required DPS= E/ + DMSE configuration is done in QUSB2PHY_INTR_CTRL reg= ister + of PHY address space. + - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the = DP/ + DM pads of the SoC. These are used for wake= up + only on SoCs with non-QUSB2 targets with + exception of SDM670/SDM845/SM6350. + - ss_phy_irq: Used for remote wakeup in Super Speed mode of operat= ion. + minItems: 3 + maxItems: 19 + + interrupt-names: + minItems: 3 + maxItems: 19 + + qcom,select-utmi-as-pipe-clk: + description: + If present, disable USB3 pipe_clk requirement. + Used when dwc3 operates without SSPHY and only + HS/FS/LS modes are supported. + type: boolean + + wakeup-source: true + +# Required child node: + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + +allOf: + - $ref: snps,dwc3-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq4019-dwc3 + - qcom,ipq5332-dwc3 + then: + properties: + clocks: + maxItems: 3 + clock-names: + items: + - const: core + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq8064-dwc3 + then: + properties: + clocks: + items: + - description: Master/Core clock, has to be >=3D 125 MHz + for SS operation and >=3D 60MHz for HS operation. + clock-names: + items: + - const: core + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq9574-dwc3 + - qcom,msm8953-dwc3 + - qcom,msm8996-dwc3 + - qcom,msm8998-dwc3 + - qcom,qcs8300-dwc3 + - qcom,sa8775p-dwc3 + - qcom,sc7180-dwc3 + - qcom,sc7280-dwc3 + - qcom,sdm670-dwc3 + - qcom,sdm845-dwc3 + - qcom,sdx55-dwc3 + - qcom,sdx65-dwc3 + - qcom,sdx75-dwc3 + - qcom,sm6350-dwc3 + then: + properties: + clocks: + maxItems: 5 + clock-names: + items: + - const: cfg_noc + - const: core + - const: iface + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq6018-dwc3 + then: + properties: + clocks: + minItems: 3 + maxItems: 4 + clock-names: + oneOf: + - items: + - const: core + - const: sleep + - const: mock_utmi + - items: + - const: cfg_noc + - const: core + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq8074-dwc3 + - qcom,qdu1000-dwc3 + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: cfg_noc + - const: core + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5018-dwc3 + - qcom,msm8994-dwc3 + - qcom,qcs404-dwc3 + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: core + - const: iface + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-dwc3 + - qcom,sc8280xp-dwc3-mp + - qcom,x1e80100-dwc3 + - qcom,x1e80100-dwc3-mp + then: + properties: + clocks: + maxItems: 9 + clock-names: + items: + - const: cfg_noc + - const: core + - const: iface + - const: sleep + - const: mock_utmi + - const: noc_aggr + - const: noc_aggr_north + - const: noc_aggr_south + - const: noc_sys + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm660-dwc3 + then: + properties: + clocks: + minItems: 4 + maxItems: 5 + clock-names: + oneOf: + - items: + - const: cfg_noc + - const: core + - const: iface + - const: sleep + - const: mock_utmi + - items: + - const: cfg_noc + - const: core + - const: sleep + - const: mock_utmi + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcm2290-dwc3 + - qcom,qcs615-dwc3 + - qcom,sar2130p-dwc3 + - qcom,sc8180x-dwc3 + - qcom,sc8180x-dwc3-mp + - qcom,sm6115-dwc3 + - qcom,sm6125-dwc3 + - qcom,sm8150-dwc3 + - qcom,sm8250-dwc3 + - qcom,sm8450-dwc3 + - qcom,sm8550-dwc3 + - qcom,sm8650-dwc3 + then: + properties: + clocks: + minItems: 6 + clock-names: + items: + - const: cfg_noc + - const: core + - const: iface + - const: sleep + - const: mock_utmi + - const: xo + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8350-dwc3 + then: + properties: + clocks: + minItems: 5 + maxItems: 6 + clock-names: + minItems: 5 + items: + - const: cfg_noc + - const: core + - const: iface + - const: sleep + - const: mock_utmi + - const: xo + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5018-dwc3 + - qcom,ipq6018-dwc3 + - qcom,ipq8074-dwc3 + - qcom,msm8953-dwc3 + - qcom,msm8998-dwc3 + then: + properties: + interrupts: + minItems: 3 + maxItems: 4 + interrupt-names: + minItems: 3 + items: + - const: dwc_usb3 + - const: pwr_event + - const: qusb2_phy + - const: ss_phy_irq + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8996-dwc3 + - qcom,qcs404-dwc3 + - qcom,sdm660-dwc3 + - qcom,sm6115-dwc3 + - qcom,sm6125-dwc3 + then: + properties: + interrupts: + minItems: 4 + maxItems: 5 + interrupt-names: + minItems: 4 + items: + - const: dwc_usb3 + - const: pwr_event + - const: qusb2_phy + - const: hs_phy_irq + - const: ss_phy_irq + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5332-dwc3 + then: + properties: + interrupts: + maxItems: 4 + interrupt-names: + items: + - const: dwc_usb3 + - const: pwr_event + - const: dp_hs_phy_irq + - const: dm_hs_phy_irq + + - if: + properties: + compatible: + contains: + enum: + - qcom,x1e80100-dwc3 + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + items: + - const: dwc_usb3 + - const: pwr_event + - const: dp_hs_phy_irq + - const: dm_hs_phy_irq + - const: ss_phy_irq + + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq4019-dwc3 + - qcom,ipq8064-dwc3 + - qcom,msm8994-dwc3 + - qcom,qcs615-dwc3 + - qcom,qcs8300-dwc3 + - qcom,qdu1000-dwc3 + - qcom,sa8775p-dwc3 + - qcom,sc7180-dwc3 + - qcom,sc7280-dwc3 + - qcom,sc8180x-dwc3 + - qcom,sc8280xp-dwc3 + - qcom,sdm670-dwc3 + - qcom,sdm845-dwc3 + - qcom,sdx55-dwc3 + - qcom,sdx65-dwc3 + - qcom,sdx75-dwc3 + - qcom,sm4250-dwc3 + - qcom,sm6350-dwc3 + - qcom,sm8150-dwc3 + - qcom,sm8250-dwc3 + - qcom,sm8350-dwc3 + - qcom,sm8450-dwc3 + - qcom,sm8550-dwc3 + - qcom,sm8650-dwc3 + then: + properties: + interrupts: + minItems: 5 + maxItems: 6 + interrupt-names: + minItems: 5 + items: + - const: dwc_usb3 + - const: pwr_event + - const: hs_phy_irq + - const: dp_hs_phy_irq + - const: dm_hs_phy_irq + - const: ss_phy_irq + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-dwc3-mp + - qcom,x1e80100-dwc3-mp + then: + properties: + interrupts: + minItems: 11 + maxItems: 11 + interrupt-names: + items: + - const: dwc_usb3 + - const: pwr_event_1 + - const: pwr_event_2 + - const: hs_phy_1 + - const: hs_phy_2 + - const: dp_hs_phy_1 + - const: dm_hs_phy_1 + - const: dp_hs_phy_2 + - const: dm_hs_phy_2 + - const: ss_phy_1 + - const: ss_phy_2 + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-dwc3-mp + then: + properties: + interrupts: + minItems: 19 + maxItems: 19 + interrupt-names: + items: + - const: dwc_usb3 + - const: pwr_event_1 + - const: pwr_event_2 + - const: pwr_event_3 + - const: pwr_event_4 + - const: hs_phy_1 + - const: hs_phy_2 + - const: hs_phy_3 + - const: hs_phy_4 + - const: dp_hs_phy_1 + - const: dm_hs_phy_1 + - const: dp_hs_phy_2 + - const: dm_hs_phy_2 + - const: dp_hs_phy_3 + - const: dm_hs_phy_3 + - const: dp_hs_phy_4 + - const: dm_hs_phy_4 + - const: ss_phy_1 + - const: ss_phy_2 + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + usb@a600000 { + compatible =3D "qcom,sdm845-dwc3", "qcom,snps-dwc3"; + reg =3D <0 0x0a600000 0 0x100000>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks =3D <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <150000000>; + + interrupts =3D , + , + , + , + , + ; + interrupt-names =3D "dwc_usb3", "pwr_event", "hs_phy_irq", + "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains =3D <&gcc USB30_PRIM_GDSC>; + + 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-2d0969589basm958677fac.19.2025.04.10.20.50.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Apr 2025 20:50:25 -0700 (PDT) From: Bjorn Andersson Date: Thu, 10 Apr 2025 22:50:14 -0500 Subject: [PATCH v6 3/6] usb: dwc3: core: Expose core driver as library Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250410-dwc3-refactor-v6-3-dc0d1b336135@oss.qualcomm.com> References: <20250410-dwc3-refactor-v6-0-dc0d1b336135@oss.qualcomm.com> In-Reply-To: <20250410-dwc3-refactor-v6-0-dc0d1b336135@oss.qualcomm.com> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Wesley Cheng , Saravana Kannan , Thinh Nguyen , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Frank Li Cc: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Andersson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10188; i=bjorn.andersson@oss.qualcomm.com; h=from:subject:message-id; bh=YWW7h0HqgMyquql1fS+ddwkaCtxiI0GAg99bBKTcrm4=; b=owEBgwJ8/ZANAwAIAQsfOT8Nma3FAcsmYgBn+JF9VxuKSCf5swaUGAlT+Y3KpsZkiVLxVd+bZ hqnC9HS9lOJAkkEAAEIADMWIQQF3gPMXzXqTwlm1SULHzk/DZmtxQUCZ/iRfRUcYW5kZXJzc29u QGtlcm5lbC5vcmcACgkQCx85Pw2ZrcVOMw//T6LuVh86V0bhjrPCzBaAXUxmKY2kr0oZxapsbGm XA9rgPdPqZyLamGOT54gDLlvR7ik/1vciKtKoJUir3AxMdmw9Y6ZCw8Fs88ryc03QmogZh4yh/T ZYa/xC9gemSquvSGTzadllCK2am0Pb860fIwLE3VuQL0lMwFVrzkrmWCjaX7UmxmvZ1T02RSK8g CDYYdb8siK1XFFe/ALgU8L2XVqzPwNKfGJdNzzLklO5Y0MT7QhI6Td7aVplhPcLR7PlIjRRs/cV TnS1riHqW6Wb6pC6Go8rAvCjovBk4ionp2kCe+YSl0jf74teJClB6vz4H7nqMHsfaSc+omeAiim q03qSyl3TsGqngMLyFxNwa6E+kYdjDJ4Fv8RqGbmnyKut3qaeHgw4vslxXUIN3E/Sj3sveVvNLq MrR2n4vo4RXd2Avcw0qfsGaDiVFGLJL7tmTH18tmGqEKU9RdbPd8HSDgg8UKkJsQnS0YcEf/c09 /vuUw8D9mzV+hckjTZvdA5FdvVnNlK/N1HPfl+HPLXf5oQ2y/qmtPT2cDkt7cQYtjRvwFenOe1C TAEyBSgPGKR4K9x6eo9EOZAVp1cuG0VjTaJjBS+odV+aujGU6sVJI0742v8BR0PS3GHRII+9V6n zBD1KTWMCZ6+Ft0F2nShQxvqXL0fE5qMF9T/ojlCf42k= X-Developer-Key: i=bjorn.andersson@oss.qualcomm.com; a=openpgp; fpr=05DE03CC5F35EA4F0966D5250B1F393F0D99ADC5 X-Proofpoint-ORIG-GUID: sHrctOZFYQ2m7ysg1ExJbnuZ6WoGM7Al X-Authority-Analysis: v=2.4 cv=QuVe3Uyd c=1 sm=1 tr=0 ts=67f89183 cx=c_pps a=Z3eh007fzM5o9awBa1HkYQ==:117 a=DaeiM5VmU20ml6RIjrOvYw==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=jIQo8A4GAAAA:8 a=EUspDBNiAAAA:8 a=bGkOf_LmPnIWPiKmcZAA:9 a=QEXdDO2ut3YA:10 a=eBU8X_Hb5SQ8N-bgNfv4:22 X-Proofpoint-GUID: sHrctOZFYQ2m7ysg1ExJbnuZ6WoGM7Al X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-11_01,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 spamscore=0 malwarescore=0 mlxlogscore=999 bulkscore=0 priorityscore=1501 clxscore=1015 phishscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504110026 The DWC3 IP block is handled by three distinct device drivers: XHCI, DWC3 core and a platform specific (optional) DWC3 glue driver. This has resulted in, at least in the case of the Qualcomm glue, the presence of a number of layering violations, where the glue code either can't handle, or has to work around, the fact that core might not probe deterministically. An example of this is that the suspend path should operate slightly different depending on the device operating in host or peripheral mode, and the only way to determine the operating state is to peek into the core's drvdata. The Qualcomm glue driver is expected to make updates in the qscratch register region (the "glue" region) during role switch events, but with the glue and core split using the driver model, there is no reasonable way to introduce listeners for mode changes. Split the dwc3 core platform_driver callbacks and their implementation and export the implementation, to make it possible to deterministically instantiate the dwc3 core as part of the dwc3 glue drivers and to allow flattening of the DeviceTree representation. Acked-by: Thinh Nguyen Signed-off-by: Bjorn Andersson Tested-by: Neil Armstrong # on SM8650-QRD --- drivers/usb/dwc3/core.c | 142 +++++++++++++++++++++++++++++++++-----------= ---- drivers/usb/dwc3/glue.h | 32 +++++++++++ 2 files changed, 129 insertions(+), 45 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 66a08b5271653abd458f9ec85ca730afd7779d71..b428b6fc3d0a55811e2f75d33d7= 9df4b0c67dcac 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -36,6 +36,7 @@ =20 #include "core.h" #include "gadget.h" +#include "glue.h" #include "io.h" =20 #include "debug.h" @@ -2148,27 +2149,16 @@ static struct power_supply *dwc3_get_usb_power_supp= ly(struct dwc3 *dwc) return usb_psy; } =20 -static int dwc3_probe(struct platform_device *pdev) +int dwc3_core_probe(const struct dwc3_probe_data *data) { - struct device *dev =3D &pdev->dev; - struct resource *res, dwc_res; + struct dwc3 *dwc =3D data->dwc; + struct device *dev =3D dwc->dev; + struct resource dwc_res; unsigned int hw_mode; void __iomem *regs; - struct dwc3 *dwc; + struct resource *res =3D data->res; int ret; =20 - dwc =3D devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL); - if (!dwc) - return -ENOMEM; - - dwc->dev =3D dev; - - res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(dev, "missing memory resource\n"); - return -ENODEV; - } - dwc->xhci_resources[0].start =3D res->start; dwc->xhci_resources[0].end =3D dwc->xhci_resources[0].start + DWC3_XHCI_REGS_END; @@ -2232,7 +2222,7 @@ static int dwc3_probe(struct platform_device *pdev) goto err_disable_clks; } =20 - platform_set_drvdata(pdev, dwc); + dev_set_drvdata(dev, dwc); dwc3_cache_hwparams(dwc); =20 if (!dwc->sysdev_is_parent && @@ -2327,12 +2317,35 @@ static int dwc3_probe(struct platform_device *pdev) =20 return ret; } +EXPORT_SYMBOL_GPL(dwc3_core_probe); =20 -static void dwc3_remove(struct platform_device *pdev) +static int dwc3_probe(struct platform_device *pdev) { - struct dwc3 *dwc =3D platform_get_drvdata(pdev); + struct dwc3_probe_data probe_data; + struct resource *res; + struct dwc3 *dwc; =20 - pm_runtime_get_sync(&pdev->dev); + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "missing memory resource\n"); + return -ENODEV; + } + + dwc =3D devm_kzalloc(&pdev->dev, sizeof(*dwc), GFP_KERNEL); + if (!dwc) + return -ENOMEM; + + dwc->dev =3D &pdev->dev; + + probe_data.dwc =3D dwc; + probe_data.res =3D res; + + return dwc3_core_probe(&probe_data); +} + +void dwc3_core_remove(struct dwc3 *dwc) +{ + pm_runtime_get_sync(dwc->dev); =20 dwc3_core_exit_mode(dwc); dwc3_debugfs_exit(dwc); @@ -2340,22 +2353,28 @@ static void dwc3_remove(struct platform_device *pde= v) dwc3_core_exit(dwc); dwc3_ulpi_exit(dwc); =20 - pm_runtime_allow(&pdev->dev); - pm_runtime_disable(&pdev->dev); - pm_runtime_dont_use_autosuspend(&pdev->dev); - pm_runtime_put_noidle(&pdev->dev); + pm_runtime_allow(dwc->dev); + pm_runtime_disable(dwc->dev); + pm_runtime_dont_use_autosuspend(dwc->dev); + pm_runtime_put_noidle(dwc->dev); /* * HACK: Clear the driver data, which is currently accessed by parent * glue drivers, before allowing the parent to suspend. */ - platform_set_drvdata(pdev, NULL); - pm_runtime_set_suspended(&pdev->dev); + dev_set_drvdata(dwc->dev, NULL); + pm_runtime_set_suspended(dwc->dev); =20 dwc3_free_event_buffers(dwc); =20 if (dwc->usb_psy) power_supply_put(dwc->usb_psy); } +EXPORT_SYMBOL_GPL(dwc3_core_remove); + +static void dwc3_remove(struct platform_device *pdev) +{ + dwc3_core_remove(platform_get_drvdata(pdev)); +} =20 #ifdef CONFIG_PM static int dwc3_core_init_for_resume(struct dwc3 *dwc) @@ -2544,9 +2563,8 @@ static int dwc3_runtime_checks(struct dwc3 *dwc) return 0; } =20 -static int dwc3_runtime_suspend(struct device *dev) +int dwc3_runtime_suspend(struct dwc3 *dwc) { - struct dwc3 *dwc =3D dev_get_drvdata(dev); int ret; =20 if (dwc3_runtime_checks(dwc)) @@ -2558,10 +2576,11 @@ static int dwc3_runtime_suspend(struct device *dev) =20 return 0; } +EXPORT_SYMBOL_GPL(dwc3_runtime_suspend); =20 -static int dwc3_runtime_resume(struct device *dev) +int dwc3_runtime_resume(struct dwc3 *dwc) { - struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct device *dev =3D dwc->dev; int ret; =20 ret =3D dwc3_resume_common(dwc, PMSG_AUTO_RESUME); @@ -2571,7 +2590,7 @@ static int dwc3_runtime_resume(struct device *dev) switch (dwc->current_dr_role) { case DWC3_GCTL_PRTCAP_DEVICE: if (dwc->pending_events) { - pm_runtime_put(dwc->dev); + pm_runtime_put(dev); dwc->pending_events =3D false; enable_irq(dwc->irq_gadget); } @@ -2586,10 +2605,11 @@ static int dwc3_runtime_resume(struct device *dev) =20 return 0; } +EXPORT_SYMBOL_GPL(dwc3_runtime_resume); =20 -static int dwc3_runtime_idle(struct device *dev) +int dwc3_runtime_idle(struct dwc3 *dwc) { - struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct device *dev =3D dwc->dev; =20 switch (dwc->current_dr_role) { case DWC3_GCTL_PRTCAP_DEVICE: @@ -2607,12 +2627,28 @@ static int dwc3_runtime_idle(struct device *dev) =20 return 0; } +EXPORT_SYMBOL_GPL(dwc3_runtime_idle); + +static int dwc3_plat_runtime_suspend(struct device *dev) +{ + return dwc3_runtime_suspend(dev_get_drvdata(dev)); +} + +static int dwc3_plat_runtime_resume(struct device *dev) +{ + return dwc3_runtime_resume(dev_get_drvdata(dev)); +} + +static int dwc3_plat_runtime_idle(struct device *dev) +{ + return dwc3_runtime_idle(dev_get_drvdata(dev)); +} #endif /* CONFIG_PM */ =20 #ifdef CONFIG_PM_SLEEP -static int dwc3_suspend(struct device *dev) +int dwc3_pm_suspend(struct dwc3 *dwc) { - struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct device *dev =3D dwc->dev; int ret; =20 ret =3D dwc3_suspend_common(dwc, PMSG_SUSPEND); @@ -2623,10 +2659,11 @@ static int dwc3_suspend(struct device *dev) =20 return 0; } +EXPORT_SYMBOL_GPL(dwc3_pm_suspend); =20 -static int dwc3_resume(struct device *dev) +int dwc3_pm_resume(struct dwc3 *dwc) { - struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct device *dev =3D dwc->dev; int ret =3D 0; =20 pinctrl_pm_select_default_state(dev); @@ -2645,10 +2682,10 @@ static int dwc3_resume(struct device *dev) =20 return ret; } +EXPORT_SYMBOL_GPL(dwc3_pm_resume); =20 -static void dwc3_complete(struct device *dev) +void dwc3_pm_complete(struct dwc3 *dwc) { - struct dwc3 *dwc =3D dev_get_drvdata(dev); u32 reg; =20 if (dwc->current_dr_role =3D=3D DWC3_GCTL_PRTCAP_HOST && @@ -2658,21 +2695,36 @@ static void dwc3_complete(struct device *dev) dwc3_writel(dwc->regs, DWC3_GUCTL3, reg); } } +EXPORT_SYMBOL_GPL(dwc3_pm_complete); + +static int dwc3_plat_suspend(struct device *dev) +{ + return dwc3_pm_suspend(dev_get_drvdata(dev)); +} + +static int dwc3_plat_resume(struct device *dev) +{ + return dwc3_pm_resume(dev_get_drvdata(dev)); +} + +static void dwc3_plat_complete(struct device *dev) +{ + dwc3_pm_complete(dev_get_drvdata(dev)); +} #else -#define dwc3_complete NULL +#define dwc3_plat_complete NULL #endif /* CONFIG_PM_SLEEP */ =20 static const struct dev_pm_ops dwc3_dev_pm_ops =3D { - SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume) - .complete =3D dwc3_complete, - + SET_SYSTEM_SLEEP_PM_OPS(dwc3_plat_suspend, dwc3_plat_resume) + .complete =3D dwc3_plat_complete, /* * Runtime suspend halts the controller on disconnection. It relies on * platforms with custom connection notification to start the controller * again. */ - SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume, - dwc3_runtime_idle) + SET_RUNTIME_PM_OPS(dwc3_plat_runtime_suspend, dwc3_plat_runtime_resume, + dwc3_plat_runtime_idle) }; =20 #ifdef CONFIG_OF diff --git a/drivers/usb/dwc3/glue.h b/drivers/usb/dwc3/glue.h new file mode 100644 index 0000000000000000000000000000000000000000..e73cfc466012f07214291abe564= 54934ab014013 --- /dev/null +++ b/drivers/usb/dwc3/glue.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * glue.h - DesignWare USB3 DRD glue header + */ + +#ifndef __DRIVERS_USB_DWC3_GLUE_H +#define __DRIVERS_USB_DWC3_GLUE_H + +#include +#include "core.h" + +/** + * dwc3_probe_data: Initialization parameters passed to dwc3_core_probe() + * @dwc: Reference to dwc3 context structure + * @res: resource for the DWC3 core mmio region + */ +struct dwc3_probe_data { + struct dwc3 *dwc; + struct resource *res; +}; + +int dwc3_core_probe(const struct dwc3_probe_data *data); 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As such the glue must own these resources and be allowed to turn them on/off outside the core's handling. Allow the platform or glue layer to indicate if the core logic for clocks and resets should be skipped to deal with this. Reviewed-by: Frank Li Acked-by: Thinh Nguyen Signed-off-by: Bjorn Andersson Tested-by: Neil Armstrong # on SM8650-QRD --- drivers/usb/dwc3/core.c | 20 +++++++++++--------- drivers/usb/dwc3/glue.h | 3 +++ 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index b428b6fc3d0a55811e2f75d33d79df4b0c67dcac..77a9848a0ac70fbe563988cecbe= 489130989aadc 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -2198,15 +2198,17 @@ int dwc3_core_probe(const struct dwc3_probe_data *d= ata) if (IS_ERR(dwc->usb_psy)) return dev_err_probe(dev, PTR_ERR(dwc->usb_psy), "couldn't get usb power= supply\n"); =20 - dwc->reset =3D devm_reset_control_array_get_optional_shared(dev); - if (IS_ERR(dwc->reset)) { - ret =3D PTR_ERR(dwc->reset); - goto err_put_psy; - } + if (!data->ignore_clocks_and_resets) { + dwc->reset =3D devm_reset_control_array_get_optional_shared(dev); + if (IS_ERR(dwc->reset)) { + ret =3D PTR_ERR(dwc->reset); + goto err_put_psy; + } =20 - ret =3D dwc3_get_clocks(dwc); - if (ret) - goto err_put_psy; + ret =3D dwc3_get_clocks(dwc); + if (ret) + goto err_put_psy; + } =20 ret =3D reset_control_deassert(dwc->reset); if (ret) @@ -2321,7 +2323,7 @@ EXPORT_SYMBOL_GPL(dwc3_core_probe); =20 static int dwc3_probe(struct platform_device *pdev) { - struct dwc3_probe_data probe_data; + struct dwc3_probe_data probe_data =3D {}; struct resource *res; struct dwc3 *dwc; =20 diff --git a/drivers/usb/dwc3/glue.h b/drivers/usb/dwc3/glue.h index e73cfc466012f07214291abe56454934ab014013..703d40c189565b1e28ae28afb87= 28b78f4cd2fca 100644 --- a/drivers/usb/dwc3/glue.h +++ b/drivers/usb/dwc3/glue.h @@ -13,10 +13,13 @@ * dwc3_probe_data: Initialization parameters passed to dwc3_core_probe() * @dwc: Reference to dwc3 context structure * @res: resource for the DWC3 core mmio region + * @ignore_clocks_and_resets: clocks and resets defined for the device sho= uld + * be ignored by the DWC3 core, as they are managed by the glue */ struct dwc3_probe_data { struct dwc3 *dwc; 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-2d0969589basm958677fac.19.2025.04.10.20.50.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Apr 2025 20:50:27 -0700 (PDT) From: Bjorn Andersson Date: Thu, 10 Apr 2025 22:50:16 -0500 Subject: [PATCH v6 5/6] usb: dwc3: qcom: Don't rely on drvdata during probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250410-dwc3-refactor-v6-5-dc0d1b336135@oss.qualcomm.com> References: <20250410-dwc3-refactor-v6-0-dc0d1b336135@oss.qualcomm.com> In-Reply-To: <20250410-dwc3-refactor-v6-0-dc0d1b336135@oss.qualcomm.com> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Wesley Cheng , Saravana Kannan , Thinh Nguyen , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Frank Li Cc: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Andersson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3136; i=bjorn.andersson@oss.qualcomm.com; h=from:subject:message-id; bh=RSuxk/dHzfMuHqU3U1cL04m7MqJ/Ml8N36LwtwzR9Og=; b=owEBgwJ8/ZANAwAIAQsfOT8Nma3FAcsmYgBn+JF9qiL5G7nhdRn0u6cP1Jl7oF5pjHpLTc1Ut b2tAJuY2GuJAkkEAAEIADMWIQQF3gPMXzXqTwlm1SULHzk/DZmtxQUCZ/iRfRUcYW5kZXJzc29u QGtlcm5lbC5vcmcACgkQCx85Pw2ZrcV3FQ/+PsV3vdTXi8T+b41VDzzOy0p8rFRKUvPN8x480LO tjt/YfilpIndvUZagukl92ZMdTlH9Kil18eJGuyK9uwsjG9kZ7SOsvd9eMg7qSlKekj3kDkMA9J 236qsQIWH9YqOT0DXaswHJiVqNl96TyfZw6l1EtZYQl8CSCOyqiZtXLEI49rYwocaOwjCEjmGgt LX3HLOpuWhlwu1l2bPhg1G0JRTxlJzGc+gelHYuT1DdGMJDOROz2i+yDYjU1X7q70Vi7xgxSIrw gpUd77j28R4eB2agSO7id2ewsMhwB+6NhN9STZ9U+5rfXrFG+MkGbaqsztdqH850lXRrmh2sjj2 cce3/RWdT+x3/dizxxk8QQr824dF9sYa2jiwjtf9Ct6k6QKgbG1ew6a2tf4xWXIdnJdaASK8h+x 3TIoFgMuJVlrp+6LrjSbn+x0WruBO5ZJRbpVEiwD9IygAj14UHyIg9mwojCeWO7J2XlYrPt4+/W a0zDeHNz1FKRqQXUHzvzUef8MjxvELWYxAs3MdTOLah+Camprkc/uCPVEMAEvipdTZXMcl4qbce s55datCM/lYZDPUII3EDpA1CYIierVskd+8vhr7tTyLptjEbJUCqGOicqWRLM7bJzbT/L/u73Bu zWpE9yod4VOu7okl9xigZmH4smAQQBjp72u+PZQY4vxY= X-Developer-Key: i=bjorn.andersson@oss.qualcomm.com; a=openpgp; fpr=05DE03CC5F35EA4F0966D5250B1F393F0D99ADC5 X-Proofpoint-ORIG-GUID: EuwgQCGTPwNVgyiiYXi9P3DivXc_y1N2 X-Proofpoint-GUID: EuwgQCGTPwNVgyiiYXi9P3DivXc_y1N2 X-Authority-Analysis: v=2.4 cv=NaLm13D4 c=1 sm=1 tr=0 ts=67f8918a cx=c_pps a=zPxD6eHSjdtQ/OcAcrOFGw==:117 a=DaeiM5VmU20ml6RIjrOvYw==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=jIQo8A4GAAAA:8 a=EUspDBNiAAAA:8 a=0UB9HjPGtwcCTtCM8zIA:9 a=QEXdDO2ut3YA:10 a=y8BKWJGFn5sdPF1Y92-H:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-11_01,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 priorityscore=1501 adultscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=999 clxscore=1015 phishscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504110026 With the upcoming transition to a model where DWC3 core and glue operate on a single struct device the drvdata datatype will change to be owned by the core. The drvdata is however used by the Qualcomm DWC3 glue to pass the qcom glue context around before the core is allocated. Remove this problem, and clean up the code, by passing the dwc3_qcom struct around during probe, instead of acquiring it from the drvdata. Acked-by: Thinh Nguyen Signed-off-by: Bjorn Andersson Tested-by: Neil Armstrong # on SM8650-QRD --- drivers/usb/dwc3/dwc3-qcom.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 79f3600f25c41a5ed770f164a03c7dc424b01440..9d04c2457433bd6bcd96c445f59= d7f2a3c6fdf24 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -547,9 +547,10 @@ static int dwc3_qcom_request_irq(struct dwc3_qcom *qco= m, int irq, return ret; } =20 -static int dwc3_qcom_setup_port_irq(struct platform_device *pdev, int port= _index, bool is_multiport) +static int dwc3_qcom_setup_port_irq(struct dwc3_qcom *qcom, + struct platform_device *pdev, + int port_index, bool is_multiport) { - struct dwc3_qcom *qcom =3D platform_get_drvdata(pdev); const char *irq_name; int irq; int ret; @@ -634,9 +635,8 @@ static int dwc3_qcom_find_num_ports(struct platform_dev= ice *pdev) return DWC3_QCOM_MAX_PORTS; } =20 -static int dwc3_qcom_setup_irq(struct platform_device *pdev) +static int dwc3_qcom_setup_irq(struct dwc3_qcom *qcom, struct platform_dev= ice *pdev) { - struct dwc3_qcom *qcom =3D platform_get_drvdata(pdev); bool is_multiport; int ret; int i; @@ -645,7 +645,7 @@ static int dwc3_qcom_setup_irq(struct platform_device *= pdev) is_multiport =3D (qcom->num_ports > 1); =20 for (i =3D 0; i < qcom->num_ports; i++) { - ret =3D dwc3_qcom_setup_port_irq(pdev, i, is_multiport); + ret =3D dwc3_qcom_setup_port_irq(qcom, pdev, i, is_multiport); if (ret) return ret; } @@ -700,9 +700,8 @@ static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, i= nt count) return 0; } =20 -static int dwc3_qcom_of_register_core(struct platform_device *pdev) +static int dwc3_qcom_of_register_core(struct dwc3_qcom *qcom, struct platf= orm_device *pdev) { - struct dwc3_qcom *qcom =3D platform_get_drvdata(pdev); struct device_node *np =3D pdev->dev.of_node; struct device *dev =3D &pdev->dev; int ret; @@ -778,7 +777,7 @@ static int dwc3_qcom_probe(struct platform_device *pdev) goto clk_disable; } =20 - ret =3D dwc3_qcom_setup_irq(pdev); + ret =3D dwc3_qcom_setup_irq(qcom, pdev); if (ret) { dev_err(dev, "failed to setup IRQs, err=3D%d\n", ret); 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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-2d0969589basm958677fac.19.2025.04.10.20.50.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Apr 2025 20:50:28 -0700 (PDT) From: Bjorn Andersson Date: Thu, 10 Apr 2025 22:50:17 -0500 Subject: [PATCH v6 6/6] usb: dwc3: qcom: Transition to flattened model Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250410-dwc3-refactor-v6-6-dc0d1b336135@oss.qualcomm.com> References: <20250410-dwc3-refactor-v6-0-dc0d1b336135@oss.qualcomm.com> In-Reply-To: <20250410-dwc3-refactor-v6-0-dc0d1b336135@oss.qualcomm.com> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Wesley Cheng , Saravana Kannan , Thinh Nguyen , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Frank Li Cc: linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Andersson X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=12567; i=bjorn.andersson@oss.qualcomm.com; h=from:subject:message-id; bh=JvFdgODbjBbS+ZvrfFLarjzmj9NETKrOx4wtULiGSAA=; b=owEBgwJ8/ZANAwAIAQsfOT8Nma3FAcsmYgBn+JF9eHa3ioDQ9ZpBdgq83qklg1RMCYlVjUneV UEhw4Uv+1yJAkkEAAEIADMWIQQF3gPMXzXqTwlm1SULHzk/DZmtxQUCZ/iRfRUcYW5kZXJzc29u QGtlcm5lbC5vcmcACgkQCx85Pw2ZrcXF+w//Z3MS8HtJShmjCcGq3htHOqqww0KJin0D7YbCI5s APCXkxwqXQlHtpGFHMKZ4bmlfJesj5ouU3odeyElQoB/gOhS4sQhmp+L/QNPXPGUGFGfWtxSi5e 5boZAoFy0jQ26ljjWGhIBeRcbNRUGyeN8CstRZtskgOeqDny8zCs9UdhnnQb37stc1l5r20FLpA C+dXQI8l3p5Q9KM73Pc/1uACZySDP46SThcRdoc8g8JxGkNctZYW2nuF6LQdZcsIq5BnYeF8lbo zPl36gWI/YMDQVJqilcjklsh2LcAjk6KtKNs9BLQ9EasliaRo09S5GuSbXJhDoKdGpNrXWoLCsR +s8g3J1I/qyvmuzdLOgceozyFJRgt+kmc61bVH80phTitRpTgPPS77Kc4VWw/F+5GrvXlTv93ZO 8lV4IxEe7AjTzHp6cTOGYXLIMYjgx4MHh6QWsOo8zwAcWamlB405IhdQT5h1GSkWxnxwubIRzhG eFGU84cnUwXZ2oQAUoz9w/Lyn0hSr1UxRjDQBVR/1ym+wBhqcKpBJcuoIB+L6yMu2SybSmTEoE4 grNVPWpI2iOPWtF5mpsbOixg6rwch3IRxB4++gcX7PbHNCAt5xRcnTEa3OZGKuwnJlDvbZtxAax 0emHpb0mFSpGEYIZlHz4bilWqQp7h0JwjESEkHCbQhs8= X-Developer-Key: i=bjorn.andersson@oss.qualcomm.com; a=openpgp; fpr=05DE03CC5F35EA4F0966D5250B1F393F0D99ADC5 X-Proofpoint-ORIG-GUID: uB17378G6MK4YvujOFigxxpnh0Rptz2W X-Authority-Analysis: v=2.4 cv=QuVe3Uyd c=1 sm=1 tr=0 ts=67f89186 cx=c_pps a=zPxD6eHSjdtQ/OcAcrOFGw==:117 a=DaeiM5VmU20ml6RIjrOvYw==:17 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=oNyuIvTq0u59PHEm3sEA:9 a=QEXdDO2ut3YA:10 a=y8BKWJGFn5sdPF1Y92-H:22 X-Proofpoint-GUID: uB17378G6MK4YvujOFigxxpnh0Rptz2W X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-11_01,2025-04-10_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 spamscore=0 malwarescore=0 mlxlogscore=999 bulkscore=0 priorityscore=1501 clxscore=1015 phishscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504110026 The USB IP-block found in most Qualcomm platforms is modelled in the Linux kernel as 3 different independent device drivers, but as shown by the already existing layering violations in the Qualcomm glue driver they can not be operated independently. With the current implementation, the glue driver registers the core and has no way to know when this is done. As a result, e.g. the suspend callbacks needs to guard against NULL pointer dereferences when trying to peek into the struct dwc3 found in the drvdata of the child. Even with these checks, there are no way to fully protect ourselves from the race conditions that occur if the DWC3 is unbound. Missing from the upstream Qualcomm USB support is handling of role switching, in which the glue needs to be notified upon DRD mode changes. Several attempts has been made through the years to register callbacks etc, but they always fall short when it comes to handling of the core's probe deferral on resources etc. Moving to a model where the DWC3 core is instantiated in a synchronous fashion avoids above described race conditions. It is however not feasible to do so without also flattening the DeviceTree binding, as assumptions are made in the DWC3 core and frameworks used that the device's associated of_node will the that of the core. Furthermore, the DeviceTree binding is a direct representation of the Linux driver model, and doesn't necessarily describe "the USB IP-block". The Qualcomm DWC3 glue driver is therefor transitioned to initialize and operate the DWC3 within the one device context, in synchronous fashion. To provide a limited time backwards compatibility, a snapshot of the driver is retained in a previous commit. As such no care is taken in the dwc3-qcom driver for the qcom,dwc3 backwards compatibility. Signed-off-by: Bjorn Andersson Tested-by: Neil Armstrong # on SM8650-QRD --- drivers/usb/dwc3/dwc3-qcom.c | 168 +++++++++++++++++++++++----------------= ---- 1 file changed, 90 insertions(+), 78 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 9d04c2457433bd6bcd96c445f59d7f2a3c6fdf24..59a3117b0f6b66949643f2b563f= d6dc27c6a2fbf 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -4,7 +4,6 @@ * Inspired by dwc3-of-simple.c */ =20 -#include #include #include #include @@ -14,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -23,6 +21,7 @@ #include #include #include "core.h" +#include "glue.h" =20 /* USB QSCRATCH Hardware registers */ #define QSCRATCH_HS_PHY_CTRL 0x10 @@ -73,7 +72,7 @@ struct dwc3_qcom_port { struct dwc3_qcom { struct device *dev; void __iomem *qscratch_base; - struct platform_device *dwc3; + struct dwc3 dwc; struct clk **clks; int num_clocks; struct reset_control *resets; @@ -92,6 +91,8 @@ struct dwc3_qcom { struct icc_path *icc_path_apps; }; =20 +#define to_dwc3_qcom(d) container_of((d), struct dwc3_qcom, dwc) + static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 v= al) { u32 reg; @@ -116,6 +117,11 @@ static inline void dwc3_qcom_clrbits(void __iomem *bas= e, u32 offset, u32 val) readl(base + offset); } =20 +/* + * TODO: Make the in-core role switching code invoke dwc3_qcom_vbus_overri= de_enable(), + * validate that the in-core extcon support is functional, and drop extcon + * handling from the glue + */ static void dwc3_qcom_vbus_override_enable(struct dwc3_qcom *qcom, bool en= able) { if (enable) { @@ -260,7 +266,7 @@ static int dwc3_qcom_interconnect_init(struct dwc3_qcom= *qcom) goto put_path_ddr; } =20 - max_speed =3D usb_get_maximum_speed(&qcom->dwc3->dev); + max_speed =3D usb_get_maximum_speed(qcom->dwc.dev); if (max_speed >=3D USB_SPEED_SUPER || max_speed =3D=3D USB_SPEED_UNKNOWN)= { ret =3D icc_set_bw(qcom->icc_path_ddr, USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW); @@ -303,25 +309,14 @@ static void dwc3_qcom_interconnect_exit(struct dwc3_q= com *qcom) /* Only usable in contexts where the role can not change. */ static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom) { - struct dwc3 *dwc; - - /* - * FIXME: Fix this layering violation. - */ - dwc =3D platform_get_drvdata(qcom->dwc3); - - /* Core driver may not have probed yet. */ - if (!dwc) - return false; - - return dwc->xhci; + return qcom->dwc.xhci; } =20 static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *q= com, int port_index) { - struct dwc3 *dwc =3D platform_get_drvdata(qcom->dwc3); struct usb_device *udev; struct usb_hcd __maybe_unused *hcd; + struct dwc3 *dwc =3D &qcom->dwc; =20 /* * FIXME: Fix this layering violation. @@ -498,7 +493,7 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, boo= l wakeup) static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data) { struct dwc3_qcom *qcom =3D data; - struct dwc3 *dwc =3D platform_get_drvdata(qcom->dwc3); + struct dwc3 *dwc =3D &qcom->dwc; =20 /* If pm_suspended then let pm_resume take care of resuming h/w */ if (qcom->pm_suspended) @@ -700,40 +695,14 @@ static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom,= int count) return 0; } =20 -static int dwc3_qcom_of_register_core(struct dwc3_qcom *qcom, struct platf= orm_device *pdev) -{ - struct device_node *np =3D pdev->dev.of_node; - struct device *dev =3D &pdev->dev; - int ret; - - struct device_node *dwc3_np __free(device_node) =3D of_get_compatible_chi= ld(np, - "snps,dwc3"); - if (!dwc3_np) { - dev_err(dev, "failed to find dwc3 core child\n"); - return -ENODEV; - } - - ret =3D of_platform_populate(np, NULL, NULL, dev); - if (ret) { - dev_err(dev, "failed to register dwc3 core - %d\n", ret); - return ret; - } - - qcom->dwc3 =3D of_find_device_by_node(dwc3_np); - if (!qcom->dwc3) { - ret =3D -ENODEV; - dev_err(dev, "failed to get dwc3 platform device\n"); - of_platform_depopulate(dev); - } - - return ret; -} - static int dwc3_qcom_probe(struct platform_device *pdev) { + struct dwc3_probe_data probe_data =3D {}; struct device_node *np =3D pdev->dev.of_node; struct device *dev =3D &pdev->dev; struct dwc3_qcom *qcom; + struct resource res; + struct resource *r; int ret, i; bool ignore_pipe_clk; bool wakeup_source; @@ -742,7 +711,6 @@ static int dwc3_qcom_probe(struct platform_device *pdev) if (!qcom) return -ENOMEM; =20 - platform_set_drvdata(pdev, qcom); qcom->dev =3D &pdev->dev; =20 qcom->resets =3D devm_reset_control_array_get_optional_exclusive(dev); @@ -771,8 +739,15 @@ static int dwc3_qcom_probe(struct platform_device *pde= v) goto reset_assert; } =20 - qcom->qscratch_base =3D devm_platform_ioremap_resource(pdev, 0); + r =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) + goto clk_disable; + res =3D *r; + res.end =3D res.start + SDM845_QSCRATCH_BASE_OFFSET; + + qcom->qscratch_base =3D devm_ioremap(dev, res.end, SDM845_QSCRATCH_SIZE); if (IS_ERR(qcom->qscratch_base)) { + dev_err(dev, "failed to map qscratch region: %pe\n", qcom->qscratch_base= ); ret =3D PTR_ERR(qcom->qscratch_base); goto clk_disable; } @@ -792,17 +767,21 @@ static int dwc3_qcom_probe(struct platform_device *pd= ev) if (ignore_pipe_clk) dwc3_qcom_select_utmi_clk(qcom); =20 - ret =3D dwc3_qcom_of_register_core(qcom, pdev); - if (ret) { - dev_err(dev, "failed to register DWC3 Core, err=3D%d\n", ret); + qcom->dwc.dev =3D dev; + probe_data.dwc =3D &qcom->dwc; + probe_data.res =3D &res; + probe_data.ignore_clocks_and_resets =3D true; + ret =3D dwc3_core_probe(&probe_data); + if (ret) { + ret =3D dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); goto clk_disable; } =20 ret =3D dwc3_qcom_interconnect_init(qcom); if (ret) - goto depopulate; + goto remove_core; =20 - qcom->mode =3D usb_get_dr_mode(&qcom->dwc3->dev); + qcom->mode =3D usb_get_dr_mode(dev); =20 /* enable vbus override for device mode */ if (qcom->mode !=3D USB_DR_MODE_HOST) @@ -815,20 +794,15 @@ static int dwc3_qcom_probe(struct platform_device *pd= ev) =20 wakeup_source =3D of_property_read_bool(dev->of_node, "wakeup-source"); device_init_wakeup(&pdev->dev, wakeup_source); - device_init_wakeup(&qcom->dwc3->dev, wakeup_source); =20 qcom->is_suspended =3D false; - pm_runtime_set_active(dev); - pm_runtime_enable(dev); - pm_runtime_forbid(dev); =20 return 0; =20 interconnect_exit: dwc3_qcom_interconnect_exit(qcom); -depopulate: - of_platform_depopulate(&pdev->dev); - platform_device_put(qcom->dwc3); +remove_core: + dwc3_core_remove(&qcom->dwc); clk_disable: for (i =3D qcom->num_clocks - 1; i >=3D 0; i--) { clk_disable_unprepare(qcom->clks[i]); @@ -842,12 +816,11 @@ static int dwc3_qcom_probe(struct platform_device *pd= ev) =20 static void dwc3_qcom_remove(struct platform_device *pdev) { - struct dwc3_qcom *qcom =3D platform_get_drvdata(pdev); - struct device *dev =3D &pdev->dev; + struct dwc3 *dwc =3D platform_get_drvdata(pdev); + struct dwc3_qcom *qcom =3D to_dwc3_qcom(dwc); int i; =20 - of_platform_depopulate(&pdev->dev); - platform_device_put(qcom->dwc3); + dwc3_core_remove(&qcom->dwc); =20 for (i =3D qcom->num_clocks - 1; i >=3D 0; i--) { clk_disable_unprepare(qcom->clks[i]); @@ -857,17 +830,20 @@ static void dwc3_qcom_remove(struct platform_device *= pdev) =20 dwc3_qcom_interconnect_exit(qcom); reset_control_assert(qcom->resets); - - pm_runtime_allow(dev); - pm_runtime_disable(dev); } =20 -static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev) +#ifdef CONFIG_PM_SLEEP +static int dwc3_qcom_pm_suspend(struct device *dev) { - struct dwc3_qcom *qcom =3D dev_get_drvdata(dev); + struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct dwc3_qcom *qcom =3D to_dwc3_qcom(dwc); bool wakeup =3D device_may_wakeup(dev); int ret; =20 + ret =3D dwc3_pm_suspend(&qcom->dwc); + if (ret) + return ret; + ret =3D dwc3_qcom_suspend(qcom, wakeup); if (ret) return ret; @@ -877,9 +853,10 @@ static int __maybe_unused dwc3_qcom_pm_suspend(struct = device *dev) return 0; } =20 -static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev) +static int dwc3_qcom_pm_resume(struct device *dev) { - struct dwc3_qcom *qcom =3D dev_get_drvdata(dev); + struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct dwc3_qcom *qcom =3D to_dwc3_qcom(dwc); bool wakeup =3D device_may_wakeup(dev); int ret; =20 @@ -889,30 +866,65 @@ static int __maybe_unused dwc3_qcom_pm_resume(struct = device *dev) =20 qcom->pm_suspended =3D false; =20 + ret =3D dwc3_pm_resume(&qcom->dwc); + if (ret) + return ret; + return 0; } =20 -static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev) +static void dwc3_qcom_complete(struct device *dev) { - struct dwc3_qcom *qcom =3D dev_get_drvdata(dev); + struct dwc3 *dwc =3D dev_get_drvdata(dev); + + dwc3_pm_complete(dwc); +} +#else +#define dwc3_qcom_complete NULL +#endif /* CONFIG_PM_SLEEP */ + +#ifdef CONFIG_PM +static int dwc3_qcom_runtime_suspend(struct device *dev) +{ + struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct dwc3_qcom *qcom =3D to_dwc3_qcom(dwc); + int ret; + + ret =3D dwc3_runtime_suspend(&qcom->dwc); + if (ret) + return ret; =20 return dwc3_qcom_suspend(qcom, true); } =20 -static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev) +static int dwc3_qcom_runtime_resume(struct device *dev) { - struct dwc3_qcom *qcom =3D dev_get_drvdata(dev); + struct dwc3 *dwc =3D dev_get_drvdata(dev); + struct dwc3_qcom *qcom =3D to_dwc3_qcom(dwc); + int ret; =20 - return dwc3_qcom_resume(qcom, true); + ret =3D dwc3_qcom_resume(qcom, true); + if (ret) + return ret; + + return dwc3_runtime_resume(&qcom->dwc); +} + +static int dwc3_qcom_runtime_idle(struct device *dev) +{ + return dwc3_runtime_idle(dev_get_drvdata(dev)); } +#endif /* CONFIG_PM */ =20 static const struct dev_pm_ops dwc3_qcom_dev_pm_ops =3D { SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume) SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume, - NULL) + dwc3_qcom_runtime_idle) + .complete =3D dwc3_qcom_complete, }; =20 static const struct of_device_id dwc3_qcom_of_match[] =3D { + { .compatible =3D "qcom,snps-dwc3" }, { } }; MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match); --=20 2.49.0