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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4f505cf81bcsm373459173.10.2025.04.09.12.22.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Apr 2025 12:22:19 -0700 (PDT) From: Alex Elder To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, gregkh@linuxfoundation.org, jirislaby@kernel.org Cc: dlan@gentoo.org, benjamin.larsson@genexis.eu, bastien.curutchet@bootlin.com, andriy.shevchenko@linux.intel.com, u.kleine-koenig@baylibre.com, lkundrak@v3.sk, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: serial: 8250: support an optional second clock Date: Wed, 9 Apr 2025 14:22:11 -0500 Message-ID: <20250409192213.1130181-2-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250409192213.1130181-1-elder@riscstar.com> References: <20250409192213.1130181-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SpacemiT UART driver requires a bus clock to be enabled in addition to the primary function clock. Add the option to specify two clocks for an 8250-compatible UART, named "core" and "bus". If both are needed, require them to be named. Signed-off-by: Alex Elder Reviewed-by: Rob Herring (Arm) --- v2: Require both clocks to be specified with names for SpacemiT .../devicetree/bindings/serial/8250.yaml | 30 ++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documenta= tion/devicetree/bindings/serial/8250.yaml index dc0d52920575f..33d2016b65090 100644 --- a/Documentation/devicetree/bindings/serial/8250.yaml +++ b/Documentation/devicetree/bindings/serial/8250.yaml @@ -135,7 +135,16 @@ properties: clock-frequency: true =20 clocks: - maxItems: 1 + minItems: 1 + items: + - description: The core function clock + - description: An optional bus clock + + clock-names: + minItems: 1 + items: + - const: core + - const: bus =20 resets: maxItems: 1 @@ -224,6 +233,25 @@ required: - reg - interrupts =20 +if: + properties: + compatible: + contains: + const: spacemit,k1-uart +then: + required: [clock-names] + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 +else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + unevaluatedProperties: false =20 examples: --=20 2.45.2 From nobody Sat Feb 7 11:38:42 2026 Received: from mail-io1-f51.google.com (mail-io1-f51.google.com [209.85.166.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BC801E5205 for ; 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[73.228.159.35]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4f505cf81bcsm373459173.10.2025.04.09.12.22.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Apr 2025 12:22:20 -0700 (PDT) From: Alex Elder To: gregkh@linuxfoundation.org, jirislaby@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: dlan@gentoo.org, benjamin.larsson@genexis.eu, bastien.curutchet@bootlin.com, andriy.shevchenko@linux.intel.com, u.kleine-koenig@baylibre.com, lkundrak@v3.sk, devicetree@vger.kernel.org, linux-serial@vger.kernel.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] serial: 8250_of: add support for an optional bus clock Date: Wed, 9 Apr 2025 14:22:12 -0500 Message-ID: <20250409192213.1130181-3-elder@riscstar.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250409192213.1130181-1-elder@riscstar.com> References: <20250409192213.1130181-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SpacemiT UART requires a bus clock to be enabled, in addition to it's "normal" core clock. Look up the optional bus clock by name, and if that's found, look up the core clock using the name "core". Supplying a bus clock is optional. If no bus clock is needed, the the first/only clock is used for the core clock. Signed-off-by: Alex Elder --- v2: Update logic to more check for the optional bus clock first drivers/tty/serial/8250/8250_of.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/8250/8250_of.c b/drivers/tty/serial/8250/82= 50_of.c index 11c860ea80f60..a90a5462aa72a 100644 --- a/drivers/tty/serial/8250/8250_of.c +++ b/drivers/tty/serial/8250/8250_of.c @@ -123,7 +123,16 @@ static int of_platform_serial_setup(struct platform_de= vice *ofdev, =20 /* Get clk rate through clk driver if present */ if (!port->uartclk) { - info->clk =3D devm_clk_get_enabled(dev, NULL); + struct clk *bus_clk; + + bus_clk =3D devm_clk_get_optional_enabled(dev, "bus"); + if (IS_ERR(bus_clk)) { + ret =3D dev_err_probe(dev, PTR_ERR(bus_clk), "failed to get bus clock\n= "); + goto err_pmruntime; + } + + /* If the bus clock is required, core clock must be named */ + info->clk =3D devm_clk_get_enabled(dev, bus_clk ? "core" : NULL); if (IS_ERR(info->clk)) { ret =3D dev_err_probe(dev, PTR_ERR(info->clk), "failed to get clock\n"); goto err_pmruntime; --=20 2.45.2