From nobody Sat Feb 7 06:20:47 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41C5125F98A for ; Wed, 9 Apr 2025 12:22:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744201361; cv=none; b=oY+/IxmKl6ZP4EseLp8XbbfpWm5edeZNVs9RAeFbr3x6a+bW1pEGRLSvD9dAmMbKi0txKzeDGHxvnlqBIQM1rltWLqhHP6EITjyWP1s8UeqY+VzfZNDVvMv+uOjd0jyLAx/GSLHZm7a7bwt9aWfjymi06/w+ze6J/GS8TmAOvno= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744201361; c=relaxed/simple; bh=oJ6F4PKN+iw8PYMmda6U1Aa8eTXvnEB4E+3FSw4zKQc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=En6tiQk6Hhr/I1nrf+JcGX51r7asLfuax30vFT/+aCGDEDLoovDud01olRyhvnd46/FDbZib46+9g7GJzJ6cPx/7wEgVDphchVS2JTANscKMGpWl/jnXrg8nbo6hu4YMcMchwrC3xUA55PIHB1lbtx5D65iWdB1W+lCsYQ6J/lk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=eNNhXFO7; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=bqmpl6ta; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="eNNhXFO7"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="bqmpl6ta" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1744201358; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5Z01DDvTLc3A+iis9JwNmMtr4ZIHUaMbDJfUxv/Jvm0=; b=eNNhXFO7I9Br6pKz4Ig4rEsFKezz784jo1ArzvByjdJNztVlc0ws8OJRSgpXncDI8+Y2zp c2OzDoSsfwp57lm4BOSmWYVx3NE1AbbI24CB7NYWMPk//7XepNUTYdGribN9L47xdhLZ90 CqSnNb4cx0GMYs9kZT4IbRidXuyuuQpkcpAlYqPGCKYrq9LCUVqr8ASw0o7MLDbxfaIRSR NRCv5FIcs5/uQHMyGuMrV6Hj4ij2MqFXFpLtAOWH7oOVvqC2ajx/4hypm3X+nn5vgLCbzL TmYEGNz1ftfcogxPUiyGup0fMljJDMtlHVg91tInWV7KCZWL8xz6VTOnQnpZjw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1744201358; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5Z01DDvTLc3A+iis9JwNmMtr4ZIHUaMbDJfUxv/Jvm0=; b=bqmpl6tae34wk5O+BskuD5hpCHSlhteuFyGonUbO3slvV7he5ugnVH2voV8JC/xNFkxUJl he4CC3UFfrbWFQBQ== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 1/2] x86/cacheinfo: Properly parse CPUID(0x80000005) L1d/L1i associativity Date: Wed, 9 Apr 2025 14:22:30 +0200 Message-ID: <20250409122233.1058601-2-darwi@linutronix.de> In-Reply-To: <20250409122233.1058601-1-darwi@linutronix.de> References: <20250409122233.1058601-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For the AMD CPUID(4) emulation cache info logic, the same associativity mapping array, assocs[], is used for both CPUID(0x80000005) and CPUID(0x80000006). This is incorrect since per the AMD manuals, the mappings for CPUID(0x80000005) L1d/L1i associativity is: n =3D 0x1 -> 0xfe n n =3D 0xff fully associative while assocs[] maps these values to: n =3D 0x1, 0x2, 0x4 n n =3D 0x3, 0x7, 0x9 0 n =3D 0x6 8 n =3D 0x8 16 n =3D 0xa 32 n =3D 0xb 48 n =3D 0xc 64 n =3D 0xd 96 n =3D 0xe 128 n =3D 0xf fully associative which is only valid for CPUID(0x80000006). Parse CPUID(0x80000005) L1d/L1i associativity values as shown in the AMD manuals. Since the 0xffff literal is used to denote full associativity at the AMD CPUID(4)-emulation logic, define AMD_CPUID4_FULLY_ASSOCIATIVE for it instead of spreading that literal in more places. Mark the assocs[] mapping array as only valid for CPUID(0x80000006) L2/L3 cache information. Fixes: a326e948c538 ("x86, cacheinfo: Fixup L3 cache information for AMD mu= lti-node processors") Cc: stable@vger.kernel.org Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index cd48d34ac04b..f4817cd50cfb 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -91,6 +91,8 @@ static const enum cache_type cache_type_map[] =3D { * AMD CPUs with TOPOEXT can just use CPUID(0x8000001d) */ =20 +#define AMD_CPUID4_FULLY_ASSOCIATIVE 0xffff + union l1_cache { struct { unsigned line_size :8; @@ -122,6 +124,7 @@ union l3_cache { unsigned int val; }; =20 +/* L2/L3 associativity mapping */ static const unsigned short assocs[] =3D { [1] =3D 1, [2] =3D 2, @@ -133,7 +136,7 @@ static const unsigned short assocs[] =3D { [0xc] =3D 64, [0xd] =3D 96, [0xe] =3D 128, - [0xf] =3D 0xffff /* Fully associative */ + [0xf] =3D AMD_CPUID4_FULLY_ASSOCIATIVE }; =20 static const unsigned char levels[] =3D { 1, 1, 2, 3 }; @@ -163,7 +166,7 @@ static void legacy_amd_cpuid4(int index, union _cpuid4_= leaf_eax *eax, if (!l1->val) return; =20 - assoc =3D assocs[l1->assoc]; + assoc =3D (l1->assoc =3D=3D 0xff) ? AMD_CPUID4_FULLY_ASSOCIATIVE : l1->= assoc; line_size =3D l1->line_size; lines_per_tag =3D l1->lines_per_tag; size_in_kb =3D l1->size_in_kb; @@ -201,7 +204,7 @@ static void legacy_amd_cpuid4(int index, union _cpuid4_= leaf_eax *eax, eax->split.num_threads_sharing =3D 0; eax->split.num_cores_on_die =3D topology_num_cores_per_package(); =20 - if (assoc =3D=3D 0xffff) + if (assoc =3D=3D AMD_CPUID4_FULLY_ASSOCIATIVE) eax->split.is_fully_associative =3D 1; =20 ebx->split.coherency_line_size =3D line_size - 1; --=20 2.49.0 From nobody Sat Feb 7 06:20:47 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AE9F26157E for ; Wed, 9 Apr 2025 12:22:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744201366; cv=none; b=SEv8zipxBX2XcZ3yT/++4IjaJWimK0C5b/O7aKXl8QgpwBhVONHFeC4dQ1hHuRvBQ0s6m94iOI5uGiUSKyyVFHGB7J66clbnt1yGF8NQOHTy4edg2HT+Eez7elIBPLuRu7a1dbtct/vLphKKZSecVNnZTjjynlwVF+0TPIWELIM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744201366; c=relaxed/simple; bh=ardz7KIirKoNESRrAcakMlL3X1UAbC/18FVFaR5RTRQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=be4ixIaDjdOvHb6x2CtpMwH3h1DHyi6TBk+4wEmcgoqJbSj/ll3YM5t04iJwfpa+IaPGvBDtPFg/cMOkVajAZoUeFwnm7H9Ab41ovERztipAHtj+51kI/XDWMgFJrVBB/C0kT+4GFmRHGAdKth2iXYpUVeyvLnQpVUZdRN+zqCE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=V9uLV+ob; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=OdmolsO7; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="V9uLV+ob"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="OdmolsO7" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1744201361; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WQsbjCvdNtCVEADB8V6oJZCRiRUpMBzibOwy8DYpBSU=; b=V9uLV+obTuCj+28NmEvfwWOyvyZ6zwcN+KQNuNA9x2yZqPtYFRii8t7SsZPLSnLVSDIkQV tPtJLaHLGW5H2CqTphhJVH8N5YoVCuGCEXqRNMeNzqkQ13fr3r5CX1WmT4Ac6ujaSBX4mT a/khfR8wbDy15+xH+b4J6pAu0MH7Z4xt+6lagzP3wBkK+1S8BenNrLAnseC86Tgtxf9E2e z8RBCEsbe8qx1XQzLn439zKlH/178393w9FPMznPZ/Y4g9z6cx1czRI1xCEAguL+pUA1cn thj1tq4abb/eq3cyTGabFHqaR3OiRJzMYufoJYTuLrdu1kLD97E6QgTPyr2hRg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1744201361; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=WQsbjCvdNtCVEADB8V6oJZCRiRUpMBzibOwy8DYpBSU=; b=OdmolsO7pYejkSKLi8S3Lt41J/ejjYCWCG/RKFuNthVeXH1p4K4k98bNyPTIBcUnYp4+lG Bpi3SMAiFJbijCBw== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 2/2] x86/cacheinfo: Properly parse CPUID(0x80000006) L2/L3 associativity Date: Wed, 9 Apr 2025 14:22:31 +0200 Message-ID: <20250409122233.1058601-3-darwi@linutronix.de> In-Reply-To: <20250409122233.1058601-1-darwi@linutronix.de> References: <20250409122233.1058601-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Complete the AMD CPUID(4) emulation logic, which uses CPUID(0x80000006) for L2/L3 cache info and an assocs[] associativity mapping array, by adding entries for 3-way caches and 6-way caches. Properly handle the case where CPUID(0x80000006) returns an L2/L3 associativity of 9. This is not real associativity, but a marker to indicate that the respective L2/L3 cache information should be retrieved from CPUID(0x8000001d) instead. If such a marker is encountered, return early from legacy_amd_cpuid4(), thus effectively emulating an "invalid index" CPUID(4) response with a cache type of zero. When checking if CPUID(0x80000006) L2/L3 cache info output is valid, and given the associtivity marker 9 above, do not just check if the whole ECX/EDX register is zero. Rather, check if the associativity is zero or 9. An associativity of zero implies no L2/L3 cache, which make it the more correct check anyway vs. a zero check of the whole output register. Fixes: a326e948c538 ("x86, cacheinfo: Fixup L3 cache information for AMD mu= lti-node processors") Cc: stable@vger.kernel.org Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index f4817cd50cfb..52727f8c0006 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -89,9 +89,13 @@ static const enum cache_type cache_type_map[] =3D { /* * Fallback AMD CPUID(4) emulation * AMD CPUs with TOPOEXT can just use CPUID(0x8000001d) + * + * @AMD_L2_L3_INVALID_ASSOC: cache info for the respective L2/L3 cache sho= uld + * be determined from CPUID(0x8000001d) instead of CPUID(0x80000006). */ =20 #define AMD_CPUID4_FULLY_ASSOCIATIVE 0xffff +#define AMD_L2_L3_INVALID_ASSOC 0x9 =20 union l1_cache { struct { @@ -128,7 +132,9 @@ union l3_cache { static const unsigned short assocs[] =3D { [1] =3D 1, [2] =3D 2, + [3] =3D 3, [4] =3D 4, + [5] =3D 6, [6] =3D 8, [8] =3D 16, [0xa] =3D 32, @@ -172,7 +178,7 @@ static void legacy_amd_cpuid4(int index, union _cpuid4_= leaf_eax *eax, size_in_kb =3D l1->size_in_kb; break; case 2: - if (!l2.val) + if (!l2.assoc || l2.assoc =3D=3D AMD_L2_L3_INVALID_ASSOC) return; =20 /* Use x86_cache_size as it might have K7 errata fixes */ @@ -182,7 +188,7 @@ static void legacy_amd_cpuid4(int index, union _cpuid4_= leaf_eax *eax, size_in_kb =3D __this_cpu_read(cpu_info.x86_cache_size); break; case 3: - if (!l3.val) + if (!l3.assoc || l3.assoc =3D=3D AMD_L2_L3_INVALID_ASSOC) return; =20 assoc =3D assocs[l3.assoc]; --=20 2.49.0