From nobody Sun Feb 8 22:08:34 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6236625DCE0 for ; Wed, 9 Apr 2025 10:54:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744196082; cv=none; b=cvmrKGxF0tghdhkSRVhamnrlW4/efA4Ow884IYpCkeqex26PmQdRA8Gyj7gfeApv6t6kpN9ByBMKKq0mKE4Ql42q9egrFLoJyjXHZ/upE5nmbhssuepRiBkYous0NpLJEd1elttQ4g1p5NBPD0/Ts32O6qCazwFEk2yvEatpDss= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744196082; c=relaxed/simple; bh=WE+fR5R5Le2F26iYDkYuRg3MPTRSQ5mwY9M7TxWrkFA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=m9HH+KghSL9eMAVNpf4J8d75P7EvVGDaji3xof+T5lieM3DPhq+qF+5HVPQNVUhFtEdYl2VJwpK6u8dDtJzvtfrgncMhPQxEaX3fqXMfGsJ4mem66GCBEXHpwoOaQxMHlQPjjNYE6OxUMWuGmFeCT84NmxWmI5g44m7mflLfGTU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=s3CHB2NB; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=XWyD4lLR; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="s3CHB2NB"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="XWyD4lLR" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1744196079; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XvJ+dWA6n4Y9zbDSWY3pwiECtlWOSXm6zw8uMdiQHXw=; b=s3CHB2NB/qNITMhs6Z62BubXqDLM/AGqImnPEBsJtPFSmy9aR/oQYnBRo4UxW1gy7a5CFd T8HPLxqJG0a0KprySNdUUdIwI2F2lB8Qn6Arzkp0SSehWUIqfPmWXdE5hpn1fFWOaFcGkK 7LNe6Ssas5IWMTNJewjmrzV7hOOJsyG/uNGOrai7TaHlb2FA9THl0USQh3KgljYz5kYK07 G/4B9WU0aD4u3mu0xaQ8g4uOMnPafzcWFmiR8Mb46iGcajDY3cTdW7bC1zXHaWOJvFkHdk dFxg4M5X2cX7l9AIC3Xyn1nsQhyDyc8n0Nv3dMLNV6uN0fZ40PGabW0HiWRX0Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1744196079; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XvJ+dWA6n4Y9zbDSWY3pwiECtlWOSXm6zw8uMdiQHXw=; b=XWyD4lLRS6fJOg4OqWntbuC/rIE+ovupR4y5DgcN1smAbLX0rifow4pxT650S9IJ7oV7iw +sRd8H66vR0unmBA== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 1/2] x86/cacheinfo: Properly parse CPUID(0x80000005) L1d/L1i associativity Date: Wed, 9 Apr 2025 12:54:24 +0200 Message-ID: <20250409105429.1048199-2-darwi@linutronix.de> In-Reply-To: <20250409105429.1048199-1-darwi@linutronix.de> References: <20250409105429.1048199-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For the AMD CPUID(4) emulation cache info logic, the same associativity mapping array, assocs[], is used for both CPUID(0x80000005) and CPUID(0x80000006). This is incorrect since per the AMD manuals, the mappings for CPUID(0x80000005) L1d/L1i associativity is: n =3D 0x1 -> 0xfe n n =3D 0xff fully associative while assocs[] maps these values to: n =3D 0x1, 0x2, 0x4 n n =3D 0x3, 0x7, 0x9 0 n =3D 0x6 8 n =3D 0x8 16 n =3D 0xa 32 n =3D 0xb 48 n =3D 0xc 64 n =3D 0xd 96 n =3D 0xe 128 n =3D 0xf fully associative which is only valid for CPUID(0x80000006). Parse CPUID(0x80000005) L1d/L1i associativity values as shown in the AMD manuals. Since the 0xffff literal is used to denote full associativity at the AMD CPUID(4)-emulation logic, define AMD_CPUID4_FULLY_ASSOCIATIVE for it instead of spreading that literal in more places. Mark the assocs[] mapping array as only valid for CPUID(0x80000006) L2/L3 cache information. Fixes: a326e948c538 ("x86, cacheinfo: Fixup L3 cache information for AMD mu= lti-node processors") Cc: stable@vger.kernel.org Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index b3a520959b51..7a95e1ce73f8 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -208,6 +208,9 @@ union l3_cache { unsigned val; }; =20 +#define AMD_CPUID4_FULLY_ASSOCIATIVE 0xffff + +/* L2/L3 associativity mapping */ static const unsigned short assocs[] =3D { [1] =3D 1, [2] =3D 2, @@ -219,7 +222,7 @@ static const unsigned short assocs[] =3D { [0xc] =3D 64, [0xd] =3D 96, [0xe] =3D 128, - [0xf] =3D 0xffff /* fully associative - no way to show this currently */ + [0xf] =3D AMD_CPUID4_FULLY_ASSOCIATIVE }; =20 static const unsigned char levels[] =3D { 1, 1, 2, 3 }; @@ -258,7 +261,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax, case 0: if (!l1->val) return; - assoc =3D assocs[l1->assoc]; + assoc =3D (l1->assoc =3D=3D 0xff) ? AMD_CPUID4_FULLY_ASSOCIATIVE : l1->a= ssoc; line_size =3D l1->line_size; lines_per_tag =3D l1->lines_per_tag; size_in_kb =3D l1->size_in_kb; @@ -295,7 +298,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax, eax->split.num_cores_on_die =3D topology_num_cores_per_package(); =20 =20 - if (assoc =3D=3D 0xffff) + if (assoc =3D=3D AMD_CPUID4_FULLY_ASSOCIATIVE) eax->split.is_fully_associative =3D 1; ebx->split.coherency_line_size =3D line_size - 1; ebx->split.ways_of_associativity =3D assoc - 1; --=20 2.49.0 From nobody Sun Feb 8 22:08:34 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73B9025E44C for ; Wed, 9 Apr 2025 10:54:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744196087; cv=none; b=qp+6RGEwy+OJTjIGkZCucjgZnfvxdqSnZDupSH8kUm+9L6HeUX337IQLAPeNKOLLo9qByrNK28TzDME+2X7fhxZ+8OYZ/lB+TFcgxDStmZ+i27U3/86kyZQVpoE8sCrxju6Qm36MCtiRWIsb2bXBXKTK7EZE+6J9cDq0pnhMxMI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744196087; c=relaxed/simple; bh=pHflYcKqFoKG8cLoQ/9fnD6NmQ/Wt4RsX+dpA1DRZdg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hxXmHZcUi3KLPRqFXOFFdGhJ5tMyV3nfEmFbIWRw9n8RR5exoiBMKGPRDyEhXZIQPJMV+zTeZuLtGV1b+bV+FHftds/K6b7GGW21om0i3kE2usPIi/AZarjzLDtkqalSZRYN073d3Z1oRri3cA8DcSZTyKo38OeyZTxU1He82uM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=cMZI7iKf; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=vd8kpkLt; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="cMZI7iKf"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="vd8kpkLt" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1744196082; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gsys2pZg1b9LKpYoW/QXl009adwTq+tVztT5ium1pgk=; b=cMZI7iKfSi3CmZHK88pNQOQmqk+hFZVyMLbt8/mbgWCbz50PwljRUVt85euhWplp/g8ArV vU9AA07s0kzIprA5txZLyWYL5iPkF3rjB9nqXVbxLgDv/oGgho94rR0QJUMJxKzFqKayvJ UfRvVYq3vyuAtvIOvKWqHDtD4lJF1ALqZ46hiPG9O1JjMZcpxsmm8Fb1in2EL3QxMH1oDF hvNkJqDibZWwI78N0Vn+jPkymIPxOrHaWfgaWyQUuKufgWp+MmjW78PmHEyatpaf9ncmsD iQwmSAiHwZ2BJsacJP6+Y2xkVK0QtWGd51dOmEq4390ioTPuV4NXTzRXhCh4PA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1744196082; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gsys2pZg1b9LKpYoW/QXl009adwTq+tVztT5ium1pgk=; b=vd8kpkLtAItLxWmAEHdHdLt6FGOJhk1u5EzHQwzv9on66iKYvsZPmkJdQFE1p824Wyf5VH O/KwZ8/4OuisIeAQ== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 2/2] x86/cacheinfo: Properly parse CPUID(0x80000006) L2/L3 associativity Date: Wed, 9 Apr 2025 12:54:25 +0200 Message-ID: <20250409105429.1048199-3-darwi@linutronix.de> In-Reply-To: <20250409105429.1048199-1-darwi@linutronix.de> References: <20250409105429.1048199-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Complete the AMD CPUID(4) emulation logic, which uses CPUID(0x80000006) for L2/L3 cache info and an assocs[] associativity mapping array, by adding entries for 3-way caches and 6-way caches. Properly handle the case where CPUID(0x80000006) returns an L2/L3 associativity of 9. This is not real associativity, but a marker to indicate that the respective L2/L3 cache information should be retrieved from CPUID(0x8000001d) instead. If such a marker is encountered, return early from legacy_amd_cpuid4(), thus effectively emulating an "invalid index" CPUID(4) response with a cache type of zero. When checking if CPUID(0x80000006) L2/L3 cache info output is valid, and given the associtivity marker 9 above, do not just check if the whole ECX/EDX register is zero. Rather, check if the associativity is zero or 9. An associativity of zero implies no L2/L3 cache, which make it the more correct check anyway vs. a zero check of the whole output register. Fixes: a326e948c538 ("x86, cacheinfo: Fixup L3 cache information for AMD mu= lti-node processors") Cc: stable@vger.kernel.org Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 7a95e1ce73f8..038f819da20e 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -208,13 +208,20 @@ union l3_cache { unsigned val; }; =20 +/* + * AMD_L2_L3_INVALID_ASSOC: Cache info for the respective L2/L3 cache shou= ld + * be determined from CPUID(0x8000001d) instead of CPUID(0x80000006). + */ #define AMD_CPUID4_FULLY_ASSOCIATIVE 0xffff +#define AMD_L2_L3_INVALID_ASSOC 0x9 =20 /* L2/L3 associativity mapping */ static const unsigned short assocs[] =3D { [1] =3D 1, [2] =3D 2, + [3] =3D 3, [4] =3D 4, + [5] =3D 6, [6] =3D 8, [8] =3D 16, [0xa] =3D 32, @@ -267,7 +274,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax, size_in_kb =3D l1->size_in_kb; break; case 2: - if (!l2.val) + if (!l2.assoc || l2.assoc =3D=3D AMD_L2_L3_INVALID_ASSOC) return; assoc =3D assocs[l2.assoc]; line_size =3D l2.line_size; @@ -276,7 +283,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax, size_in_kb =3D __this_cpu_read(cpu_info.x86_cache_size); break; case 3: - if (!l3.val) + if (!l3.assoc || l3.assoc =3D=3D AMD_L2_L3_INVALID_ASSOC) return; assoc =3D assocs[l3.assoc]; line_size =3D l3.line_size; --=20 2.49.0