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From: =?utf-8?q?Andr=C3=A9_Draszik?= <andre.draszik@linaro.org>
Date: Wed, 09 Apr 2025 21:37:43 +0100
Subject: [PATCH v4 22/32] mfd: sec-irq: Convert to using REGMAP_IRQ_REG()
macros
Precedence: bulk
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Message-Id: <20250409-s2mpg10-v4-22-d66d5f39b6bf@linaro.org>
References: <20250409-s2mpg10-v4-0-d66d5f39b6bf@linaro.org>
In-Reply-To: <20250409-s2mpg10-v4-0-d66d5f39b6bf@linaro.org>
To: Krzysztof Kozlowski <krzk@kernel.org>, Lee Jones <lee@kernel.org>,
Rob Herring <robh@kernel.org>, Conor Dooley <conor+dt@kernel.org>,
Sylwester Nawrocki <s.nawrocki@samsung.com>,
Chanwoo Choi <cw00.choi@samsung.com>, Alim Akhtar <alim.akhtar@samsung.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Russell King <linux@armlinux.org.uk>,
Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>,
Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Peter Griffin <peter.griffin@linaro.org>,
Tudor Ambarus <tudor.ambarus@linaro.org>,
Will McVicker <willmcvicker@google.com>, kernel-team@android.com,
linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-rtc@vger.kernel.org,
=?utf-8?q?Andr=C3=A9_Draszik?= <andre.draszik@linaro.org>
X-Mailer: b4 0.14.2
Use REGMAP_IRQ_REG macro helpers instead of open coding. This makes the
code a bit shorter and more obvious.
Signed-off-by: Andr=C3=A9 Draszik <andre.draszik@linaro.org>
---
drivers/mfd/sec-irq.c | 343 +++++++++++-----------------------------------=
----
1 file changed, 75 insertions(+), 268 deletions(-)
diff --git a/drivers/mfd/sec-irq.c b/drivers/mfd/sec-irq.c
index 4a6585a6acdb71d2fb368ddf38463f001e513c7c..c5c80b1ba104e6c5a55b442d2f1=
0a8554201a961 100644
--- a/drivers/mfd/sec-irq.c
+++ b/drivers/mfd/sec-irq.c
@@ -74,212 +74,68 @@ static const struct regmap_irq s2mpg10_irqs[] =3D {
};
=20
static const struct regmap_irq s2mps11_irqs[] =3D {
- [S2MPS11_IRQ_PWRONF] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_PWRONF_MASK,
- },
- [S2MPS11_IRQ_PWRONR] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_PWRONR_MASK,
- },
- [S2MPS11_IRQ_JIGONBF] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_JIGONBF_MASK,
- },
- [S2MPS11_IRQ_JIGONBR] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_JIGONBR_MASK,
- },
- [S2MPS11_IRQ_ACOKBF] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_ACOKBF_MASK,
- },
- [S2MPS11_IRQ_ACOKBR] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_ACOKBR_MASK,
- },
- [S2MPS11_IRQ_PWRON1S] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_PWRON1S_MASK,
- },
- [S2MPS11_IRQ_MRB] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_MRB_MASK,
- },
- [S2MPS11_IRQ_RTC60S] =3D {
- .reg_offset =3D 1,
- .mask =3D S2MPS11_IRQ_RTC60S_MASK,
- },
- [S2MPS11_IRQ_RTCA1] =3D {
- .reg_offset =3D 1,
- .mask =3D S2MPS11_IRQ_RTCA1_MASK,
- },
- [S2MPS11_IRQ_RTCA0] =3D {
- .reg_offset =3D 1,
- .mask =3D S2MPS11_IRQ_RTCA0_MASK,
- },
- [S2MPS11_IRQ_SMPL] =3D {
- .reg_offset =3D 1,
- .mask =3D S2MPS11_IRQ_SMPL_MASK,
- },
- [S2MPS11_IRQ_RTC1S] =3D {
- .reg_offset =3D 1,
- .mask =3D S2MPS11_IRQ_RTC1S_MASK,
- },
- [S2MPS11_IRQ_WTSR] =3D {
- .reg_offset =3D 1,
- .mask =3D S2MPS11_IRQ_WTSR_MASK,
- },
- [S2MPS11_IRQ_INT120C] =3D {
- .reg_offset =3D 2,
- .mask =3D S2MPS11_IRQ_INT120C_MASK,
- },
- [S2MPS11_IRQ_INT140C] =3D {
- .reg_offset =3D 2,
- .mask =3D S2MPS11_IRQ_INT140C_MASK,
- },
+ REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK),
+ REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK),
+ REGMAP_IRQ_REG(S2MPS11_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK),
+ REGMAP_IRQ_REG(S2MPS11_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK),
+ REGMAP_IRQ_REG(S2MPS11_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK),
+ REGMAP_IRQ_REG(S2MPS11_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK),
+ REGMAP_IRQ_REG(S2MPS11_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK),
+ REGMAP_IRQ_REG(S2MPS11_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK),
+
+ REGMAP_IRQ_REG(S2MPS11_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK),
+ REGMAP_IRQ_REG(S2MPS11_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK),
+ REGMAP_IRQ_REG(S2MPS11_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK),
+ REGMAP_IRQ_REG(S2MPS11_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK),
+ REGMAP_IRQ_REG(S2MPS11_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK),
+ REGMAP_IRQ_REG(S2MPS11_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK),
+
+ REGMAP_IRQ_REG(S2MPS11_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK),
+ REGMAP_IRQ_REG(S2MPS11_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK),
};
=20
static const struct regmap_irq s2mps14_irqs[] =3D {
- [S2MPS14_IRQ_PWRONF] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_PWRONF_MASK,
- },
- [S2MPS14_IRQ_PWRONR] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_PWRONR_MASK,
- },
- [S2MPS14_IRQ_JIGONBF] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_JIGONBF_MASK,
- },
- [S2MPS14_IRQ_JIGONBR] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_JIGONBR_MASK,
- },
- [S2MPS14_IRQ_ACOKBF] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_ACOKBF_MASK,
- },
- [S2MPS14_IRQ_ACOKBR] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_ACOKBR_MASK,
- },
- [S2MPS14_IRQ_PWRON1S] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_PWRON1S_MASK,
- },
- [S2MPS14_IRQ_MRB] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_MRB_MASK,
- },
- [S2MPS14_IRQ_RTC60S] =3D {
- .reg_offset =3D 1,
- .mask =3D S2MPS11_IRQ_RTC60S_MASK,
- },
- [S2MPS14_IRQ_RTCA1] =3D {
- .reg_offset =3D 1,
- .mask =3D S2MPS11_IRQ_RTCA1_MASK,
- },
- [S2MPS14_IRQ_RTCA0] =3D {
- .reg_offset =3D 1,
- .mask =3D S2MPS11_IRQ_RTCA0_MASK,
- },
- [S2MPS14_IRQ_SMPL] =3D {
- .reg_offset =3D 1,
- .mask =3D S2MPS11_IRQ_SMPL_MASK,
- },
- [S2MPS14_IRQ_RTC1S] =3D {
- .reg_offset =3D 1,
- .mask =3D S2MPS11_IRQ_RTC1S_MASK,
- },
- [S2MPS14_IRQ_WTSR] =3D {
- .reg_offset =3D 1,
- .mask =3D S2MPS11_IRQ_WTSR_MASK,
- },
- [S2MPS14_IRQ_INT120C] =3D {
- .reg_offset =3D 2,
- .mask =3D S2MPS11_IRQ_INT120C_MASK,
- },
- [S2MPS14_IRQ_INT140C] =3D {
- .reg_offset =3D 2,
- .mask =3D S2MPS11_IRQ_INT140C_MASK,
- },
- [S2MPS14_IRQ_TSD] =3D {
- .reg_offset =3D 2,
- .mask =3D S2MPS14_IRQ_TSD_MASK,
- },
+ REGMAP_IRQ_REG(S2MPS14_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK),
+ REGMAP_IRQ_REG(S2MPS14_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK),
+ REGMAP_IRQ_REG(S2MPS14_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK),
+ REGMAP_IRQ_REG(S2MPS14_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK),
+ REGMAP_IRQ_REG(S2MPS14_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK),
+ REGMAP_IRQ_REG(S2MPS14_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK),
+ REGMAP_IRQ_REG(S2MPS14_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK),
+ REGMAP_IRQ_REG(S2MPS14_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK),
+
+ REGMAP_IRQ_REG(S2MPS14_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK),
+ REGMAP_IRQ_REG(S2MPS14_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK),
+ REGMAP_IRQ_REG(S2MPS14_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK),
+ REGMAP_IRQ_REG(S2MPS14_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK),
+ REGMAP_IRQ_REG(S2MPS14_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK),
+ REGMAP_IRQ_REG(S2MPS14_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK),
+
+ REGMAP_IRQ_REG(S2MPS14_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK),
+ REGMAP_IRQ_REG(S2MPS14_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK),
+ REGMAP_IRQ_REG(S2MPS14_IRQ_TSD, 2, S2MPS14_IRQ_TSD_MASK),
};
=20
static const struct regmap_irq s2mpu02_irqs[] =3D {
- [S2MPU02_IRQ_PWRONF] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_PWRONF_MASK,
- },
- [S2MPU02_IRQ_PWRONR] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_PWRONR_MASK,
- },
- [S2MPU02_IRQ_JIGONBF] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_JIGONBF_MASK,
- },
- [S2MPU02_IRQ_JIGONBR] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_JIGONBR_MASK,
- },
- [S2MPU02_IRQ_ACOKBF] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_ACOKBF_MASK,
- },
- [S2MPU02_IRQ_ACOKBR] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_ACOKBR_MASK,
- },
- [S2MPU02_IRQ_PWRON1S] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_PWRON1S_MASK,
- },
- [S2MPU02_IRQ_MRB] =3D {
- .reg_offset =3D 0,
- .mask =3D S2MPS11_IRQ_MRB_MASK,
- },
- [S2MPU02_IRQ_RTC60S] =3D {
- .reg_offset =3D 1,
- .mask =3D S2MPS11_IRQ_RTC60S_MASK,
- },
- [S2MPU02_IRQ_RTCA1] =3D {
- .reg_offset =3D 1,
- .mask =3D S2MPS11_IRQ_RTCA1_MASK,
- },
- [S2MPU02_IRQ_RTCA0] =3D {
- .reg_offset =3D 1,
- .mask =3D S2MPS11_IRQ_RTCA0_MASK,
- },
- [S2MPU02_IRQ_SMPL] =3D {
- .reg_offset =3D 1,
- .mask =3D S2MPS11_IRQ_SMPL_MASK,
- },
- [S2MPU02_IRQ_RTC1S] =3D {
- .reg_offset =3D 1,
- .mask =3D S2MPS11_IRQ_RTC1S_MASK,
- },
- [S2MPU02_IRQ_WTSR] =3D {
- .reg_offset =3D 1,
- .mask =3D S2MPS11_IRQ_WTSR_MASK,
- },
- [S2MPU02_IRQ_INT120C] =3D {
- .reg_offset =3D 2,
- .mask =3D S2MPS11_IRQ_INT120C_MASK,
- },
- [S2MPU02_IRQ_INT140C] =3D {
- .reg_offset =3D 2,
- .mask =3D S2MPS11_IRQ_INT140C_MASK,
- },
- [S2MPU02_IRQ_TSD] =3D {
- .reg_offset =3D 2,
- .mask =3D S2MPS14_IRQ_TSD_MASK,
- },
+ REGMAP_IRQ_REG(S2MPU02_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK),
+ REGMAP_IRQ_REG(S2MPU02_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK),
+ REGMAP_IRQ_REG(S2MPU02_IRQ_JIGONBF, 0, S2MPS11_IRQ_JIGONBF_MASK),
+ REGMAP_IRQ_REG(S2MPU02_IRQ_JIGONBR, 0, S2MPS11_IRQ_JIGONBR_MASK),
+ REGMAP_IRQ_REG(S2MPU02_IRQ_ACOKBF, 0, S2MPS11_IRQ_ACOKBF_MASK),
+ REGMAP_IRQ_REG(S2MPU02_IRQ_ACOKBR, 0, S2MPS11_IRQ_ACOKBR_MASK),
+ REGMAP_IRQ_REG(S2MPU02_IRQ_PWRON1S, 0, S2MPS11_IRQ_PWRON1S_MASK),
+ REGMAP_IRQ_REG(S2MPU02_IRQ_MRB, 0, S2MPS11_IRQ_MRB_MASK),
+
+ REGMAP_IRQ_REG(S2MPU02_IRQ_RTC60S, 1, S2MPS11_IRQ_RTC60S_MASK),
+ REGMAP_IRQ_REG(S2MPU02_IRQ_RTCA1, 1, S2MPS11_IRQ_RTCA1_MASK),
+ REGMAP_IRQ_REG(S2MPU02_IRQ_RTCA0, 1, S2MPS11_IRQ_RTCA0_MASK),
+ REGMAP_IRQ_REG(S2MPU02_IRQ_SMPL, 1, S2MPS11_IRQ_SMPL_MASK),
+ REGMAP_IRQ_REG(S2MPU02_IRQ_RTC1S, 1, S2MPS11_IRQ_RTC1S_MASK),
+ REGMAP_IRQ_REG(S2MPU02_IRQ_WTSR, 1, S2MPS11_IRQ_WTSR_MASK),
+
+ REGMAP_IRQ_REG(S2MPU02_IRQ_INT120C, 2, S2MPS11_IRQ_INT120C_MASK),
+ REGMAP_IRQ_REG(S2MPU02_IRQ_INT140C, 2, S2MPS11_IRQ_INT140C_MASK),
+ REGMAP_IRQ_REG(S2MPU02_IRQ_TSD, 2, S2MPS14_IRQ_TSD_MASK),
};
=20
static const struct regmap_irq s2mpu05_irqs[] =3D {
@@ -303,74 +159,25 @@ static const struct regmap_irq s2mpu05_irqs[] =3D {
};
=20
static const struct regmap_irq s5m8767_irqs[] =3D {
- [S5M8767_IRQ_PWRR] =3D {
- .reg_offset =3D 0,
- .mask =3D S5M8767_IRQ_PWRR_MASK,
- },
- [S5M8767_IRQ_PWRF] =3D {
- .reg_offset =3D 0,
- .mask =3D S5M8767_IRQ_PWRF_MASK,
- },
- [S5M8767_IRQ_PWR1S] =3D {
- .reg_offset =3D 0,
- .mask =3D S5M8767_IRQ_PWR1S_MASK,
- },
- [S5M8767_IRQ_JIGR] =3D {
- .reg_offset =3D 0,
- .mask =3D S5M8767_IRQ_JIGR_MASK,
- },
- [S5M8767_IRQ_JIGF] =3D {
- .reg_offset =3D 0,
- .mask =3D S5M8767_IRQ_JIGF_MASK,
- },
- [S5M8767_IRQ_LOWBAT2] =3D {
- .reg_offset =3D 0,
- .mask =3D S5M8767_IRQ_LOWBAT2_MASK,
- },
- [S5M8767_IRQ_LOWBAT1] =3D {
- .reg_offset =3D 0,
- .mask =3D S5M8767_IRQ_LOWBAT1_MASK,
- },
- [S5M8767_IRQ_MRB] =3D {
- .reg_offset =3D 1,
- .mask =3D S5M8767_IRQ_MRB_MASK,
- },
- [S5M8767_IRQ_DVSOK2] =3D {
- .reg_offset =3D 1,
- .mask =3D S5M8767_IRQ_DVSOK2_MASK,
- },
- [S5M8767_IRQ_DVSOK3] =3D {
- .reg_offset =3D 1,
- .mask =3D S5M8767_IRQ_DVSOK3_MASK,
- },
- [S5M8767_IRQ_DVSOK4] =3D {
- .reg_offset =3D 1,
- .mask =3D S5M8767_IRQ_DVSOK4_MASK,
- },
- [S5M8767_IRQ_RTC60S] =3D {
- .reg_offset =3D 2,
- .mask =3D S5M8767_IRQ_RTC60S_MASK,
- },
- [S5M8767_IRQ_RTCA1] =3D {
- .reg_offset =3D 2,
- .mask =3D S5M8767_IRQ_RTCA1_MASK,
- },
- [S5M8767_IRQ_RTCA2] =3D {
- .reg_offset =3D 2,
- .mask =3D S5M8767_IRQ_RTCA2_MASK,
- },
- [S5M8767_IRQ_SMPL] =3D {
- .reg_offset =3D 2,
- .mask =3D S5M8767_IRQ_SMPL_MASK,
- },
- [S5M8767_IRQ_RTC1S] =3D {
- .reg_offset =3D 2,
- .mask =3D S5M8767_IRQ_RTC1S_MASK,
- },
- [S5M8767_IRQ_WTSR] =3D {
- .reg_offset =3D 2,
- .mask =3D S5M8767_IRQ_WTSR_MASK,
- },
+ REGMAP_IRQ_REG(S5M8767_IRQ_PWRR, 0, S5M8767_IRQ_PWRR_MASK),
+ REGMAP_IRQ_REG(S5M8767_IRQ_PWRF, 0, S5M8767_IRQ_PWRF_MASK),
+ REGMAP_IRQ_REG(S5M8767_IRQ_PWR1S, 0, S5M8767_IRQ_PWR1S_MASK),
+ REGMAP_IRQ_REG(S5M8767_IRQ_JIGR, 0, S5M8767_IRQ_JIGR_MASK),
+ REGMAP_IRQ_REG(S5M8767_IRQ_JIGF, 0, S5M8767_IRQ_JIGF_MASK),
+ REGMAP_IRQ_REG(S5M8767_IRQ_LOWBAT2, 0, S5M8767_IRQ_LOWBAT2_MASK),
+ REGMAP_IRQ_REG(S5M8767_IRQ_LOWBAT1, 0, S5M8767_IRQ_LOWBAT1_MASK),
+
+ REGMAP_IRQ_REG(S5M8767_IRQ_MRB, 1, S5M8767_IRQ_MRB_MASK),
+ REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK2, 1, S5M8767_IRQ_DVSOK2_MASK),
+ REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK3, 1, S5M8767_IRQ_DVSOK3_MASK),
+ REGMAP_IRQ_REG(S5M8767_IRQ_DVSOK4, 1, S5M8767_IRQ_DVSOK4_MASK),
+
+ REGMAP_IRQ_REG(S5M8767_IRQ_RTC60S, 2, S5M8767_IRQ_RTC60S_MASK),
+ REGMAP_IRQ_REG(S5M8767_IRQ_RTCA1, 2, S5M8767_IRQ_RTCA1_MASK),
+ REGMAP_IRQ_REG(S5M8767_IRQ_RTCA2, 2, S5M8767_IRQ_RTCA2_MASK),
+ REGMAP_IRQ_REG(S5M8767_IRQ_SMPL, 2, S5M8767_IRQ_SMPL_MASK),
+ REGMAP_IRQ_REG(S5M8767_IRQ_RTC1S, 2, S5M8767_IRQ_RTC1S_MASK),
+ REGMAP_IRQ_REG(S5M8767_IRQ_WTSR, 2, S5M8767_IRQ_WTSR_MASK),
};
=20
/* All S2MPG10 interrupt sources are read-only and don't require clearing =
*/
--=20
2.49.0.604.gff1f9ca942-goog