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Wed, 09 Apr 2025 01:40:47 -0700 (PDT) From: Bartosz Golaszewski Date: Wed, 09 Apr 2025 10:40:40 +0200 Subject: [PATCH v2 2/7] iio: dac: ad5592r: use lock guards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250409-gpiochip-set-rv-iio-v2-2-4b36428f39cb@linaro.org> References: <20250409-gpiochip-set-rv-iio-v2-0-4b36428f39cb@linaro.org> In-Reply-To: <20250409-gpiochip-set-rv-iio-v2-0-4b36428f39cb@linaro.org> To: Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Linus Walleij , Bartosz Golaszewski , Cosmin Tanislav Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Bartosz Golaszewski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=8820; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=1vAOkph4RSRlxXIL03fJybHqa8k7PtHiCUYi8heCqHc=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBn9jKLZVn1FOhgbMDtXZw827Abtxy1D8yn3IvuO sMRKUkuydSJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCZ/YyiwAKCRARpy6gFHHX coN8D/4vxRXZ3tWjiGyIv72luaGwtMnEOJvgFSIKHF9Uya0djXcv1SJB7TgJhyZQkiuBahr6rGY oWhY+BrHin5LBrySTVdTJNDoL7cYfJeJT9l/aUJS4EMY7kjdq22nVlWBNeP2NoSZFFvFjSeEtQW ly3bHKE2RtgSxAn5zFWXk2iygQqLYSG7Ex2KwdiuUj5MtCaM44sQtKo7EnCYSnYH0bW7Itysi/j KtEfkcJ5RGXn21BkPo8tzeOcgiKYL6J/wTnk5ZPc9UDoaOsanHqjm2BZhTRFb6VdgyUB3s6kfGh NUyMybUXsGsWkOWHskotR6zReUolFzyqRChaAQTwNeXw3oDKEmgMPqyeT8ceoy83rOzGqRQUwtC t+AO5smaE7Aq5gT5P3IGmK0b9jtBzCe+bI6rI/9divtj3cVkx/o/DXCwCrhmi34v3x2BR7fF3m7 Q5GnyrgQTh/KXPztG5Ts+jBSPxsPKQWZC7BDtPTjFEg+A1NOWasTOQxSwPGSbLs8jR7lzaB4i87 TLl+7QKg0NewGGD7B9jT6CfPhQvxL9okCEwKlQfLfIfNuSHVZ672/CHqQNltRffRx+65PYg1Mul 8FAFJAIgSv/ZhseCRm01CVi1596ks7fGon9FSALH1NDkMT3Als7bTY2xWFxoX1JXPfr4cMYZb51 QOkAE+PwcJYJtiQ== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Use lock guards from linux/cleanup.h to simplify the code and remove some labels. Note that we need to initialize some variables even though it's not technically required as scoped_guards() are implemented as for loops. Signed-off-by: Bartosz Golaszewski --- drivers/iio/dac/ad5592r-base.c | 132 +++++++++++++++++--------------------= ---- 1 file changed, 54 insertions(+), 78 deletions(-) diff --git a/drivers/iio/dac/ad5592r-base.c b/drivers/iio/dac/ad5592r-base.c index eb85907f61ae..ada60f5ff1b6 100644 --- a/drivers/iio/dac/ad5592r-base.c +++ b/drivers/iio/dac/ad5592r-base.c @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -24,16 +25,14 @@ static int ad5592r_gpio_get(struct gpio_chip *chip, uns= igned offset) { struct ad5592r_state *st =3D gpiochip_get_data(chip); int ret =3D 0; - u8 val; + u8 val =3D 0; =20 - mutex_lock(&st->gpio_lock); - - if (st->gpio_out & BIT(offset)) - val =3D st->gpio_val; - else - ret =3D st->ops->gpio_read(st, &val); - - mutex_unlock(&st->gpio_lock); + scoped_guard(mutex, &st->gpio_lock) { + if (st->gpio_out & BIT(offset)) + val =3D st->gpio_val; + else + ret =3D st->ops->gpio_read(st, &val); + } =20 if (ret < 0) return ret; @@ -45,7 +44,7 @@ static void ad5592r_gpio_set(struct gpio_chip *chip, unsi= gned offset, int value) { struct ad5592r_state *st =3D gpiochip_get_data(chip); =20 - mutex_lock(&st->gpio_lock); + guard(mutex)(&st->gpio_lock); =20 if (value) st->gpio_val |=3D BIT(offset); @@ -53,8 +52,6 @@ static void ad5592r_gpio_set(struct gpio_chip *chip, unsi= gned offset, int value) st->gpio_val &=3D ~BIT(offset); =20 st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); - - mutex_unlock(&st->gpio_lock); } =20 static int ad5592r_gpio_direction_input(struct gpio_chip *chip, unsigned o= ffset) @@ -62,21 +59,16 @@ static int ad5592r_gpio_direction_input(struct gpio_chi= p *chip, unsigned offset) struct ad5592r_state *st =3D gpiochip_get_data(chip); int ret; =20 - mutex_lock(&st->gpio_lock); + guard(mutex)(&st->gpio_lock); =20 st->gpio_out &=3D ~BIT(offset); st->gpio_in |=3D BIT(offset); =20 ret =3D st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); if (ret < 0) - goto err_unlock; + return ret; =20 - ret =3D st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); - -err_unlock: - mutex_unlock(&st->gpio_lock); - - return ret; + return st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); } =20 static int ad5592r_gpio_direction_output(struct gpio_chip *chip, @@ -85,7 +77,7 @@ static int ad5592r_gpio_direction_output(struct gpio_chip= *chip, struct ad5592r_state *st =3D gpiochip_get_data(chip); int ret; =20 - mutex_lock(&st->gpio_lock); + guard(mutex)(&st->gpio_lock); =20 if (value) st->gpio_val |=3D BIT(offset); @@ -97,18 +89,13 @@ static int ad5592r_gpio_direction_output(struct gpio_ch= ip *chip, =20 ret =3D st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); if (ret < 0) - goto err_unlock; + return ret; =20 ret =3D st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); if (ret < 0) - goto err_unlock; + return ret; =20 - ret =3D st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); - -err_unlock: - mutex_unlock(&st->gpio_lock); - - return ret; + return st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); } =20 static int ad5592r_gpio_request(struct gpio_chip *chip, unsigned offset) @@ -171,10 +158,9 @@ static int ad5592r_reset(struct ad5592r_state *st) udelay(1); gpiod_set_value(gpio, 1); } else { - mutex_lock(&st->lock); - /* Writing this magic value resets the device */ - st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac); - mutex_unlock(&st->lock); + scoped_guard(mutex, &st->lock) + /* Writing this magic value resets the device */ + st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac); } =20 udelay(250); @@ -249,46 +235,44 @@ static int ad5592r_set_channel_modes(struct ad5592r_s= tate *st) } } =20 - mutex_lock(&st->lock); + guard(mutex)(&st->lock); =20 /* Pull down unused pins to GND */ ret =3D ops->reg_write(st, AD5592R_REG_PULLDOWN, pulldown); if (ret) - goto err_unlock; + return ret; =20 ret =3D ops->reg_write(st, AD5592R_REG_TRISTATE, tristate); if (ret) - goto err_unlock; + return ret; =20 /* Configure pins that we use */ ret =3D ops->reg_write(st, AD5592R_REG_DAC_EN, dac); if (ret) - goto err_unlock; + return ret; =20 ret =3D ops->reg_write(st, AD5592R_REG_ADC_EN, adc); if (ret) - goto err_unlock; + return ret; =20 ret =3D ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); if (ret) - goto err_unlock; + return ret; =20 ret =3D ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); if (ret) - goto err_unlock; + return ret; =20 ret =3D ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); if (ret) - goto err_unlock; + return ret; =20 /* Verify that we can read back at least one register */ ret =3D ops->reg_read(st, AD5592R_REG_ADC_EN, &read_back); if (!ret && (read_back & 0xff) !=3D adc) - ret =3D -EIO; + return -EIO; =20 -err_unlock: - mutex_unlock(&st->lock); - return ret; + return 0; } =20 static int ad5592r_reset_channel_modes(struct ad5592r_state *st) @@ -305,7 +289,7 @@ static int ad5592r_write_raw(struct iio_dev *iio_dev, struct iio_chan_spec const *chan, int val, int val2, long mask) { struct ad5592r_state *st =3D iio_priv(iio_dev); - int ret; + int ret =3D 0; =20 switch (mask) { case IIO_CHAN_INFO_RAW: @@ -316,11 +300,11 @@ static int ad5592r_write_raw(struct iio_dev *iio_dev, if (!chan->output) return -EINVAL; =20 - mutex_lock(&st->lock); - ret =3D st->ops->write_dac(st, chan->channel, val); - if (!ret) - st->cached_dac[chan->channel] =3D val; - mutex_unlock(&st->lock); + scoped_guard(mutex, &st->lock) { + ret =3D st->ops->write_dac(st, chan->channel, val); + if (!ret) + st->cached_dac[chan->channel] =3D val; + } return ret; case IIO_CHAN_INFO_SCALE: if (chan->type =3D=3D IIO_VOLTAGE) { @@ -335,7 +319,7 @@ static int ad5592r_write_raw(struct iio_dev *iio_dev, else return -EINVAL; =20 - mutex_lock(&st->lock); + guard(mutex)(&st->lock); =20 ret =3D st->ops->reg_read(st, AD5592R_REG_CTRL, &st->cached_gp_ctrl); @@ -360,11 +344,8 @@ static int ad5592r_write_raw(struct iio_dev *iio_dev, ~AD5592R_REG_CTRL_ADC_RANGE; } =20 - ret =3D st->ops->reg_write(st, AD5592R_REG_CTRL, - st->cached_gp_ctrl); - mutex_unlock(&st->lock); - - return ret; + return st->ops->reg_write(st, AD5592R_REG_CTRL, + st->cached_gp_ctrl); } break; default: @@ -379,15 +360,15 @@ static int ad5592r_read_raw(struct iio_dev *iio_dev, int *val, int *val2, long m) { struct ad5592r_state *st =3D iio_priv(iio_dev); - u16 read_val; - int ret, mult; + u16 read_val =3D 0; + int ret =3D 0, mult =3D 0; =20 switch (m) { case IIO_CHAN_INFO_RAW: if (!chan->output) { - mutex_lock(&st->lock); - ret =3D st->ops->read_adc(st, chan->channel, &read_val); - mutex_unlock(&st->lock); + scoped_guard(mutex, &st->lock) + ret =3D st->ops->read_adc(st, chan->channel, + &read_val); if (ret) return ret; =20 @@ -400,9 +381,8 @@ static int ad5592r_read_raw(struct iio_dev *iio_dev, read_val &=3D GENMASK(11, 0); =20 } else { - mutex_lock(&st->lock); - read_val =3D st->cached_dac[chan->channel]; - mutex_unlock(&st->lock); + scoped_guard(mutex, &st->lock) + read_val =3D st->cached_dac[chan->channel]; } =20 dev_dbg(st->dev, "Channel %u read: 0x%04hX\n", @@ -420,16 +400,14 @@ static int ad5592r_read_raw(struct iio_dev *iio_dev, return IIO_VAL_INT_PLUS_NANO; } =20 - mutex_lock(&st->lock); - - if (chan->output) - mult =3D !!(st->cached_gp_ctrl & - AD5592R_REG_CTRL_DAC_RANGE); - else - mult =3D !!(st->cached_gp_ctrl & - AD5592R_REG_CTRL_ADC_RANGE); - - mutex_unlock(&st->lock); + scoped_guard(mutex, &st->lock) { + if (chan->output) + mult =3D !!(st->cached_gp_ctrl & + AD5592R_REG_CTRL_DAC_RANGE); + else + mult =3D !!(st->cached_gp_ctrl & + AD5592R_REG_CTRL_ADC_RANGE); + } =20 *val *=3D ++mult; =20 @@ -439,15 +417,13 @@ static int ad5592r_read_raw(struct iio_dev *iio_dev, case IIO_CHAN_INFO_OFFSET: ret =3D ad5592r_get_vref(st); =20 - mutex_lock(&st->lock); + guard(mutex)(&st->lock); =20 if (st->cached_gp_ctrl & AD5592R_REG_CTRL_ADC_RANGE) *val =3D (-34365 * 25) / ret; else *val =3D (-75365 * 25) / ret; =20 - mutex_unlock(&st->lock); - return IIO_VAL_INT; default: return -EINVAL; --=20 2.45.2