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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Apr 2025 18:20:41.7096 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1e677989-d078-46fd-a049-08dd76ca1245 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7789 Content-Type: text/plain; charset="utf-8" Add the necessary support to enable Crater ethernet device. Since the BAR1 address cannot be used to access the XPCS registers on Crater, use the smn functions. Signed-off-by: Raju Rangoju --- drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 79 ++++++++++++++++++++++++ drivers/net/ethernet/amd/xgbe/xgbe.h | 6 ++ 2 files changed, 85 insertions(+) diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/etherne= t/amd/xgbe/xgbe-dev.c index ae82dc3ac460..d75cf8df272f 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c +++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c @@ -11,6 +11,7 @@ #include #include #include +#include =20 #include "xgbe.h" #include "xgbe-common.h" @@ -1066,6 +1067,78 @@ static void get_pcs_index_and_offset(struct xgbe_prv= _data *pdata, *offset =3D pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); } =20 +static int xgbe_read_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad, + int mmd_reg) +{ + unsigned int mmd_address, index, offset; + struct pci_dev *rdev; + unsigned long flags; + int mmd_data; + + rdev =3D pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); + if (!rdev) + return 0; + + mmd_address =3D get_mmd_address(pdata, mmd_reg); + + get_pcs_index_and_offset(pdata, mmd_address, &index, &offset); + + spin_lock_irqsave(&pdata->xpcs_lock, flags); + pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + pdata->xpcs_window= _sel_reg)); + pci_write_config_dword(rdev, 0x64, index); + pci_write_config_dword(rdev, 0x60, pdata->xphy_base + offset); + pci_read_config_dword(rdev, 0x64, &mmd_data); + mmd_data =3D (offset % 4) ? FIELD_GET(XGBE_GEN_HI_MASK, mmd_data) : + FIELD_GET(XGBE_GEN_LO_MASK, mmd_data); + + pci_dev_put(rdev); + spin_unlock_irqrestore(&pdata->xpcs_lock, flags); + + return mmd_data; +} + +static void xgbe_write_mmd_regs_v3(struct xgbe_prv_data *pdata, int prtad, + int mmd_reg, int mmd_data) +{ + unsigned int pci_mmd_data, hi_mask, lo_mask; + unsigned int mmd_address, index, offset; + struct pci_dev *rdev; + unsigned long flags; + + rdev =3D pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0)); + if (!rdev) + return; + + mmd_address =3D get_mmd_address(pdata, mmd_reg); + + get_pcs_index_and_offset(pdata, mmd_address, &index, &offset); + + spin_lock_irqsave(&pdata->xpcs_lock, flags); + pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + pdata->xpcs_window= _sel_reg)); + pci_write_config_dword(rdev, 0x64, index); + pci_write_config_dword(rdev, 0x60, pdata->xphy_base + offset); + pci_read_config_dword(rdev, 0x64, &pci_mmd_data); + + if (offset % 4) { + hi_mask =3D FIELD_PREP(XGBE_GEN_HI_MASK, mmd_data); + lo_mask =3D FIELD_GET(XGBE_GEN_LO_MASK, pci_mmd_data); + } else { + hi_mask =3D FIELD_PREP(XGBE_GEN_HI_MASK, + FIELD_GET(XGBE_GEN_HI_MASK, pci_mmd_data)); + lo_mask =3D FIELD_GET(XGBE_GEN_LO_MASK, mmd_data); + } + + pci_mmd_data =3D hi_mask | lo_mask; + + pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + pdata->xpcs_window= _sel_reg)); + pci_write_config_dword(rdev, 0x64, index); + pci_write_config_dword(rdev, 0x60, (pdata->xphy_base + offset)); + pci_write_config_dword(rdev, 0x64, pci_mmd_data); + pci_dev_put(rdev); + + spin_unlock_irqrestore(&pdata->xpcs_lock, flags); +} + static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, int mmd_reg) { @@ -1160,6 +1233,9 @@ static int xgbe_read_mmd_regs(struct xgbe_prv_data *p= data, int prtad, case XGBE_XPCS_ACCESS_V2: default: return xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg); + + case XGBE_XPCS_ACCESS_V3: + return xgbe_read_mmd_regs_v3(pdata, prtad, mmd_reg); } } =20 @@ -1173,6 +1249,9 @@ static void xgbe_write_mmd_regs(struct xgbe_prv_data = *pdata, int prtad, case XGBE_XPCS_ACCESS_V2: default: return xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data); + + case XGBE_XPCS_ACCESS_V3: + return xgbe_write_mmd_regs_v3(pdata, prtad, mmd_reg, mmd_data); } } =20 diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/am= d/xgbe/xgbe.h index 2e9b3be44ff8..6c49bf19e537 100644 --- a/drivers/net/ethernet/amd/xgbe/xgbe.h +++ b/drivers/net/ethernet/amd/xgbe/xgbe.h @@ -242,6 +242,10 @@ #define XGBE_RV_PCI_DEVICE_ID 0x15d0 #define XGBE_YC_PCI_DEVICE_ID 0x14b5 =20 + /* Generic low and high masks */ +#define XGBE_GEN_HI_MASK GENMASK(31, 16) +#define XGBE_GEN_LO_MASK GENMASK(15, 0) + struct xgbe_prv_data; =20 struct xgbe_packet_data { @@ -460,6 +464,7 @@ enum xgbe_speed { enum xgbe_xpcs_access { XGBE_XPCS_ACCESS_V1 =3D 0, XGBE_XPCS_ACCESS_V2, + XGBE_XPCS_ACCESS_V3, }; =20 enum xgbe_an_mode { @@ -951,6 +956,7 @@ struct xgbe_prv_data { struct device *dev; struct platform_device *phy_platdev; struct device *phy_dev; + unsigned int xphy_base; =20 /* Version related data */ struct xgbe_version_data *vdata; --=20 2.34.1