From nobody Mon Feb 9 01:51:37 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EDC5320F; Tue, 8 Apr 2025 13:25:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744118737; cv=none; b=nIdPEpEH8wg/qQTFwn+xSv1KQQ5zfmyWfhY4JuvsowIKPp86BF3PqTw4tJAcH8zij/Mxh5nSWNwBe1Lsx94Wbkfj5D0D/CNRBvKd2+6IWIdx6wgd7/uhJY6qk4epHIZBYaTSl7n/u2frtNmTWcmZAM9zKi6zV+bAdtVKNI5XWGk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744118737; c=relaxed/simple; bh=NHSpW9e+meHIZV0X3SUJ0MZoalf/ZJrgkR4A2Jp1pqo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ML9P0zRzQI8f6dPf7IbX1+PRNyjkpJhFPQe70RLy1BbQKdPxaoCb1hxdpJl2O1oEcetospBkiziVkonQC6ADAGdjW8g07tQm5YzM9g5nsT3WDcvTOJJuyfCgsBl3nPZ56xSCtM5UuCwcONI9fiehkqafy2c2tXqUDAupqbACr60= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XB3ggbkq; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XB3ggbkq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744118736; x=1775654736; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NHSpW9e+meHIZV0X3SUJ0MZoalf/ZJrgkR4A2Jp1pqo=; b=XB3ggbkq5HAnG0wXQNqx0E3FvJNYXrzwQKeP4ZQq/+ddr5Ss+qcf+j7M WwYVXBedIOQTyup38/7ZC9LfmFZqdw+LF9WmusNwb9vEC3Mz5Bho7t5dS voejiSdGh+e6muIhmvvjYkR2pTTBByXJvNBxiQsIGCU7sIWIHLLxCyCx8 ubvhbVLkgNwGoURFZ9uQQQH4SO1AT32Xukg3RdLiYVqF7/npYK5E/WQQF OdYeAdDN9WqMVhENExOH5qtyDSSNrswxxCUkZWe0L2KuBq96ZDMqFQV9k /0D1v/65TpRe5QzUejmdMtx1gd03COlZwasJFOt77XX5fsAFHi7WEnVBU Q==; X-CSE-ConnectionGUID: smrjaQg8QniwB4dmbNMw0w== X-CSE-MsgGUID: v+Rmu2V7Re+HE97/3zaEAg== X-IronPort-AV: E=McAfee;i="6700,10204,11397"; a="44799620" X-IronPort-AV: E=Sophos;i="6.15,198,1739865600"; d="scan'208";a="44799620" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Apr 2025 06:25:35 -0700 X-CSE-ConnectionGUID: 6ZFuHMXzTzaLHH/c9Q9jzw== X-CSE-MsgGUID: 8IEWc3TDQfen9GuS5PwKSg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,198,1739865600"; d="scan'208";a="159258212" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Apr 2025 06:25:33 -0700 From: Qiuxu Zhuo To: Tony Luck Cc: Qiuxu Zhuo , Borislav Petkov , James Morse , Mauro Carvalho Chehab , Robert Richter , Yi Lai , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] EDAC/igen6: Skip the absent memory controllers Date: Tue, 8 Apr 2025 21:24:53 +0800 Message-ID: <20250408132455.489046-2-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250408132455.489046-1-qiuxu.zhuo@intel.com> References: <20250408132455.489046-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some BIOS versions may fuse off certain memory controllers and set the registers of these absent memory controllers to ~0. The current igen6_edac mistakenly enumerates these absent memory controllers and registers them with the EDAC core. Skip the absent memory controllers to avoid mistakenly enumerating them. Signed-off-by: Qiuxu Zhuo --- drivers/edac/igen6_edac.c | 78 +++++++++++++++++++++++++++++++-------- 1 file changed, 62 insertions(+), 16 deletions(-) diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c index 5807517ee32d..ec64bff8236f 100644 --- a/drivers/edac/igen6_edac.c +++ b/drivers/edac/igen6_edac.c @@ -127,6 +127,7 @@ =20 static const struct res_config { bool machine_check; + /* The number of present memory controllers. */ int num_imc; u32 imc_base; u32 cmf_base; @@ -1201,23 +1202,21 @@ static void igen6_check(struct mem_ctl_info *mci) irq_work_queue(&ecclog_irq_work); } =20 -static int igen6_register_mci(int mc, u64 mchbar, struct pci_dev *pdev) +/* Check whether the memory controller is absent. */ +static bool igen6_imc_absent(void __iomem *window) +{ + return readl(window + MAD_INTER_CHANNEL_OFFSET) =3D=3D ~0; +} + +static int igen6_register_mci(int mc, void __iomem *window, struct pci_dev= *pdev) { struct edac_mc_layer layers[2]; struct mem_ctl_info *mci; struct igen6_imc *imc; - void __iomem *window; int rc; =20 edac_dbg(2, "\n"); =20 - mchbar +=3D mc * MCHBAR_SIZE; - window =3D ioremap(mchbar, MCHBAR_SIZE); - if (!window) { - igen6_printk(KERN_ERR, "Failed to ioremap 0x%llx\n", mchbar); - return -ENODEV; - } - layers[0].type =3D EDAC_MC_LAYER_CHANNEL; layers[0].size =3D NUM_CHANNELS; layers[0].is_virt_csrow =3D false; @@ -1283,7 +1282,6 @@ static int igen6_register_mci(int mc, u64 mchbar, str= uct pci_dev *pdev) fail2: edac_mc_free(mci); fail: - iounmap(window); return rc; } =20 @@ -1309,6 +1307,56 @@ static void igen6_unregister_mcis(void) } } =20 +static int igen6_register_mcis(struct pci_dev *pdev, u64 mchbar) +{ + void __iomem *window; + int lmc, pmc, rc; + u64 base; + + for (lmc =3D 0, pmc =3D 0; pmc < NUM_IMC; pmc++) { + base =3D mchbar + pmc * MCHBAR_SIZE; + window =3D ioremap(base, MCHBAR_SIZE); + if (!window) { + igen6_printk(KERN_ERR, "Failed to ioremap 0x%llx for mc%d\n", base, pmc= ); + rc =3D -ENOMEM; + goto out_unregister_mcis; + } + + if (igen6_imc_absent(window)) { + iounmap(window); + edac_dbg(2, "Skip absent mc%d\n", pmc); + continue; + } + + rc =3D igen6_register_mci(lmc, window, pdev); + if (rc) + goto out_iounmap; + + /* Done, if all present MCs are detected and registered. */ + if (++lmc >=3D res_cfg->num_imc) + break; + } + + if (!lmc) { + igen6_printk(KERN_ERR, "No mc found.\n"); + return -ENODEV; + } + + if (lmc < res_cfg->num_imc) + igen6_printk(KERN_WARNING, "Expected %d mcs, but only %d detected.", + res_cfg->num_imc, lmc); + + return 0; + +out_iounmap: + iounmap(window); + +out_unregister_mcis: + igen6_unregister_mcis(); + + return rc; +} + static int igen6_mem_slice_setup(u64 mchbar) { struct igen6_imc *imc =3D &igen6_pvt->imc[0]; @@ -1405,7 +1453,7 @@ static void opstate_set(const struct res_config *cfg,= const struct pci_device_id static int igen6_probe(struct pci_dev *pdev, const struct pci_device_id *e= nt) { u64 mchbar; - int i, rc; + int rc; =20 edac_dbg(2, "\n"); =20 @@ -1421,11 +1469,9 @@ static int igen6_probe(struct pci_dev *pdev, const s= truct pci_device_id *ent) =20 opstate_set(res_cfg, ent); =20 - for (i =3D 0; i < res_cfg->num_imc; i++) { - rc =3D igen6_register_mci(i, mchbar, pdev); - if (rc) - goto fail2; - } + rc =3D igen6_register_mcis(pdev, mchbar); + if (rc) + goto fail; =20 if (res_cfg->num_imc > 1) { rc =3D igen6_mem_slice_setup(mchbar); --=20 2.43.0 From nobody Mon Feb 9 01:51:37 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C750B3BBF2; Tue, 8 Apr 2025 13:25:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744118747; cv=none; b=IvXS8KS/yNG6c3fMEKf0/4OdQsyM1aONGLWn0OQavflCqNvFS+YTnQRDizGTjy8TuBYPlrKeetFs45JPvi1MVvcRJMqrM5zgny1ZHwGskU3HG7ZToC49318X4jhy72yDJVCIkTdKlawA+S8S/DzeAlrp/sOhmarz6WLaf1PJ+pU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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d="scan'208";a="159258217" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Apr 2025 06:25:42 -0700 From: Qiuxu Zhuo To: Tony Luck Cc: Qiuxu Zhuo , Borislav Petkov , James Morse , Mauro Carvalho Chehab , Robert Richter , Yi Lai , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] EDAC/igen6: Add Intel Arizona Beach SoCs support Date: Tue, 8 Apr 2025 21:24:54 +0800 Message-ID: <20250408132455.489046-3-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250408132455.489046-1-qiuxu.zhuo@intel.com> References: <20250408132455.489046-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Intel Arizona Lake SoC series is oriented toward network computing. Some types of these SoCs are equipped with IBECC(In-Band ECC) and share the same IBECC registers with Alder Lake-N SoCs. Add a die ID for Arizona Lake SoC for EDAC support. Signed-off-by: Qiuxu Zhuo --- drivers/edac/igen6_edac.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c index ec64bff8236f..13314f24536b 100644 --- a/drivers/edac/igen6_edac.c +++ b/drivers/edac/igen6_edac.c @@ -241,6 +241,9 @@ static struct work_struct ecclog_work; #define DID_ADL_N_SKU11 0x467c #define DID_ADL_N_SKU12 0x4632 =20 +/* Compute die IDs for Arizona Beach with IBECC */ +#define DID_AZB_SKU1 0x4676 + /* Compute die IDs for Raptor Lake-P with IBECC */ #define DID_RPL_P_SKU1 0xa706 #define DID_RPL_P_SKU2 0xa707 @@ -596,6 +599,7 @@ static const struct pci_device_id igen6_pci_tbl[] =3D { { PCI_VDEVICE(INTEL, DID_ADL_N_SKU10), (kernel_ulong_t)&adl_n_cfg }, { PCI_VDEVICE(INTEL, DID_ADL_N_SKU11), (kernel_ulong_t)&adl_n_cfg }, { PCI_VDEVICE(INTEL, DID_ADL_N_SKU12), (kernel_ulong_t)&adl_n_cfg }, + { PCI_VDEVICE(INTEL, DID_AZB_SKU1), (kernel_ulong_t)&adl_n_cfg }, { PCI_VDEVICE(INTEL, DID_RPL_P_SKU1), (kernel_ulong_t)&rpl_p_cfg }, { PCI_VDEVICE(INTEL, DID_RPL_P_SKU2), (kernel_ulong_t)&rpl_p_cfg }, { PCI_VDEVICE(INTEL, DID_RPL_P_SKU3), (kernel_ulong_t)&rpl_p_cfg }, --=20 2.43.0 From nobody Mon Feb 9 01:51:37 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56DF43BBF2; Tue, 8 Apr 2025 13:25:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744118755; cv=none; b=DUHqGws8Q/e81h+nEwRl72x21nDKvR+69EniQBxGOfqvBL3kFRDUvMJZ+Fj2WPeRjiHCpqa3nuJp0l1xO7x5ap4TOlYKIZE8O8gzZoT1act8kUFeEEVQ4sxCk7wiHV94Dtl4XgUqjkVJZGT4nHSOPUbteLNIaS39pzBLPvATOzo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744118755; c=relaxed/simple; bh=eIYL+W0qNdQyEZYoFpWw1PXFI0J3GSiKF7Bhr9jioTs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SBOI9YN1s/pFXzKGhAenVHL4nnES7dkoJr9gtLrvyvq/t/ucEVxykcgE853a7QIJ8xlMDaT9jhV4ygWTla310+FOXt7/K+3Iabzgqiv5FB6Dv7FBr3Zpc7DJU7mM9Xr/h5QBxKQ9OJOAzTBR5EZGNP72ijo+s1amhIldkCfDtOY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Dw2SA4Km; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Dw2SA4Km" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744118753; x=1775654753; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eIYL+W0qNdQyEZYoFpWw1PXFI0J3GSiKF7Bhr9jioTs=; b=Dw2SA4KmZnyInFRtiZwA9+hq1QCb87IUyDVb4QPhgIvFf7FuoMNd3Var Xwth12+JmBSobt64O/wmyJA3OzEQvYx63QctXpjBv5rHJPm9uVOHGNkVC yvf3nH56SJ2Bz4pYgy6q+sN6LeQkiX/sKLuGu6371v4Nk+uZqMv+MZYKo ZTh3Yj+pEk5HKuNlRgqVdcXMrrGMv457F700iGGLk3p7an5XqGBsiyOnE 6+DKqnJkVtpVI2xNr1nfT+ClXa7ZKVv7faN/2Yiizkml1BGMUhRDErq3k rRm793S0dU21zXtnWtg+3L7oprQ8kq1KhJKIBqm6aSKAbBnxwr4dlFKLj Q==; X-CSE-ConnectionGUID: IresKA8bSwSz6RNcPiREKg== X-CSE-MsgGUID: qmxyXPFMR++QAMVqfNNQBw== X-IronPort-AV: E=McAfee;i="6700,10204,11397"; a="44799638" X-IronPort-AV: E=Sophos;i="6.15,198,1739865600"; d="scan'208";a="44799638" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Apr 2025 06:25:52 -0700 X-CSE-ConnectionGUID: BrPx6C64RyuOYPmsvMbJXg== X-CSE-MsgGUID: XKLRXlQfQyaB/vwio25t6Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,198,1739865600"; d="scan'208";a="159258220" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Apr 2025 06:25:50 -0700 From: Qiuxu Zhuo To: Tony Luck Cc: Qiuxu Zhuo , Borislav Petkov , James Morse , Mauro Carvalho Chehab , Robert Richter , Yi Lai , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] EDAC/igen6: Add Intel Amston Lake SoCs support Date: Tue, 8 Apr 2025 21:24:55 +0800 Message-ID: <20250408132455.489046-4-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250408132455.489046-1-qiuxu.zhuo@intel.com> References: <20250408132455.489046-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Intel Amston Lake is a series of SoCs tailored for edge computing needs. The Amston Lake SoCs, equipped with IBECC(In-Band ECC) capability, share the same IBECC registers with Alder Lake-N SoCs. Add the Intel Amston Lake SoC compute die ID for EDAC support. Signed-off-by: Qiuxu Zhuo --- drivers/edac/igen6_edac.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/edac/igen6_edac.c b/drivers/edac/igen6_edac.c index 13314f24536b..1930dc00c791 100644 --- a/drivers/edac/igen6_edac.c +++ b/drivers/edac/igen6_edac.c @@ -244,6 +244,9 @@ static struct work_struct ecclog_work; /* Compute die IDs for Arizona Beach with IBECC */ #define DID_AZB_SKU1 0x4676 =20 +/* Compute did IDs for Amston Lake with IBECC */ +#define DID_ASL_SKU1 0x464a + /* Compute die IDs for Raptor Lake-P with IBECC */ #define DID_RPL_P_SKU1 0xa706 #define DID_RPL_P_SKU2 0xa707 @@ -600,6 +603,7 @@ static const struct pci_device_id igen6_pci_tbl[] =3D { { PCI_VDEVICE(INTEL, DID_ADL_N_SKU11), (kernel_ulong_t)&adl_n_cfg }, { PCI_VDEVICE(INTEL, DID_ADL_N_SKU12), (kernel_ulong_t)&adl_n_cfg }, { PCI_VDEVICE(INTEL, DID_AZB_SKU1), (kernel_ulong_t)&adl_n_cfg }, + { PCI_VDEVICE(INTEL, DID_ASL_SKU1), (kernel_ulong_t)&adl_n_cfg }, { PCI_VDEVICE(INTEL, DID_RPL_P_SKU1), (kernel_ulong_t)&rpl_p_cfg }, { PCI_VDEVICE(INTEL, DID_RPL_P_SKU2), (kernel_ulong_t)&rpl_p_cfg }, { PCI_VDEVICE(INTEL, DID_RPL_P_SKU3), (kernel_ulong_t)&rpl_p_cfg }, --=20 2.43.0