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[76.88.115.8]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-af9bc41af71sm7439565a12.75.2025.04.08.06.21.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Apr 2025 06:21:42 -0700 (PDT) From: Sukrut Bellary To: Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Angelo Compagnucci Cc: Sukrut Bellary , Nishanth Menon , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH 1/2] dt-bindings: iio: adc: ti,adc128s052: Add adc08c and adc10c family Date: Tue, 8 Apr 2025 06:21:19 -0700 Message-Id: <20250408132120.836461-2-sbellary@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250408132120.836461-1-sbellary@baylibre.com> References: <20250408132120.836461-1-sbellary@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The adcxx4s communicates with a host processor via an SPI/Microwire Bus interface. The device family responds with 12-bit data, of which the LSB bits are 0 for the lower resolution devices. The unavailable bits are 0 in LSB. Shift is calculated per resolution and used in scaling and raw data read. I have been able to test adc102s051, hence adding just the missing ones in that family. Lets reuse the binding to support the family of devices with name ADCS, where * bb is the resolution in number of bits (8, 10, 12) * c is the number of channels (1, 2, 4, 8) * sss is the maximum conversion speed (021 for 200 kSPS, 051 for 500 kSPS and 101 for 1 MSPS) Complete datasheets are available at TI's website here: https://www.ti.com/lit/gpn/adcs.pdf Co-developed-by: Nishanth Menon Signed-off-by: Nishanth Menon Signed-off-by: Sukrut Bellary Acked-by: Krzysztof Kozlowski --- Changes in v3: - No changes in dt-bindings - Link to v2: https://lore.kernel.org/lkml/20231022031203.632153-1-sukrut.= bellary@linux.com/ Changes in v2:=20 - No changes in dt-bindings - Link to v1: https://lore.kernel.org/all/20220701042919.18180-2-nm@ti.com/ --- .../devicetree/bindings/iio/adc/ti,adc128s052.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/ti,adc128s052.yaml b= /Documentation/devicetree/bindings/iio/adc/ti,adc128s052.yaml index 775eee972b12..392b4a3e867c 100644 --- a/Documentation/devicetree/bindings/iio/adc/ti,adc128s052.yaml +++ b/Documentation/devicetree/bindings/iio/adc/ti,adc128s052.yaml @@ -16,6 +16,12 @@ description: | properties: compatible: enum: + - ti,adc082s021 + - ti,adc082s051 + - ti,adc082s101 + - ti,adc102s021 + - ti,adc102s051 + - ti,adc102s101 - ti,adc122s021 - ti,adc122s051 - ti,adc122s101 --=20 2.34.1 From nobody Sun Feb 8 12:14:54 2026 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A78518E743 for ; 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[76.88.115.8]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-af9bc41af71sm7439565a12.75.2025.04.08.06.21.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Apr 2025 06:21:46 -0700 (PDT) From: Sukrut Bellary To: Jonathan Cameron , Lars-Peter Clausen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Angelo Compagnucci Cc: Sukrut Bellary , Nishanth Menon , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] iio: adc: ti-adc128s052: Add lower resolution devices support Date: Tue, 8 Apr 2025 06:21:20 -0700 Message-Id: <20250408132120.836461-3-sbellary@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250408132120.836461-1-sbellary@baylibre.com> References: <20250408132120.836461-1-sbellary@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The adcxx4s communicates with a host processor via an SPI/Microwire Bus interface. The device family responds with 12-bit data, of which the LSB bits are transmitted by the lower resolution devices as 0. The unavailable bits are 0 in LSB. Shift is calculated per resolution and used in scaling and raw data read. Lets reuse the driver to support the family of devices with name ADCS, where * bb is the resolution in number of bits (8, 10, 12) * c is the number of channels (1, 2, 4, 8) * sss is the maximum conversion speed (021 for 200 kSPS, 051 for 500 kSPS and 101 for 1 MSPS) Complete datasheets are available at TI's website here: https://www.ti.com/lit/gpn/adcs.pdf Tested only with ti-adc102s051 on BegalePlay SBC. https://www.beagleboard.org/boards/beagleplay Co-developed-by: Nishanth Menon Signed-off-by: Nishanth Menon Signed-off-by: Sukrut Bellary --- Changes in v3:=20 - used be16_to_cpu() for the endian conversion. - used config index enum while setting up the adc128_config[] - Link to v2:=20 https://lore.kernel.org/lkml/20231022031203.632153-1-sukrut.bellary= @linux.com/ Changes in v2: - Arranged of_device_id and spi_device_id in numeric order. - Used enum to index into adc128_config. - Reorder adc128_config in alphabetical. - Include channel resolution information. - Shift is calculated per resolution and used in scaling and=20 raw data read. - Link to v1: https://lore.kernel.org/all/20220701042919.18180-1-nm@ti.com/ --- drivers/iio/adc/ti-adc128s052.c | 149 ++++++++++++++++++++++++-------- 1 file changed, 112 insertions(+), 37 deletions(-) diff --git a/drivers/iio/adc/ti-adc128s052.c b/drivers/iio/adc/ti-adc128s05= 2.c index a456ea78462f..d4b76fd85abd 100644 --- a/drivers/iio/adc/ti-adc128s052.c +++ b/drivers/iio/adc/ti-adc128s052.c @@ -7,6 +7,22 @@ * https://www.ti.com/lit/ds/symlink/adc128s052.pdf * https://www.ti.com/lit/ds/symlink/adc122s021.pdf * https://www.ti.com/lit/ds/symlink/adc124s021.pdf + * + * The adcxx4s communicates with a host processor via an SPI/Microwire Bus + * interface. This driver supports the whole family of devices with a name + * ADCS, where + * bb is the resolution in number of bits (8, 10, 12) + * c is the number of channels (1, 2, 4, 8) + * sss is the maximum conversion speed (021 for 200 kSPS, 051 for 500 kSPS + * and 101 for 1 MSPS) + * + * Complete datasheets are available at TI's website here: + * https://www.ti.com/lit/gpn/adcs.pdf + * + * 8, 10, and 12 bits converters send 12-bit data with + * unavailable bits set to 0 in LSB. + * Shift is calculated per resolution and used in scaling and + * raw data read. */ =20 #include @@ -53,7 +69,7 @@ static int adc128_adc_conversion(struct adc128 *adc, u8 c= hannel) if (ret < 0) return ret; =20 - return ((adc->buffer[0] << 8 | adc->buffer[1]) & 0xFFF); + return be16_to_cpu(*((__be16 *)adc->buffer)); } =20 static int adc128_read_raw(struct iio_dev *indio_dev, @@ -70,7 +86,8 @@ static int adc128_read_raw(struct iio_dev *indio_dev, if (ret < 0) return ret; =20 - *val =3D ret; + *val =3D (ret >> channel->scan_type.shift) & + GENMASK(channel->scan_type.realbits - 1, 0); return IIO_VAL_INT; =20 case IIO_CHAN_INFO_SCALE: @@ -80,7 +97,7 @@ static int adc128_read_raw(struct iio_dev *indio_dev, return ret; =20 *val =3D ret / 1000; - *val2 =3D 12; + *val2 =3D channel->scan_type.realbits; return IIO_VAL_FRACTIONAL_LOG2; =20 default: @@ -89,24 +106,34 @@ static int adc128_read_raw(struct iio_dev *indio_dev, =20 } =20 -#define ADC128_VOLTAGE_CHANNEL(num) \ - { \ - .type =3D IIO_VOLTAGE, \ - .indexed =3D 1, \ - .channel =3D (num), \ - .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ - .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE) \ +#define _ADC128_VOLTAGE_CHANNEL(num, real_bits, store_bits) \ + { \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .channel =3D (num), \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_RAW), \ + .info_mask_shared_by_type =3D BIT(IIO_CHAN_INFO_SCALE), \ + .scan_index =3D (num), \ + .scan_type =3D { \ + .sign =3D 'u', \ + .realbits =3D (real_bits), \ + .storagebits =3D (store_bits), \ + .shift =3D (12 - real_bits), \ + }, \ } =20 -static const struct iio_chan_spec adc128s052_channels[] =3D { - ADC128_VOLTAGE_CHANNEL(0), - ADC128_VOLTAGE_CHANNEL(1), - ADC128_VOLTAGE_CHANNEL(2), - ADC128_VOLTAGE_CHANNEL(3), - ADC128_VOLTAGE_CHANNEL(4), - ADC128_VOLTAGE_CHANNEL(5), - ADC128_VOLTAGE_CHANNEL(6), - ADC128_VOLTAGE_CHANNEL(7), +#define ADC082_VOLTAGE_CHANNEL(num) _ADC128_VOLTAGE_CHANNEL(num, 8, 16) +#define ADC102_VOLTAGE_CHANNEL(num) _ADC128_VOLTAGE_CHANNEL(num, 10, 16) +#define ADC128_VOLTAGE_CHANNEL(num) _ADC128_VOLTAGE_CHANNEL(num, 12, 16) + +static const struct iio_chan_spec adc082s021_channels[] =3D { + ADC082_VOLTAGE_CHANNEL(0), + ADC082_VOLTAGE_CHANNEL(1), +}; + +static const struct iio_chan_spec adc102s021_channels[] =3D { + ADC102_VOLTAGE_CHANNEL(0), + ADC102_VOLTAGE_CHANNEL(1), }; =20 static const struct iio_chan_spec adc122s021_channels[] =3D { @@ -121,10 +148,46 @@ static const struct iio_chan_spec adc124s021_channels= [] =3D { ADC128_VOLTAGE_CHANNEL(3), }; =20 +static const struct iio_chan_spec adc128s052_channels[] =3D { + ADC128_VOLTAGE_CHANNEL(0), + ADC128_VOLTAGE_CHANNEL(1), + ADC128_VOLTAGE_CHANNEL(2), + ADC128_VOLTAGE_CHANNEL(3), + ADC128_VOLTAGE_CHANNEL(4), + ADC128_VOLTAGE_CHANNEL(5), + ADC128_VOLTAGE_CHANNEL(6), + ADC128_VOLTAGE_CHANNEL(7), +}; + +enum adc128_configuration_index { + ADC128_CONFIG_INDEX_082S, + ADC128_CONFIG_INDEX_102S, + ADC128_CONFIG_INDEX_122S, + ADC128_CONFIG_INDEX_124S, + ADC128_CONFIG_INDEX_128S, +}; + static const struct adc128_configuration adc128_config[] =3D { - { adc128s052_channels, ARRAY_SIZE(adc128s052_channels) }, - { adc122s021_channels, ARRAY_SIZE(adc122s021_channels) }, - { adc124s021_channels, ARRAY_SIZE(adc124s021_channels) }, + [ADC128_CONFIG_INDEX_082S] =3D { + .channels =3D adc082s021_channels, + .num_channels =3D ARRAY_SIZE(adc082s021_channels) + }, + [ADC128_CONFIG_INDEX_102S] =3D { + .channels =3D adc102s021_channels, + .num_channels =3D ARRAY_SIZE(adc102s021_channels) + }, + [ADC128_CONFIG_INDEX_122S] =3D { + .channels =3D adc122s021_channels, + .num_channels =3D ARRAY_SIZE(adc122s021_channels) + }, + [ADC128_CONFIG_INDEX_124S] =3D { + .channels =3D adc124s021_channels, + .num_channels =3D ARRAY_SIZE(adc124s021_channels) + }, + [ADC128_CONFIG_INDEX_128S] =3D { + .channels =3D adc128s052_channels, + .num_channels =3D ARRAY_SIZE(adc128s052_channels) + }, }; =20 static const struct iio_info adc128_info =3D { @@ -177,31 +240,43 @@ static int adc128_probe(struct spi_device *spi) } =20 static const struct of_device_id adc128_of_match[] =3D { - { .compatible =3D "ti,adc128s052", .data =3D &adc128_config[0] }, - { .compatible =3D "ti,adc122s021", .data =3D &adc128_config[1] }, - { .compatible =3D "ti,adc122s051", .data =3D &adc128_config[1] }, - { .compatible =3D "ti,adc122s101", .data =3D &adc128_config[1] }, - { .compatible =3D "ti,adc124s021", .data =3D &adc128_config[2] }, - { .compatible =3D "ti,adc124s051", .data =3D &adc128_config[2] }, - { .compatible =3D "ti,adc124s101", .data =3D &adc128_config[2] }, + { .compatible =3D "ti,adc082s021", .data =3D &adc128_config[ADC128_CONFIG= _INDEX_082S] }, + { .compatible =3D "ti,adc082s051", .data =3D &adc128_config[ADC128_CONFIG= _INDEX_082S] }, + { .compatible =3D "ti,adc082s101", .data =3D &adc128_config[ADC128_CONFIG= _INDEX_082S] }, + { .compatible =3D "ti,adc102s021", .data =3D &adc128_config[ADC128_CONFIG= _INDEX_102S] }, + { .compatible =3D "ti,adc102s051", .data =3D &adc128_config[ADC128_CONFIG= _INDEX_102S] }, + { .compatible =3D "ti,adc102s101", .data =3D &adc128_config[ADC128_CONFIG= _INDEX_102S] }, + { .compatible =3D "ti,adc122s021", .data =3D &adc128_config[ADC128_CONFIG= _INDEX_122S] }, + { .compatible =3D "ti,adc122s051", .data =3D &adc128_config[ADC128_CONFIG= _INDEX_122S] }, + { .compatible =3D "ti,adc122s101", .data =3D &adc128_config[ADC128_CONFIG= _INDEX_122S] }, + { .compatible =3D "ti,adc124s021", .data =3D &adc128_config[ADC128_CONFIG= _INDEX_124S] }, + { .compatible =3D "ti,adc124s051", .data =3D &adc128_config[ADC128_CONFIG= _INDEX_124S] }, + { .compatible =3D "ti,adc124s101", .data =3D &adc128_config[ADC128_CONFIG= _INDEX_124S] }, + { .compatible =3D "ti,adc128s052", .data =3D &adc128_config[ADC128_CONFIG= _INDEX_128S] }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, adc128_of_match); =20 static const struct spi_device_id adc128_id[] =3D { - { "adc128s052", (kernel_ulong_t)&adc128_config[0] }, - { "adc122s021", (kernel_ulong_t)&adc128_config[1] }, - { "adc122s051", (kernel_ulong_t)&adc128_config[1] }, - { "adc122s101", (kernel_ulong_t)&adc128_config[1] }, - { "adc124s021", (kernel_ulong_t)&adc128_config[2] }, - { "adc124s051", (kernel_ulong_t)&adc128_config[2] }, - { "adc124s101", (kernel_ulong_t)&adc128_config[2] }, + { "adc082s021", (kernel_ulong_t)&adc128_config[ADC128_CONFIG_INDEX_082S] = }, + { "adc082s051", (kernel_ulong_t)&adc128_config[ADC128_CONFIG_INDEX_082S] = }, + { "adc082s101", (kernel_ulong_t)&adc128_config[ADC128_CONFIG_INDEX_082S] = }, + { "adc102s021", (kernel_ulong_t)&adc128_config[ADC128_CONFIG_INDEX_102S] = }, + { "adc102s051", (kernel_ulong_t)&adc128_config[ADC128_CONFIG_INDEX_102S] = }, + { "adc102s101", (kernel_ulong_t)&adc128_config[ADC128_CONFIG_INDEX_102S] = }, + { "adc122s021", (kernel_ulong_t)&adc128_config[ADC128_CONFIG_INDEX_122S] = }, + { "adc122s051", (kernel_ulong_t)&adc128_config[ADC128_CONFIG_INDEX_122S] = }, + { "adc122s101", (kernel_ulong_t)&adc128_config[ADC128_CONFIG_INDEX_122S] = }, + { "adc124s021", (kernel_ulong_t)&adc128_config[ADC128_CONFIG_INDEX_124S] = }, + { "adc124s051", (kernel_ulong_t)&adc128_config[ADC128_CONFIG_INDEX_124S] = }, + { "adc124s101", (kernel_ulong_t)&adc128_config[ADC128_CONFIG_INDEX_124S] = }, + { "adc128s052", (kernel_ulong_t)&adc128_config[ADC128_CONFIG_INDEX_128S] = }, { } }; MODULE_DEVICE_TABLE(spi, adc128_id); =20 static const struct acpi_device_id adc128_acpi_match[] =3D { - { "AANT1280", (kernel_ulong_t)&adc128_config[2] }, + { "AANT1280", (kernel_ulong_t)&adc128_config[ADC128_CONFIG_INDEX_124S] }, { } }; MODULE_DEVICE_TABLE(acpi, adc128_acpi_match); --=20 2.34.1