From nobody Fri Dec 19 20:28:17 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33D61266B55; Tue, 8 Apr 2025 10:36:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744108584; cv=none; b=qg0Lw2oHzRVcsiR3i+vN6G70msQpqmapQnnEe8jwqAsMu6FvpGKSa8mnK7qLP/xQuJptYh5NVm0aHTN1c3COZJQXoYY4zd3NzwbtP141925O9zeOipWq9rv46HxOEb70H4Nzy7tODic8A+mDtzdmgKHpMuR5ZE1+BKCQwMcGIiI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744108584; c=relaxed/simple; bh=66XE36a6ibZulGjDZqvbEm80NqjNSQc32BtllAoJtT8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=q2B0UdWq2tYE9L1v0tYKj3XhvWdPcD00AXKpLsjcUfOIJa9ckr5y+4UyqmhH24QKXFGOGwDWrOfddDUx7UdtqPJlYpP//0CnicOO5/unVUvQekDjwRPL1d7FxOuyYM2U68kHqJhh7552qR3Qribd3tQvX4ZmJ/ZXseUNd5LWnPM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=bUmwAx3m; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="bUmwAx3m" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 538AaF2e1150088 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 8 Apr 2025 05:36:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1744108575; bh=PbIXTJ8cqYyRq4DH9ZIEbVM9db9hbL/vEEhMzlT0zZk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bUmwAx3mmKlR4xs33su2aKXb5VPw48f2mLZHrtj4/Oh44BNNmwgjGIg1t507G8lQ4 CiI97d2R295S3PJ1gk1/ZEitShFCRyK0+aGRC+uV2dg9utpa+6gvhyob+v+oHGpGYy uBAfc/MO/PdT8BIYNWqX2qQZrN3dq6/KkQ6wNmHA= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 538AaFK0028494 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Apr 2025 05:36:15 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 8 Apr 2025 05:36:15 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 8 Apr 2025 05:36:14 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 538Aa6T8016171; Tue, 8 Apr 2025 05:36:11 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , , Subject: [PATCH v2 1/2] arm64: dts: ti: k3-j722s-evm: Enable "serdes_wiz0" and "serdes_wiz1" Date: Tue, 8 Apr 2025 16:06:05 +0530 Message-ID: <20250408103606.3679505-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250408103606.3679505-1-s-vadapalli@ti.com> References: <20250408103606.3679505-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" In preparation for disabling "serdes_wiz0" and "serdes_wiz1" device-tree nodes in the SoC file, enable them in the board file. The motivation for this change is that of following the existing convention of disabling nodes in the SoC file and only enabling the required ones in the board file. Fixes: 485705df5d5f ("arm64: dts: ti: k3-j722s: Enable PCIe and USB support= on J722S-EVM") Cc: stable@vger.kernel.org Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar --- v1 of this patch is at: https://lore.kernel.org/r/20250408060636.3413856-2-s-vadapalli@ti.com/ Changes since v1: - Added "Fixes" tag and updated commit message accordingly. Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index 2127316f36a3..0bf2e1821662 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -843,6 +843,10 @@ &serdes_ln_ctrl { ; }; =20 +&serdes_wiz0 { + status =3D "okay"; +}; + &serdes0 { status =3D "okay"; serdes0_usb_link: phy@0 { @@ -854,6 +858,10 @@ serdes0_usb_link: phy@0 { }; }; =20 +&serdes_wiz1 { + status =3D "okay"; +}; + &serdes1 { status =3D "okay"; serdes1_pcie_link: phy@0 { --=20 2.34.1 From nobody Fri Dec 19 20:28:17 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C971F267AF0; Tue, 8 Apr 2025 10:36:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744108590; cv=none; b=JEIZOi5xLkFi+a63pOhaKOL7TxHlnC4DSIRC2eZZuloslt1uxZiFaKL3fMe/HHMp+6qNTaIR2SbuqI2Pd2Z7KD/UaatLAeyjlRT0hwOSrqibWn1ZymTmmpWwm1qkp4vNmbsgtxlRnl+/CcrqplicB1z8Q41w3shzT3ALAocjH/E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744108590; c=relaxed/simple; bh=RrngJ5bh60xNJhc9TjEINQUJppKVEPMdTxIpBFnN13Y=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VnEtmpcygitJXfz9tPv169m06Nv0JTYOGG5FCs46EjWHjKJAAhV4j4/q24uZl8IyxUxknuXae9Z5dcxllehW0Ho5nIvcQy7bgcDYDzztVQX2+JDWhbg0erIk8KIfQfxIfW+gwBBJwWdC8mE2grA+n6ao94nYzVhkMNkKRwF0HbM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=XFZ62dW8; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="XFZ62dW8" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 538AaJOq655532 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 8 Apr 2025 05:36:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1744108579; bh=gtkeFnj7OUO0U4bnqYDUPhFLm3B9Pqw2DU045e21LFw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=XFZ62dW87X2NQzHQhPUVXfYGm5xqGL/cHTCRS7A07FvCznkHYnOFNXzrMykRWTI8F 10zxxAV3HOLmOrzOvQybFb9XSWERmWLJwLmJDafAzQpWoGEsu/TSZoaGRNNqjikr3z 4rWeAIP0DP4Sgg59Xb9R2lNrhwKvgjGrwMjdwHRU= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 538AaJYf079656 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 8 Apr 2025 05:36:19 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 8 Apr 2025 05:36:18 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 8 Apr 2025 05:36:18 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [10.24.72.113]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 538Aa6T9016171; Tue, 8 Apr 2025 05:36:15 -0500 From: Siddharth Vadapalli To: , , , , , , CC: , , , , , Subject: [PATCH v2 2/2] arm64: dts: ti: k3-j722s-main: Disable "serdes_wiz0" and "serdes_wiz1" Date: Tue, 8 Apr 2025 16:06:06 +0530 Message-ID: <20250408103606.3679505-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250408103606.3679505-1-s-vadapalli@ti.com> References: <20250408103606.3679505-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Since "serdes0" and "serdes1" which are the sub-nodes of "serdes_wiz0" and "serdes_wiz1" respectively, have been disabled in the SoC file already, and, given that these sub-nodes will only be enabled in a board file if the board utilizes any of the SERDES instances and the peripherals bound to them, we end up in a situation where the board file doesn't explicitly disable "serdes_wiz0" and "serdes_wiz1". As a consequence of this, the following errors show up when booting Linux: wiz bus@f0000:phy@f000000: probe with driver wiz failed with error -12 ... wiz bus@f0000:phy@f010000: probe with driver wiz failed with error -12 To not only fix the above, but also, in order to follow the convention of disabling device-tree nodes in the SoC file and enabling them in the board files for those boards which require them, disable "serdes_wiz0" and "serdes_wiz1" device-tree nodes. Fixes: 628e0a0118e6 ("arm64: dts: ti: k3-j722s-main: Add SERDES and PCIe su= pport") Cc: stable@vger.kernel.org Signed-off-by: Siddharth Vadapalli Reviewed-by: Udit Kumar --- v1 of this patch is at: https://lore.kernel.org/r/20250408060636.3413856-3-s-vadapalli@ti.com/ Changes since v1: - Added "Fixes" tag and updated commit message accordingly. Regards, Siddharth. arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-j722s-main.dtsi index 6850f50530f1..beda9e40e931 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi @@ -32,6 +32,8 @@ serdes_wiz0: phy@f000000 { assigned-clocks =3D <&k3_clks 279 1>; assigned-clock-parents =3D <&k3_clks 279 5>; =20 + status =3D "disabled"; + serdes0: serdes@f000000 { compatible =3D "ti,j721e-serdes-10g"; reg =3D <0x0f000000 0x00010000>; @@ -70,6 +72,8 @@ serdes_wiz1: phy@f010000 { assigned-clocks =3D <&k3_clks 280 1>; assigned-clock-parents =3D <&k3_clks 280 5>; =20 + status =3D "disabled"; + serdes1: serdes@f010000 { compatible =3D "ti,j721e-serdes-10g"; reg =3D <0x0f010000 0x00010000>; --=20 2.34.1