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Mon, 07 Apr 2025 22:02:36 -0700 (PDT) From: Inochi Amaoto To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, Yixun Lan , Longbin Li Subject: [PATCH v3 3/4] irqchip/sg2042-msi: introduce configurable chipinfo for sg2042 Date: Tue, 8 Apr 2025 13:01:44 +0800 Message-ID: <20250408050147.774987-4-inochiama@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250408050147.774987-1-inochiama@gmail.com> References: <20250408050147.774987-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As the controller on SG2044 uses different msi_parent_ops and irq_chip, it is necessary to add a structure to hold the configuration across controllers. Add the chipinfo structure and implement necessary logic for it. Signed-off-by: Inochi Amaoto --- drivers/irqchip/irq-sg2042-msi.c | 44 ++++++++++++++++++++++++++------ 1 file changed, 36 insertions(+), 8 deletions(-) diff --git a/drivers/irqchip/irq-sg2042-msi.c b/drivers/irqchip/irq-sg2042-= msi.c index c9bff7ba693d..30a1d2bfd474 100644 --- a/drivers/irqchip/irq-sg2042-msi.c +++ b/drivers/irqchip/irq-sg2042-msi.c @@ -21,16 +21,33 @@ =20 #define SG2042_MAX_MSI_VECTOR 32 =20 +struct sg204x_msi_chip_info { + const struct irq_chip *irqchip; + const struct msi_parent_ops *parent_ops; +}; + +/** + * struct sg204x_msi_chipdata - chip data for the SG204x MSI IRQ controller + * @reg_clr: clear reg, see TRM, 10.1.33, GP_INTR0_CLR + * @doorbell_addr: see TRM, 10.1.32, GP_INTR0_SET + * @irq_first: First vectors number that MSIs starts + * @num_irqs: Number of vectors for MSIs + * @msi_map: mapping for allocated MSI vectors. + * @msi_map_lock: Lock for msi_map + * @chip_info: chip specific infomations + */ struct sg204x_msi_chipdata { - void __iomem *reg_clr; // clear reg, see TRM, 10.1.33, GP_INTR0_CLR + void __iomem *reg_clr; =20 - phys_addr_t doorbell_addr; // see TRM, 10.1.32, GP_INTR0_SET + phys_addr_t doorbell_addr; =20 - u32 irq_first; // The vector number that MSIs starts - u32 num_irqs; // The number of vectors for MSIs + u32 irq_first; + u32 num_irqs; =20 DECLARE_BITMAP(msi_map, SG2042_MAX_MSI_VECTOR); - struct mutex msi_map_lock; // lock for msi_map + struct mutex msi_map_lock; + + const struct sg204x_msi_chip_info *chip_info; }; =20 static int sg204x_msi_allocate_hwirq(struct sg204x_msi_chipdata *data, int= num_req) @@ -115,7 +132,7 @@ static int sg204x_msi_middle_domain_alloc(struct irq_do= main *domain, unsigned in goto err_hwirq; =20 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, - &sg2042_msi_middle_irq_chip, data); + data->chip_info->irqchip, data); } =20 return 0; @@ -174,7 +191,7 @@ static int sg204x_msi_init_domains(struct sg204x_msi_ch= ipdata *data, irq_domain_update_bus_token(middle_domain, DOMAIN_BUS_NEXUS); =20 middle_domain->flags |=3D IRQ_DOMAIN_FLAG_MSI_PARENT; - middle_domain->msi_parent_ops =3D &sg2042_msi_parent_ops; + middle_domain->msi_parent_ops =3D data->chip_info->parent_ops; =20 return 0; } @@ -192,6 +209,12 @@ static int sg2042_msi_probe(struct platform_device *pd= ev) if (!data) return -ENOMEM; =20 + data->chip_info =3D device_get_match_data(&pdev->dev); + if (!data->chip_info) { + dev_err(&pdev->dev, "Failed to get irqchip\n"); + return -EINVAL; + } + data->reg_clr =3D devm_platform_ioremap_resource_byname(pdev, "clr"); if (IS_ERR(data->reg_clr)) { dev_err(dev, "Failed to map clear register\n"); @@ -235,8 +258,13 @@ static int sg2042_msi_probe(struct platform_device *pd= ev) return sg204x_msi_init_domains(data, plic_domain, dev); } =20 +static const struct sg204x_msi_chip_info sg2042_chip_info =3D { + .irqchip =3D &sg2042_msi_middle_irq_chip, + .parent_ops =3D &sg2042_msi_parent_ops, +}; + static const struct of_device_id sg2042_msi_of_match[] =3D { - { .compatible =3D "sophgo,sg2042-msi" }, + { .compatible =3D "sophgo,sg2042-msi", .data =3D &sg2042_chip_info }, { } }; =20 --=20 2.49.0