From nobody Fri Dec 19 17:09:41 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C1C12AEE3; Tue, 8 Apr 2025 03:32:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744083139; cv=none; b=Yps13q9+2ZIzOtTlQeA0y5BPVKdP7siPseaosnjPAHgx5cHvkTKyxJhsPtEA1/YXQY5FdF+CPjPHaJpH+d/VrLZFdqwHy3Apqv1HqChVaa5sqcCYiJzNxvzbaGOdex/PJ6cyDOA4ebedgDdExJ3HSva6VOYpaPZAKiWesezXoBM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744083139; c=relaxed/simple; bh=znhTw6gj8jkdlsxAicrfbO/x28zbFUm9gCFFotzNMkk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iUtBmFmTDj3yHejgDAbFsiNmvnF376Fr5MHa1Uxj/jhTGrob4Rq8Rd8/nZzdGadPiV3ZU1paFsfkQ9urtn4Soqmht2t44RsnIjmlnaLQ4sr3oFYB//vYrx3MAR3FcNeIRjVjhzxZsas55+e2Ny3nGJht7FJeWWjmnapPgb4bU6M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=pIzW8BlM; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="pIzW8BlM" X-UUID: 0f26b4fe142a11f0aae1fd9735fae912-20250408 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=I0RXQg/67CW5XIHlfH2JVGQV2RtfSqwW5CfapL5H23A=; b=pIzW8BlMn3tvM+gnQd7CzJ+G6NhqssiZZXNjouTqXNLfpw1WKxBC0CyrmiRKY9cpAzzqYxs0Sq2UrfYsYktx40f/Ix7RkOkOQ2ax0qhMtQ7VZwsPnr6Ykfax5FkhrYwjpHxDdoaWu8hzB835n8kVFwlPXhb5MCsMajh6ZaHCUUs=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1,REQID:94c56a44-5415-47a0-a411-1a345aa7ad7c,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:0ef645f,CLOUDID:e6b94cc7-16da-468a-87f7-8ca8d6b3b9f7,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 0f26b4fe142a11f0aae1fd9735fae912-20250408 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1272687449; Tue, 08 Apr 2025 11:32:12 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Tue, 8 Apr 2025 11:32:11 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Tue, 8 Apr 2025 11:32:10 +0800 From: Friday Yang To: Yong Wu , Krzysztof Kozlowski , "Rob Herring" , Conor Dooley , "Matthias Brugger" , AngeloGioacchino Del Regno , Philipp Zabel CC: Friday Yang , , , , , Subject: [PATCH v6 1/3] dt-bindings: memory: mediatek: Add SMI reset and clamp for MT8188 Date: Tue, 8 Apr 2025 11:31:54 +0800 Message-ID: <20250408033206.12176-2-friday.yang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250408033206.12176-1-friday.yang@mediatek.com> References: <20250408033206.12176-1-friday.yang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Friday Yang" Add 'resets' and 'reset-names' properties for SMI LARBs to support SMI reset operations. On the MediaTek platform, some SMI LARBs are directly connected to the SMI Common, while others are connected to the SMI Sub-Common, which in turn is connected to the SMI Common. The hardware block diagram can be described as follows. SMI-Common(Smart Multimedia Interface Common) | +----------------+------------------+ | | | | | | | | | | | | | | | larb0 SMI-Sub-Common0 SMI-Sub-Common1 | | | | | larb1 larb2 larb3 larb7 larb9 Signed-off-by: Friday Yang --- .../mediatek,smi-common.yaml | 2 ++ .../memory-controllers/mediatek,smi-larb.yaml | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,= smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/medi= atek,smi-common.yaml index 2f36ac23604c..4392d349878c 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-com= mon.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-com= mon.yaml @@ -39,6 +39,7 @@ properties: - mediatek,mt8186-smi-common - mediatek,mt8188-smi-common-vdo - mediatek,mt8188-smi-common-vpp + - mediatek,mt8188-smi-sub-common - mediatek,mt8192-smi-common - mediatek,mt8195-smi-common-vdo - mediatek,mt8195-smi-common-vpp @@ -107,6 +108,7 @@ allOf: compatible: contains: enum: + - mediatek,mt8188-smi-sub-common - mediatek,mt8195-smi-sub-common then: required: diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,= smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediat= ek,smi-larb.yaml index 2381660b324c..f4f0ed0f1fd9 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-lar= b.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-lar= b.yaml @@ -69,6 +69,12 @@ properties: description: the hardware id of this larb. It's only required when this hardware id is not consecutive from its M4U point of view. + resets: + maxItems: 1 + + reset-names: + const: larb + required: - compatible - reg @@ -125,6 +131,19 @@ allOf: required: - mediatek,larb-id + - if: # only for image, camera and ipe subsys + properties: + compatible: + const: mediatek,mt8188-smi-larb + mediatek,larb-id: + enum: + [ 9, 10, 11, 12, 13, 16, 17, 18, 19, 20 ] + + then: + required: + - resets + - reset-names + additionalProperties: false examples: -- 2.46.0 From nobody Fri Dec 19 17:09:41 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B1421A8F7F; Tue, 8 Apr 2025 03:32:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744083140; cv=none; b=bOw2Zo9PM7AhJJhlY6bxR5SrIlxJYgW26wmLw71jeBEQnUBFMREU+xf9vsr7n87qOr406xHXoMes5t2tYwHF0rJnTXxVzyDbVIvOLOg/1biSZoJDRQPhWJETTAWzI4IecfmiaHzRbDj2DmeqTrb/F6McxvChf1qWW5n8FLRSrS8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744083140; c=relaxed/simple; bh=zlsnS6VFNMs4OCSD9DhZZY1KmbVJ2cVLBCUsMbWFm98=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QLFawQXhzsTPx+bMeuOF56sjpY/POIkf1ekbF3MZltIx8vYG34wzGoHu83GStFp2synWAvI4Y36V3X8TC4p8fmuu3T+kqaESDGoFMh96NKqAf/9Mg5rTvFKikI9AlqwWp7N6JCK9Hk8PiYDw6+7W4E2DUO5TeGz1QEeZwJEH9R8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=SdxDgI1M; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="SdxDgI1M" X-UUID: 10242544142a11f08eb9c36241bbb6fb-20250408 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=+m0JgA6bHLhwO4HRyxMekuf7XmxtW340WxTgo+8WzB8=; b=SdxDgI1MXVavygRr2eO7QbAqYrxbn0DUdvM3TUYNtUh1PyWBMV3iQnMW0bweMuDWK6XsVnWi6ET+AyYcM6pgzZZfZFT/MumOsgm23euAqab7Uxverw7SSrVxD7EFNL+Kw+L6qmbhJunw2mEtE3ScPUvXr2UelCwVIqyvRFlnriY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1,REQID:18a7a57b-95b1-4ed8-a9e2-b018234b93e1,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:0ef645f,CLOUDID:d07a114b-a527-43d8-8af6-bc8b32d9f5e9,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 10242544142a11f08eb9c36241bbb6fb-20250408 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 869557259; Tue, 08 Apr 2025 11:32:14 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Tue, 8 Apr 2025 11:32:12 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Tue, 8 Apr 2025 11:32:12 +0800 From: Friday Yang To: Yong Wu , Krzysztof Kozlowski , Rob Herring , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel CC: Friday Yang , , , , , Subject: [PATCH v6 2/3] memory: mtk-smi: mt8188: Add SMI reset and clamp for MT8188 Date: Tue, 8 Apr 2025 11:31:55 +0800 Message-ID: <20250408033206.12176-3-friday.yang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250408033206.12176-1-friday.yang@mediatek.com> References: <20250408033206.12176-1-friday.yang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Friday Yang" To prevent handling glitch signals during MTCMOS on/off transitions, SMI requires clamp and reset operations. Parse the reset settings for SMI LARBs and the clamp settings for the SMI Sub-Common. Register genpd callback for the SMI LARBs located in image, camera and IPE subsystems, and apply reset and clamp operations within the callback. Signed-off-by: Friday Yang --- drivers/memory/mtk-smi.c | 134 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index a8f5467d6b31..f25d46d2ef33 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -10,11 +10,15 @@ #include #include #include +#include #include #include #include #include +#include #include +#include +#include #include #include #include @@ -36,6 +40,12 @@ #define SMI_DCM 0x300 #define SMI_DUMMY 0x444 +#define SMI_COMMON_CLAMP_EN 0x3c0 +#define SMI_COMMON_CLAMP_EN_SET 0x3c4 +#define SMI_COMMON_CLAMP_EN_CLR 0x3c8 + +#define SMI_SUB_COMM_INPORT_NR (8) + /* SMI LARB */ #define SMI_LARB_SLP_CON 0xc #define SLP_PROT_EN BIT(0) @@ -134,6 +144,7 @@ struct mtk_smi_larb_gen { unsigned int larb_direct_to_common_mask; unsigned int flags_general; const u8 (*ostd)[SMI_LARB_PORT_NR_MAX]; + const u8 *clamp_port; }; struct mtk_smi { @@ -150,6 +161,7 @@ struct mtk_smi { }; struct mtk_smi_larb { /* larb: local arbiter */ + struct device *dev; struct mtk_smi smi; void __iomem *base; struct device *smi_common_dev; /* common or sub-common dev */ @@ -157,6 +169,10 @@ struct mtk_smi_larb { /* larb: local arbiter */ int larbid; u32 *mmu; unsigned char *bank; + struct regmap *sub_comm_syscon; + u8 sub_comm_inport; + struct notifier_block nb; + struct reset_control *rst_con; }; static int @@ -409,6 +425,19 @@ static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PO= RT_NR_MAX] =3D { [28] =3D {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, }; +static const u8 mtk_smi_larb_clamp_port_mt8188[MTK_LARB_NR_MAX] =3D { + [9] =3D BIT(1), /* larb10 */ + [10] =3D BIT(2), /* larb11a */ + [11] =3D BIT(2), /* larb11b */ + [12] =3D BIT(3), /* larb11c */ + [13] =3D BIT(0), /* larb12 */ + [16] =3D BIT(1), /* larb15 */ + [17] =3D BIT(2), /* larb16a */ + [18] =3D BIT(2), /* larb16b */ + [19] =3D BIT(3), /* larb17a */ + [20] =3D BIT(3), /* larb17b */ +}; + static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 =3D { .port_in_larb =3D { LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, @@ -455,6 +484,7 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt818= 8 =3D { .flags_general =3D MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW= _FLAG | MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CFG_PORT_SEC_CTL, .ostd =3D mtk_smi_larb_mt8188_ostd, + .clamp_port =3D mtk_smi_larb_clamp_port_mt8188, }; static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 =3D { @@ -505,6 +535,46 @@ static void mtk_smi_larb_sleep_ctrl_disable(struct mtk= _smi_larb *larb) writel_relaxed(0, larb->base + SMI_LARB_SLP_CON); } +static int mtk_smi_larb_clamp_protect_enable(struct device *dev, bool enab= le) +{ + struct mtk_smi_larb *larb =3D dev_get_drvdata(dev); + u32 reg; + int ret; + + /* sub_comm_syscon could be NULL if larb directly linked to SMI common */ + if (!larb->sub_comm_syscon) + return -EINVAL; + + reg =3D enable ? SMI_COMMON_CLAMP_EN_SET : SMI_COMMON_CLAMP_EN_CLR; + + ret =3D regmap_write(larb->sub_comm_syscon, reg, + larb->sub_comm_inport); + if (ret) + dev_err(dev, "Unable to %s clamp for input port %d: %d\n", + enable ? "enable" : "disable", + larb->sub_comm_inport, ret); + + return ret; +} + +static int mtk_smi_genpd_callback(struct notifier_block *nb, + unsigned long flags, void *data) +{ + struct mtk_smi_larb *larb =3D container_of(nb, struct mtk_smi_larb, nb); + struct device *dev =3D larb->dev; + + if (flags =3D=3D GENPD_NOTIFY_PRE_ON || flags =3D=3D GENPD_NOTIFY_PRE_OFF= ) { + /* disable related SMI sub-common port */ + mtk_smi_larb_clamp_protect_enable(dev, true); + } else if (flags =3D=3D GENPD_NOTIFY_ON) { + /* enable related SMI sub-common port */ + reset_control_reset(larb->rst_con); + mtk_smi_larb_clamp_protect_enable(dev, false); + } + + return NOTIFY_OK; +} + static int mtk_smi_device_link_common(struct device *dev, struct device **= com_dev) { struct platform_device *smi_com_pdev; @@ -561,6 +631,53 @@ static int mtk_smi_dts_clk_init(struct device *dev, st= ruct mtk_smi *smi, return ret; } +static int mtk_smi_larb_parse_clamp_optional(struct mtk_smi_larb *larb) +{ + struct device *dev =3D larb->dev; + const struct mtk_smi_larb_gen *larb_gen =3D larb->larb_gen; + u32 larb_id; + int ret; + + /* + * Only SMI LARBs in camera, image and IPE subsys need to + * apply clamp and reset operations, others can be skipped. + */ + ret =3D of_property_read_u32(dev->of_node, "mediatek,larb-id", &larb_id); + if (ret) + return -EINVAL; + if (!larb_gen->clamp_port || !larb_gen->clamp_port[larb_id]) + return 0; + + larb->sub_comm_inport =3D larb_gen->clamp_port[larb_id]; + larb->sub_comm_syscon =3D syscon_regmap_lookup_by_phandle(dev->of_node, + "mediatek,smi"); + if (IS_ERR(larb->sub_comm_syscon)) { + larb->sub_comm_syscon =3D NULL; + return dev_err_probe(dev, -EINVAL, + "Unknown clamp port for larb %d\n", larb_id); + } + + return 0; +} + +static int mtk_smi_larb_parse_reset_optional(struct mtk_smi_larb *larb) +{ + struct device *dev =3D larb->dev; + int ret; + + larb->rst_con =3D devm_reset_control_get_optional_exclusive(dev, "larb"); + if (!larb->rst_con) + return 0; + + larb->nb.notifier_call =3D mtk_smi_genpd_callback; + ret =3D dev_pm_genpd_add_notifier(dev, &larb->nb); + if (ret) + return dev_err_probe(dev, -EINVAL, + "Failed to add genpd callback %d\n", ret); + + return 0; +} + static int mtk_smi_larb_probe(struct platform_device *pdev) { struct mtk_smi_larb *larb; @@ -571,6 +688,7 @@ static int mtk_smi_larb_probe(struct platform_device *p= dev) if (!larb) return -ENOMEM; + larb->dev =3D dev; larb->larb_gen =3D of_device_get_match_data(dev); larb->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(larb->base)) @@ -587,15 +705,25 @@ static int mtk_smi_larb_probe(struct platform_device = *pdev) if (ret < 0) return ret; + ret =3D mtk_smi_larb_parse_clamp_optional(larb); + if (ret) + goto err_link_remove; + + ret =3D mtk_smi_larb_parse_reset_optional(larb); + if (ret) + goto err_link_remove; + pm_runtime_enable(dev); platform_set_drvdata(pdev, larb); ret =3D component_add(dev, &mtk_smi_larb_component_ops); if (ret) goto err_pm_disable; return 0; err_pm_disable: pm_runtime_disable(dev); +err_link_remove: device_link_remove(dev, larb->smi_common_dev); return ret; } @@ -719,6 +847,11 @@ static const struct mtk_smi_common_plat mtk_smi_common= _mt8188_vpp =3D { .init =3D mtk_smi_common_mt8195_init, }; +static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8188 =3D { + .type =3D MTK_SMI_GEN2_SUB_COMM, + .has_gals =3D true, +}; + static const struct mtk_smi_common_plat mtk_smi_common_mt8192 =3D { .type =3D MTK_SMI_GEN2, .has_gals =3D true, @@ -762,6 +895,7 @@ static const struct of_device_id mtk_smi_common_of_ids[= ] =3D { {.compatible =3D "mediatek,mt8186-smi-common", .data =3D &mtk_smi_common_= mt8186}, {.compatible =3D "mediatek,mt8188-smi-common-vdo", .data =3D &mtk_smi_com= mon_mt8188_vdo}, {.compatible =3D "mediatek,mt8188-smi-common-vpp", .data =3D &mtk_smi_com= mon_mt8188_vpp}, + {.compatible =3D "mediatek,mt8188-smi-sub-common", .data =3D &mtk_smi_sub= _common_mt8188}, {.compatible =3D "mediatek,mt8192-smi-common", .data =3D &mtk_smi_common_= mt8192}, {.compatible =3D "mediatek,mt8195-smi-common-vdo", .data =3D &mtk_smi_com= mon_mt8195_vdo}, {.compatible =3D "mediatek,mt8195-smi-common-vpp", .data =3D &mtk_smi_com= mon_mt8195_vpp}, -- 2.46.0 From nobody Fri Dec 19 17:09:41 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4928B25F98B; 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charset="utf-8" Replace pm_runtime_enable with the devres-enabled version which can trigger pm_runtime_disable. Signed-off-by: Friday Yang --- drivers/memory/mtk-smi.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c index f25d46d2ef33..daef6d350419 100644 --- a/drivers/memory/mtk-smi.c +++ b/drivers/memory/mtk-smi.c @@ -713,16 +713,17 @@ static int mtk_smi_larb_probe(struct platform_device = *pdev) if (ret) goto err_link_remove; - pm_runtime_enable(dev); + ret =3D devm_pm_runtime_enable(dev); + if (ret) + goto err_link_remove; + platform_set_drvdata(pdev, larb); ret =3D component_add(dev, &mtk_smi_larb_component_ops); if (ret) - goto err_pm_disable; + goto err_link_remove; return 0; -err_pm_disable: - pm_runtime_disable(dev); err_link_remove: device_link_remove(dev, larb->smi_common_dev); return ret; @@ -733,7 +734,6 @@ static void mtk_smi_larb_remove(struct platform_device = *pdev) struct mtk_smi_larb *larb =3D platform_get_drvdata(pdev); device_link_remove(&pdev->dev, larb->smi_common_dev); - pm_runtime_disable(&pdev->dev); component_del(&pdev->dev, &mtk_smi_larb_component_ops); } @@ -954,7 +954,10 @@ static int mtk_smi_common_probe(struct platform_device= *pdev) return ret; } - pm_runtime_enable(dev); + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + platform_set_drvdata(pdev, common); return 0; } @@ -965,7 +968,6 @@ static void mtk_smi_common_remove(struct platform_devic= e *pdev) if (common->plat->type =3D=3D MTK_SMI_GEN2_SUB_COMM) device_link_remove(&pdev->dev, common->smi_common_dev); - pm_runtime_disable(&pdev->dev); } static int __maybe_unused mtk_smi_common_resume(struct device *dev) -- 2.46.0