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Tue, 08 Apr 2025 02:33:03 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 08 Apr 2025 11:32:17 +0200 Subject: [PATCH v2 20/24] arm64: dts: qcom: sm8250: Use the header with DSI phy clock IDs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250408-dts-qcom-dsi-phy-clocks-v2-20-73b482a6dd02@linaro.org> References: <20250408-dts-qcom-dsi-phy-clocks-v2-0-73b482a6dd02@linaro.org> In-Reply-To: <20250408-dts-qcom-dsi-phy-clocks-v2-0-73b482a6dd02@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Krzysztof Kozlowski , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3506; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=omkn3m7HWR7M8yA3Wy2SKdjKBChDLn4G9csmN/Npsmg=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBn9O0nKsnrVWZzBEisFbEkzVk7Dwfx+5aBJmVyA cICw/KgXpWJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ/TtJwAKCRDBN2bmhouD 125sD/9W9jxNwTVpd7nBVeoMBxDwN/ldcSOJA7n7Y9hThPwHeCqPAn6tnQUVjfa5PwXWukWypTG V8dH6e//1ZQFU3gCDUftAvschpaZzqFdRKQZycHCnC+bp2Oyyd8otMZsbbp16sAloW65B/+6V42 j40lPic2ZqYsizWSNfycfKbnZbohk55PcU7QHHauQDqR4QOjP32ajER/vOMaG+F6Tu6kHBt8kRF VRr4mNqQ+BBBDqwG398G3RIwsL4huBp1UjGZ5/GAjuMsWY37WUTkPvm3Ol9jQ+Fe2zmLp/vfcY0 LUVJLWuvSS2O9xn8bIlEzNQpZQQC5P4aLtT8JZCc3JxVWe8pvKTQQyPGqIlvoyXfjWeOhb8xfOg 4XH6ahUFQd8bfogSzy/A5s66sw4ioMOzrgA2tzHVrs+kch3ULwmkgbRxJUQqFOxVY7IAehuYBFm izPBR0suv+2CIZPhyd79Kwg9LIkszZTeSq8okAyCjkkEr9LbUH0pVZ1tB/A406HtbBF9aSGRRlT CuJAlIOXz+ZtZM2jfu5f3XEl0JfBhY3Eo52kNN0IhS6rLB58ZfN0pyt+/RjerHhUjrBkNu1mU0f /yt8182YvTtPfYsurc94jKS+GDSCdCKt2LUq8Ag1JtI1iFuz0hRI42UwZFRwVhARoXFUEQ/gZkl o/kWOf94uddXWwA== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi | 3 ++- arch/arm64/boot/dts/qcom/sm8250.dtsi | 21 +++++++++++++----= ---- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi b/arc= h/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi index 01a321d801af3389258abd54e60c39272c59fb7e..465fd6e954a347acf15ef3199af= d8d1a198f95e8 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-common.dtsi @@ -659,7 +659,8 @@ &mdss_dsi1 { qcom,dual-dsi-mode; qcom,sync-dual-dsi; /* DSI1 is slave, so use DSI0 clocks */ - assigned-clock-parents =3D <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; status =3D "okay"; }; =20 diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qco= m/sm8250.dtsi index 68613ea7146c8882150f1b81dbc0f3384d3380ba..0425e14840c6a299aa49e82ef50= 10fc9ac090296 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include #include @@ -4861,8 +4862,10 @@ mdss_dsi0: dsi@ae94000 { "iface", "bus"; =20 - assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DIS= P_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents =3D <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; =20 operating-points-v2 =3D <&dsi_opp_table>; power-domains =3D <&rpmhpd RPMHPD_MMCX>; @@ -4953,8 +4956,10 @@ mdss_dsi1: dsi@ae96000 { "iface", "bus"; =20 - assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DIS= P_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents =3D <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; =20 operating-points-v2 =3D <&dsi_opp_table>; power-domains =3D <&rpmhpd RPMHPD_MMCX>; @@ -5011,10 +5016,10 @@ dispcc: clock-controller@af00000 { power-domains =3D <&rpmhpd RPMHPD_MMCX>; required-opps =3D <&rpmhpd_opp_low_svs>; clocks =3D <&rpmhcc RPMH_CXO_CLK>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; clock-names =3D "bi_tcxo", --=20 2.45.2