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Tue, 08 Apr 2025 02:33:01 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 08 Apr 2025 11:32:16 +0200 Subject: [PATCH v2 19/24] arm64: dts: qcom: sm8150: Use the header with DSI phy clock IDs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250408-dts-qcom-dsi-phy-clocks-v2-19-73b482a6dd02@linaro.org> References: <20250408-dts-qcom-dsi-phy-clocks-v2-0-73b482a6dd02@linaro.org> In-Reply-To: <20250408-dts-qcom-dsi-phy-clocks-v2-0-73b482a6dd02@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , cros-qcom-dts-watchers@chromium.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Krzysztof Kozlowski , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3152; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=39k1vMZOSN1FgOQwMGT7xFm121EqUSXE/MevpdIOhnQ=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBn9O0mDlXJanAZda1ObES7b5BtrdFsfnFDjjwEU K4umi231p+JAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ/TtJgAKCRDBN2bmhouD 15GtD/0YwrTy6y+fmM577d4lKjwXOJqGpjG2E8vf6LCRr+NAWG1ToDof9TBcbxNtmY+j1HOFm5X jEw9jfVvETirmVyEk+ina7S3lG5w9or22L93buc8dd6ycebF84E2RPXMFey6O3WWZr2LYZXM4UN v9eo+YVG+E1cwBx0Mp4zMWq0TtfRGHGlhMWYiECKaav0s/zRg7qzdvzVx0kr9T0b0ufWi3DK/c3 btxN6FrJXgZK+4VkQO3bW9MkMfVTPQfgXwCYnko0mfYgAS6QkaOm+hlAD/0HDVRDSFm19F+Gsb+ 8mTJ7JOaIsEFKBOsHlJkjT3gyvhybeMCU8qwRE9qIMIQUhcW9rG1kp1yTX9S9Ps8cd5HeOH//e3 q7UwDM+qEFSvrKuqyWsnfag46tMkZgw0AxlHXh8nfFoJjsf9an+lgzmFEgsnij1oIFDLc1F0GJt PJlvAkqxpiqKAD/f6XTleGVNTAFbfGSGv+5wwkiZ2ft9EOTXKUuK0QXWoDBy81tbdy1XCVrqWOk RCknBTaxP77GBnCDEu4LHPVAiWbTYvW3W7DJWVm7JQ22ttbEeZk4ngFPgrWdeF9nbbM2oG29oo8 w1QEcSyqb+/Jo8FnKAiciW3FStFAFQZDD8vcfEFLMa9w2Y2gSTse9YADnluew53ZtoPCGgjWkGH esnR+Nn8iaGu12g== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Use the header with DSI phy clock IDs to make code more readable. Reviewed-by: Dmitry Baryshkov Reviewed-by: Neil Armstrong Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 3 ++- arch/arm64/boot/dts/qcom/sm8150.dtsi | 17 +++++++++-------- 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8150-hdk.dts index 9ac9854b35fd157e0735aaff4e0bdbaa8946e0d5..e1e294f0f462ac824bffe96615b= 36ddcd8996d80 100644 --- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts @@ -500,7 +500,8 @@ &mdss_dsi1 { qcom,dual-dsi-mode; =20 /* DSI1 is slave, so use DSI0 clocks */ - assigned-clock-parents =3D <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; =20 status =3D "okay"; =20 diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qco= m/sm8150.dtsi index 4dbda54b47a54d1fa9c3fbeb441f8bc852e52f75..2aca3fdae47ceef9b3030613ec2= b8f3a6c1a3356 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -3981,8 +3982,8 @@ mdss_dsi0: dsi@ae94000 { =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents =3D <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; =20 operating-points-v2 =3D <&dsi_opp_table>; power-domains =3D <&rpmhpd SM8150_MMCX>; @@ -4074,8 +4075,8 @@ mdss_dsi1: dsi@ae96000 { =20 assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; - assigned-clock-parents =3D <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>; + assigned-clock-parents =3D <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; =20 operating-points-v2 =3D <&dsi_opp_table>; power-domains =3D <&rpmhpd SM8150_MMCX>; @@ -4130,10 +4131,10 @@ dispcc: clock-controller@af00000 { compatible =3D "qcom,sm8150-dispcc"; reg =3D <0 0x0af00000 0 0x10000>; clocks =3D <&rpmhcc RPMH_CXO_CLK>, - <&mdss_dsi0_phy 0>, - <&mdss_dsi0_phy 1>, - <&mdss_dsi1_phy 0>, - <&mdss_dsi1_phy 1>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, + <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; clock-names =3D "bi_tcxo", --=20 2.45.2