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[2001:14ba:a0c3:3a00:264b:feff:fe8b:be8a]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-54c1e670d1bsm1560613e87.214.2025.04.08.06.02.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Apr 2025 06:02:46 -0700 (PDT) From: Dmitry Baryshkov Date: Tue, 08 Apr 2025 16:02:44 +0300 Subject: [PATCH] drm/msm/dpu: drop rogue intr_tear_rd_ptr values Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250408-dpu-drop-intr-rd-ptr-v1-1-eeac337d88f8@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAHMe9WcC/x2MQQqAIBAAvxJ7bkElK/pKdKjcai8qa0Ug/T3pN MxhJkMiYUowVBmEbk4cfBFdV7Aes98J2RUHo4xVjerRxQudhIjsT0FxGAu6drGm0e2qjYWSRqG Nn387Tu/7Ae5Oh7tmAAAA X-Change-ID: 20250408-dpu-drop-intr-rd-ptr-76b52416c125 To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8183; i=dmitry.baryshkov@oss.qualcomm.com; h=from:subject:message-id; bh=JdlMXxUwizN2ti92XXyxVJFjwtOn6Nq4gI0Xlewt8tI=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBn9R50D8d8SZ21NDKudMR43W7rVbh+XQ/JeL46E rTpKwT/QwOJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ/UedAAKCRCLPIo+Aiko 1TBAB/9CG/SR1t4i7Zbc+3thhGxKeEe1SkmXyismu5gPfIWoRcjUOkzRJRDqJHynfQRE5ujp9Tb rsKr28RJPLvgHJjHVU2fy2eHDVBL/0Ef6+nfwQhd+FnXvr6fx8Ccdha2/1t6rR61NLn0+K0l12O g0FUDyCblRJeM90M6KFVcDZreLRx1ym+I1g693JRWhpLwEvwdA3E888oa1KU6WCCIMP2/F6rHvf P5xWunufE4HbFzgCEfQK5n+3hpokY906G9NsZeFm50qsFO5sQIZ+vDQI+r0ao0h1MDKfVq6+csS sa9VQffKBsgBuoMt/4AtYS8HNL6Py0dhfujMIifTyPhLdVSh X-Developer-Key: i=dmitry.baryshkov@oss.qualcomm.com; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A X-Authority-Analysis: v=2.4 cv=B5+50PtM c=1 sm=1 tr=0 ts=67f51e79 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=XR8D0OoHHMoA:10 a=EUspDBNiAAAA:8 a=ZZee45BDSTTCXVxweLkA:9 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-GUID: yZdQF1Unru-htCH74Zxmo5OU9o02FY0T X-Proofpoint-ORIG-GUID: yZdQF1Unru-htCH74Zxmo5OU9o02FY0T X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-08_05,2025-04-08_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 suspectscore=0 malwarescore=0 bulkscore=0 phishscore=0 spamscore=0 priorityscore=1501 adultscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504080092 The commit 5a9d50150c2c ("drm/msm/dpu: shift IRQ indices by 1") shifted IRQ indices by 1, making 'NO_IRQ' to be 0 rather than -1 (and allowing to skip the definition if the IRQ is not present). Several platform files were sketched before that commit, but got applied afterwards. As such, they inherited historical (and currently incorrect) setting of .intr_tear_rd_ptr =3D -1 for 'NO_IRQ' value. Drop that setting for all the affected platforms. Fixes: 62af6e1cb596 ("drm/msm/dpu: Add support for MSM8917") Fixes: c079680bb0fa ("drm/msm/dpu: Add support for MSM8937") Fixes: 7a6109ce1c2c ("drm/msm/dpu: Add support for MSM8953") Fixes: daf9a92daeb8 ("drm/msm/dpu: Add support for MSM8996") Fixes: 7204df5e7e68 ("drm/msm/dpu: add support for SDM660 and SDM630 platfo= rms") Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h | 2 -- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h | 1 - drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 3 --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 2 -- 6 files changed, 15 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h index 1f32807bb5e5d49b696832c4eab54c05106bfd4b..ad60089f18ea6c22160533874ea= 0cc54c352e064 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_14_msm8937.h @@ -132,7 +132,6 @@ static const struct dpu_intf_cfg msm8937_intf[] =3D { .prog_fetch_lines_worst_case =3D 14, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr =3D -1, }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x6b000, .len =3D 0x268, @@ -141,7 +140,6 @@ static const struct dpu_intf_cfg msm8937_intf[] =3D { .prog_fetch_lines_worst_case =3D 14, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - .intr_tear_rd_ptr =3D -1, }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h index 42131959ff22020a83c0ea65d79a56fd57c800f9..a1cf89a0a42d5f3c909798c3090= 1fe8796b15075 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_15_msm8917.h @@ -118,7 +118,6 @@ static const struct dpu_intf_cfg msm8917_intf[] =3D { .prog_fetch_lines_worst_case =3D 14, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr =3D -1, }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h index 2b4723a5c67606d68dea905d947cd691bb28eda0..eea9b80e2287a86448ab4e1a591= 4c1914d5a2090 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_16_msm8953.h @@ -131,7 +131,6 @@ static const struct dpu_intf_cfg msm8953_intf[] =3D { .prog_fetch_lines_worst_case =3D 14, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), - .intr_tear_rd_ptr =3D -1, }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x6a800, .len =3D 0x268, @@ -140,7 +139,6 @@ static const struct dpu_intf_cfg msm8953_intf[] =3D { .prog_fetch_lines_worst_case =3D 14, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr =3D -1, }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x6b000, .len =3D 0x268, @@ -149,7 +147,6 @@ static const struct dpu_intf_cfg msm8953_intf[] =3D { .prog_fetch_lines_worst_case =3D 14, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - .intr_tear_rd_ptr =3D -1, }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h index 5cf19de71f060818d257f95aa781b91ec201d4e4..ae18a354e5d2a3d2e073f2099e4= d970bff5ed085 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h @@ -241,7 +241,6 @@ static const struct dpu_intf_cfg msm8996_intf[] =3D { .prog_fetch_lines_worst_case =3D 25, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), - .intr_tear_rd_ptr =3D -1, }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x6a800, .len =3D 0x268, @@ -250,7 +249,6 @@ static const struct dpu_intf_cfg msm8996_intf[] =3D { .prog_fetch_lines_worst_case =3D 25, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr =3D -1, }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x6b000, .len =3D 0x268, @@ -259,7 +257,6 @@ static const struct dpu_intf_cfg msm8996_intf[] =3D { .prog_fetch_lines_worst_case =3D 25, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - .intr_tear_rd_ptr =3D -1, }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x6b800, .len =3D 0x268, @@ -267,7 +264,6 @@ static const struct dpu_intf_cfg msm8996_intf[] =3D { .prog_fetch_lines_worst_case =3D 25, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), - .intr_tear_rd_ptr =3D -1, }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h index 4f2f68b07f203a11529f7a680fb87b448305d80a..bb89da0a481dec053e06369dee8= b0854a3427aaf 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -202,7 +202,6 @@ static const struct dpu_intf_cfg sdm660_intf[] =3D { .prog_fetch_lines_worst_case =3D 21, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), - .intr_tear_rd_ptr =3D -1, }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x6a800, .len =3D 0x280, @@ -211,7 +210,6 @@ static const struct dpu_intf_cfg sdm660_intf[] =3D { .prog_fetch_lines_worst_case =3D 21, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr =3D -1, }, { .name =3D "intf_2", .id =3D INTF_2, .base =3D 0x6b000, .len =3D 0x280, @@ -220,7 +218,6 @@ static const struct dpu_intf_cfg sdm660_intf[] =3D { .prog_fetch_lines_worst_case =3D 21, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), - .intr_tear_rd_ptr =3D -1, }, }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h index c70bef025ac4190347f81d75caf4777786fbeaf7..7caf876ca3e30cc9230cbc6f19b= 9d3d1b954e2e0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -147,7 +147,6 @@ static const struct dpu_intf_cfg sdm630_intf[] =3D { .prog_fetch_lines_worst_case =3D 21, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), - .intr_tear_rd_ptr =3D -1, }, { .name =3D "intf_1", .id =3D INTF_1, .base =3D 0x6a800, .len =3D 0x280, @@ -156,7 +155,6 @@ static const struct dpu_intf_cfg sdm630_intf[] =3D { .prog_fetch_lines_worst_case =3D 21, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), - .intr_tear_rd_ptr =3D -1, }, }; =20 --- base-commit: 2bdde620f7f2bff2ff1cb7dc166859eaa0c78a7c change-id: 20250408-dpu-drop-intr-rd-ptr-76b52416c125 Best regards, --=20 Dmitry Baryshkov