From nobody Mon Feb 9 05:00:09 2026 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13DBD26982D for ; Tue, 8 Apr 2025 12:00:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744113648; cv=none; b=D/h3OLx3Pr+Ouk4rjvuYLzZO2yshBFspx23kCvAZ+oqKe/1+wWTT+zi1YrNU3TVdIGsMjWTl8eB4qz1Tc+hlIKSBvXBIh4fd5X+WW7V9nxKPXxE9LsCrfrxjmifVKjcdrWx6f1pJ8293PecgR8T8bkk7ZL3o5AlwENY4OCD5UsE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744113648; c=relaxed/simple; bh=N2EUklR/z9JFHYu0b2d1/TXgABpe7LjJhfgZXh/GMyc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GARreTal1ucr5cSmyNSmJ8nG5k6BFn6dnJigW26rUwQKBrv9LnutxvZQsrLnoeqpW9zmg3NwNwKcz9LD16lpCnGJ+FjRNavk1FlHuCHNLKqpDBChenWVoEJSMhzSZtPD6/tkYcUGOL37cRxTMlRINJCl5pw8EogeT2j7LyHh0zk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1u27d0-0000jq-Eg; Tue, 08 Apr 2025 14:00:30 +0200 Received: from dude02.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::28]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1u27d0-003vQ0-0A; Tue, 08 Apr 2025 14:00:30 +0200 Received: from localhost ([::1] helo=dude02.red.stw.pengutronix.de) by dude02.red.stw.pengutronix.de with esmtp (Exim 4.96) (envelope-from ) id 1u27cz-00GJS1-35; Tue, 08 Apr 2025 14:00:29 +0200 From: Sascha Hauer Date: Tue, 08 Apr 2025 14:00:22 +0200 Subject: [PATCH 1/3] clk: make determine_rate optional for non reparenting clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250408-clk-cdce6214-v1-1-bd4e7092a91f@pengutronix.de> References: <20250408-clk-cdce6214-v1-0-bd4e7092a91f@pengutronix.de> In-Reply-To: <20250408-clk-cdce6214-v1-0-bd4e7092a91f@pengutronix.de> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kernel@pengutronix.de, =?utf-8?q?Alvin_=C5=A0ipraga?= , Sascha Hauer X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1744113629; l=1101; i=s.hauer@pengutronix.de; s=20230412; h=from:subject:message-id; bh=N2EUklR/z9JFHYu0b2d1/TXgABpe7LjJhfgZXh/GMyc=; b=OyyNnA4+AWF+wadTy8EM47z/bGUEFtNJi+4ZkN368kkdNEt8nF3sZvzMqrD6ixkfKkaXCcBao 8d8OpNU19ItDy5Lvmgn5ohnOqvF58GxuMKbuVXgxnMo6h5TeWQ8tuM1 X-Developer-Key: i=s.hauer@pengutronix.de; a=ed25519; pk=4kuc9ocmECiBJKWxYgqyhtZOHj5AWi7+d0n/UjhkwTg= X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: s.hauer@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org With 326cc42f9fdc ("clk: Forbid to register a mux without determine_rate") it became mandatory to provide a determine_rate hook once a set_parent hook is provided. The determine_rate hook is only needed though when the clock reparents to set its rate. Clocks which do not reparent during set_rate do not need a determine_rate hook, so make the hook optional for clocks with the CLK_SET_RATE_NO_REPARENT flag. Signed-off-by: Sascha Hauer --- drivers/clk/clk.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 0565c87656cf5..07ae3652df6c1 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -3937,7 +3937,8 @@ static int __clk_core_init(struct clk_core *core) goto out; } =20 - if (core->ops->set_parent && !core->ops->determine_rate) { + if (!(core->flags & CLK_SET_RATE_NO_REPARENT) && + core->ops->set_parent && !core->ops->determine_rate) { pr_err("%s: %s must implement .set_parent & .determine_rate\n", __func__, core->name); ret =3D -EINVAL; --=20 2.39.5 From nobody Mon Feb 9 05:00:09 2026 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74DEC3AC1C for ; Tue, 8 Apr 2025 12:00:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744113649; cv=none; b=S3VAOYe9UFz7eTXuaYI8h/cfi7mxD7DnLBumjtzYmhwTYeNJAYctTLji8xIYxRpCMyMcQkBW8NbNpmdox403yMMpZDbq3jC4FcejM7ui5LY6d37nJDWeE/NXrW5k6Sh1Xe7XJocnWV9EI9MtgOvN1URawS0igOqbxQDmBF3zj4M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744113649; c=relaxed/simple; bh=SNmgf6M8WFqn6ocasuCuHmlE7wB50v8uTyy6VtweTRE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SrbTy6VBuCcsrPnOQb7XOcm2jhtez5xK0u+rNSXzUHhA5F8y1Npyms4C2DJ88jaMuii3Zq36NFvEXH6jowJYpyYf7N5WTmCO8d8MkTRyVLATVpus3Wfwogoevz4e2r0Dap2GKqED3kG291oW6Hmgf/pwNDQYST6g4K4e4TGA9X4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1u27d0-0000jr-Eg; Tue, 08 Apr 2025 14:00:30 +0200 Received: from dude02.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::28]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1u27d0-003vQ1-0D; Tue, 08 Apr 2025 14:00:30 +0200 Received: from localhost ([::1] helo=dude02.red.stw.pengutronix.de) by dude02.red.stw.pengutronix.de with esmtp (Exim 4.96) (envelope-from ) id 1u27cz-00GJS1-37; Tue, 08 Apr 2025 14:00:29 +0200 From: Sascha Hauer Date: Tue, 08 Apr 2025 14:00:23 +0200 Subject: [PATCH 2/3] clk: add TI CDCE6214 clock driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250408-clk-cdce6214-v1-2-bd4e7092a91f@pengutronix.de> References: <20250408-clk-cdce6214-v1-0-bd4e7092a91f@pengutronix.de> In-Reply-To: <20250408-clk-cdce6214-v1-0-bd4e7092a91f@pengutronix.de> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kernel@pengutronix.de, =?utf-8?q?Alvin_=C5=A0ipraga?= , Sascha Hauer X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1744113629; l=34175; i=s.hauer@pengutronix.de; s=20230412; h=from:subject:message-id; bh=SNmgf6M8WFqn6ocasuCuHmlE7wB50v8uTyy6VtweTRE=; b=uMWfyqzuO/ut+z8W4+dvBIcFTCBYIv63R6aRNhPCY7tdKCSSbGy8JVfB32JL6gxfU3rx3zzwR XlNzmaFZuLVB9I0NfTNnrrWhZKvaeSay+jz8WJX74xTjzv/lEUjqfM7 X-Developer-Key: i=s.hauer@pengutronix.de; a=ed25519; pk=4kuc9ocmECiBJKWxYgqyhtZOHj5AWi7+d0n/UjhkwTg= X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: s.hauer@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org The CDCE6214 is a Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM. This patch adds a common clk framework driver for this chip. - Two inputs (PRIREF and SECREF) - Programmable 8bit divider or x2 multiplier between input and PLL - 16b integer / 24bit fractional PLL - Two programmable /4, /5, /6 dividers after PLL (PSA/PSB) - Four outputs (OUT1-OUT4) with programmable 14b dividers, muxable between PSA, PSB and PLL input - One output (OUT0) fed from PLL input - PRIREF can be configured as LVCMOS or differential input - SECREF can be configured as LVCMOS, differential or oscillator input - OUT0 is a LVCMOS output - OUT1 and OUT4 can be configured as LVDS, LP-HCSL or LVCMOS outputs - OUT2 and OUT3 can be configured as LVDS or LP-HCSL outputs All clocks are registered without parent rate propagation, so each of the clocks must be configured separately via device tree or consumer. Signed-off-by: Alvin =C5=A0ipraga Signed-off-by: Sascha Hauer --- drivers/clk/Kconfig | 7 + drivers/clk/Makefile | 1 + drivers/clk/clk-cdce6214.c | 1105 +++++++++++++++++++++++++++= ++++ include/dt-bindings/clock/ti,cdce6214.h | 24 + 4 files changed, 1137 insertions(+) diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 713573b6c86c7..499fd610c0467 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -170,6 +170,13 @@ config COMMON_CLK_BM1880 help This driver supports the clocks on Bitmain BM1880 SoC. =20 +config COMMON_CLK_CDCE6214 + tristate "Clock driver for TI CDCE6214 clock synthesizer" + depends on I2C + select REGMAP_I2C + help + This driver supports TI CDCE6214 programmable 1-PLL clock synthesizer. + config COMMON_CLK_CDCE706 tristate "Clock driver for TI CDCE706 clock synthesizer" depends on I2C diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index bf4bd45adc3a0..0f87b13b137b5 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) +=3D clk-axi-clkgen.o obj-$(CONFIG_ARCH_AXXIA) +=3D clk-axm5516.o obj-$(CONFIG_COMMON_CLK_BD718XX) +=3D clk-bd718x7.o obj-$(CONFIG_COMMON_CLK_BM1880) +=3D clk-bm1880.o +obj-$(CONFIG_COMMON_CLK_CDCE6214) +=3D clk-cdce6214.o obj-$(CONFIG_COMMON_CLK_CDCE706) +=3D clk-cdce706.o obj-$(CONFIG_COMMON_CLK_CDCE925) +=3D clk-cdce925.o obj-$(CONFIG_ARCH_CLPS711X) +=3D clk-clps711x.o diff --git a/drivers/clk/clk-cdce6214.c b/drivers/clk/clk-cdce6214.c new file mode 100644 index 0000000000000..a825cd71bb11b --- /dev/null +++ b/drivers/clk/clk-cdce6214.c @@ -0,0 +1,1105 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Driver for the TI CDCE6214 clock generator + * + * Copyright (c) 2023 Alvin =C5=A0ipraga + * Copyright (c) 2025 Sascha Hauer + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define RO_I2C_A0 BIT(15) +#define RO_PDN_INPUT_SEL BIT(14) +#define RO_GPIO4_DIR_SEL BIT(13) +#define RO_GPIO1_DIR_SEL BIT(12) +#define RO_ZDM_CLOCKSEL BIT(10) +#define RO_ZDM_EN BIT(8) +#define RO_SYNC BIT(5) +#define RO_RECAL BIT(4) +#define RO_RESETN_SOFT BIT(3) +#define RO_SWRST BIT(2) +#define RO_POWERDOWN BIT(1) +#define RO_MODE BIT(0) + +#define R1_GPIO4_INPUT_SEL GENMASK(15, 12) +#define R1_GPIO3_INPUT_SEL GENMASK(11, 8) +#define R1_GPIO2_INPUT_SEL GENMASK(7, 4) +#define R1_GPIO1_INPUT_SEL GENMASK(3, 0) + +#define R2_GPIO4_OUTPUT_SEL GENMASK(9, 6) +#define R2_GPIO1_OUTPUT_SEL GENMASK(5, 2) +#define R2_REFSEL_SW GENMASK(1, 0) + +#define R3_DISABLE_CRC BIT(13) +#define R3_UPDATE_CRC BIT(12) +#define R3_NVMCOMMIT BIT(11) +#define R3_REGCOMMIT BIT(10) +#define R3_REGCOMMIT_PAGE BIT(9) +#define R3_FREQ_DEC_REG BIT(6) +#define R3_FREQ_INC_REG BIT(5) +#define R3_FREQ_INC_DEC_REG_MODE BIT(4) +#define R3_FREQ_INC_DEC_EN BIT(3) + +#define R4_CH4_PD BIT(7) +#define R4_CH3_PD BIT(6) +#define R4_CH2_PD BIT(5) +#define R4_CH1_PD BIT(4) +#define R4_POST_EE_DLY GENMASK(3, 0) + +#define R5_PLL_VCOBUFF_LDO_PD BIT(8) +#define R5_PLL_VCO_LDO_PD BIT(7) +#define R5_PLL_VCO_BUFF_PD BIT(6) +#define R5_PLL_CP_LDO_PD BIT(5) +#define R5_PLL_LOCKDET_PD BIT(4) +#define R5_PLL_PSB_PD BIT(3) +#define R5_PLL_PSA_PD BIT(2) +#define R5_PLL_PFD_PD BIT(1) + +#define R7_NVMCRCERR BIT(5) +#define R7_LOCK_DET_S BIT(1) +#define R7_LOCK_DET BIT(0) + +#define R9_NVMLCRC GENMASK(15, 0) + +#define R10_NVMSCRC GENMASK(15, 0) + +#define R11_NVM_RD_ADDR GENMASK(5, 0) + +#define R12_NVM_RD_DATA GENMASK(15, 0) + +#define R13_NVM_WR_ADDR GENMASK(5, 0) + +#define R14_NVM_WR_DATA GENMASK(15, 0) + +#define R15_EE_LOCK GENMASK(15, 12) +#define R15_CAL_MUTE BIT(5) + +#define R24_IP_PRIREF_BUF_SEL BIT(15) +#define R24_IP_XO_CLOAD GENMASK(12, 8) +#define R24_IP_BIAS_SEL_XO GENMASK(5, 2) +#define R24_IP_SECREF_BUF_SEL GENMASK(1, 0) +#define R24_IP_SECREF_BUF_SEL_XTAL 0 +#define R24_IP_SECREF_BUF_SEL_LVCMOS 1 +#define R24_IP_SECREF_BUF_SEL_DIFF 2 + +#define R25_IP_REF_TO_OUT4_EN BIT(14) +#define R25_IP_REF_TO_OUT3_EN BIT(13) +#define R25_IP_REF_TO_OUT2_EN BIT(12) +#define R25_IP_REF_TO_OUT1_EN BIT(11) +#define R25_IP_BYP_OUT0_EN BIT(10) +#define R25_REF_CH_MUX BIT(9) +#define R25_IP_RDIV GENMASK(7, 0) + +#define R27_MASH_ORDER GENMASK(1, 0) + +#define R30_PLL_NDIV GENMASK(14, 0) + +#define R31_PLL_NUM_15_0 GENMASK(15, 0) + +#define R32_PLL_NUM_23_16 GENMASK(7, 0) + +#define R33_PLL_DEN_15_0 GENMASK(15, 0) + +#define R34_PLL_DEN_23_16 GENMASK(7, 0) + +#define R41_SSC_EN BIT(15) + +#define R42_SSC_TYPE BIT(5) +#define R42_SSC_SEL GENMASK(3, 1) + +#define R43_FREQ_INC_DEC_DELTA GENMASK(15, 0) + +#define R47_PLL_CP_DN GENMASK(12, 7) +#define R47_PLL_PSB GENMASK(6, 5) +#define R47_PLL_PSA GENMASK(4, 3) + +#define R48_PLL_LF_RES GENMASK(14, 11) +#define R48_PLL_CP_UP GENMASK(5, 0) + +#define R49_PLL_LF_ZCAP GENMASK(4, 0) + +#define R50_PLL_LOCKDET_WINDOW GENMASK(10, 8) + +#define R51_PLL_PFD_DLY_EN BIT(10) +#define R51_PLL_PFD_CTRL BIT(6) + +#define R52_PLL_NCTRL_EN BIT(6) +#define R52_PLL_CP_EN BIT(3) + +#define R55_PLL_LF_3_PCTRIM GENMASK(9, 8) +#define R55_PLL_LF_3_PRTRIM GENMASK(7, 6) + +#define R56_CH1_MUX GENMASK(15, 14) +#define R56_CH1_DIV GENMASK(13, 0) + +#define R57_CH1_LPHCSL_EN BIT(14) +#define R57_CH1_1P8VDET BIT(12) +#define R57_CH1_GLITCHLESS_EN BIT(9) +#define R57_CH1_SYNC_DELAY GENMASK(8, 4) +#define R57_CH1_SYNC_EN BIT(3) +#define R57_CH1_MUTE_SEL BIT(1) +#define R57_CH1_MUTE BIT(0) + +#define R59_CH1_LVDS_EN BIT(15) +#define R59_CH1_CMOSN_EN BIT(14) +#define R59_CH1_CMOSP_EN BIT(13) +#define R59_CH1_CMOSN_POL BIT(12) +#define R59_CH1_CMOSP_POL BIT(11) + +#define R60_CH1_DIFFBUF_IBIAS_TRIM GENMASK(15, 12) +#define R60_CH1_LVDS_CMTRIM_INC GENMASK(11, 10) +#define R60_CH1_LVDS_CMTRIM_DEC GENMASK(5, 4) +#define R60_CH1_CMOS_SLEW_RATE_CTRL GENMASK(3, 0) + +#define R62_CH2_MUX GENMASK(15, 14) +#define R62_CH2_DIV GENMASK(13, 0) + +#define R63_CH2_LPHCSL_EN BIT(13) +#define R63_CH2_1P8VDET BIT(12) +#define R63_CH2_GLITCHLESS_EN BIT(9) +#define R63_CH2_SYNC_DELAY GENMASK(8, 4) +#define R63_CH2_SYNC_EN BIT(3) +#define R63_CH2_MUTE_SEL BIT(1) +#define R63_CH2_MUTE BIT(0) + +#define R65_CH2_LVDS_CMTRIM_DEC GENMASK(14, 13) +#define R65_CH2_LVDS_EN BIT(11) + +#define R66_CH2_LVDS_CMTRIM_IN GENMASK(5, 4) +#define R66_CH2_DIFFBUF_IBIAS_TRIM GENMASK(3, 0) + +#define R67_CH3_MUX GENMASK(15, 14) +#define R67_CH3_DIV GENMASK(13, 0) + +#define R68_CH3_LPHCSL_EN BIT(13) +#define R68_CH3_1P8VDET BIT(12) +#define R68_CH3_GLITCHLESS_EN BIT(9) +#define R68_CH3_SYNC_DELAY GENMASK(8, 4) +#define R68_CH3_SYNC_EN BIT(3) +#define R68_CH3_MUTE_SEL BIT(1) +#define R68_CH3_MUTE BIT(0) + +#define R70_CH3_LVDS_EN BIT(11) + +#define R71_CH3_LVDS_CMTRIM_DEC GENMASK(10, 9) +#define R71_CH3_LVDS_CMTRIM_INC GENMASK(5, 4) +#define R71_CH3_DIFFBUF_IBIAS_TR GENMASK(3, 0) + +#define R72_CH4_MUX GENMASK(15, 14) +#define R72_CH4_DIV GENMASK(13, 0) + +#define R73_CH4_LPHCSL_EN BIT(13) +#define R73_CH4_1P8VDET BIT(12) +#define R73_CH4_GLITCHLESS_EN BIT(9) +#define R73_CH4_SYNC_DELAY GENMASK(8, 4) +#define R73_CH4_SYNC_EN BIT(3) +#define R73_CH4_MUTE_SEL BIT(1) +#define R73_CH4_MUTE BIT(0) + +#define R75_CH4_LVDS_EN BIT(15) +#define R75_CH4_CMOSP_EN BIT(14) +#define R75_CH4_CMOSN_EN BIT(13) +#define R75_CH4_CMOSP_POL BIT(12) +#define R75_CH4_CMOSN_POL BIT(11) + +#define R76_CH4_DIFFBUF_IBIAS_TRIM GENMASK(9, 6) +#define R76_CH4_LVDS_CMTRIM_IN GENMASK(5, 4) +#define R76_CH4_CMOS_SLEW_RATE_CTRL GENMASK(3, 0) + +#define R77_CH4_LVDS_CMTRIM_DEC GENMASK(1, 0) + +#define R78_CH0_EN BIT(12) + +#define R79_SAFETY_1P8V_MODE BIT(9) +#define R79_CH0_CMOS_SLEW_RATE_CTRL GENMASK(3, 0) + +#define R81_PLL_LOCK_MASK BIT(3) + +#define CDCE6214_VCO_MIN 2335000000 +#define CDCE6214_VCO_MAX 2625000000 +#define CDCE6214_DENOM_DEFAULT (1 << 24) + +static char *clk_names[] =3D { + [CDCE6214_CLK_PRIREF] =3D "priref", + [CDCE6214_CLK_SECREF] =3D "secref", + [CDCE6214_CLK_OUT0] =3D "out0", + [CDCE6214_CLK_OUT1] =3D "out1", + [CDCE6214_CLK_OUT2] =3D "out2", + [CDCE6214_CLK_OUT3] =3D "out3", + [CDCE6214_CLK_OUT4] =3D "out4", + [CDCE6214_CLK_PLL] =3D "pll", + [CDCE6214_CLK_PSA] =3D "psa", + [CDCE6214_CLK_PSB] =3D "psb", +}; + +#define CDCE6214_NUM_CLOCKS ARRAY_SIZE(clk_names) + +struct cdce6214; + +struct cdce6214_clock { + struct clk_hw hw; + struct cdce6214 *priv; + int index; +}; + +struct cdce6214_config { + const struct reg_default *reg_default; + int reg_default_size; +}; + +struct cdce6214 { + struct i2c_client *client; + struct device *dev; + struct regmap *regmap; + struct gpio_desc *reset_gpio; + const struct cdce6214_config *config; + struct cdce6214_clock clk[CDCE6214_NUM_CLOCKS]; +}; + +static inline struct cdce6214_clock *hw_to_cdce6214_clk(struct clk_hw *hw) +{ + return container_of(hw, struct cdce6214_clock, hw); +} + +static struct clk_hw *cdce6214_of_clk_get(struct of_phandle_args *clkspec, + void *data) +{ + struct cdce6214 *priv =3D data; + unsigned int idx =3D clkspec->args[0]; + + if (idx >=3D CDCE6214_NUM_CLOCKS) + return ERR_PTR(-EINVAL); + if (idx <=3D CDCE6214_CLK_SECREF) + return ERR_PTR(-EINVAL); + + return &priv->clk[idx].hw; +} + +static const struct regmap_config cdce6214_regmap_config =3D { + .reg_bits =3D 16, + .val_bits =3D 16, + .reg_stride =3D 1, + .max_register =3D 0x0055, +}; + +static int cdce6214_configure(struct cdce6214 *priv) +{ + regmap_update_bits(priv->regmap, 2, R2_REFSEL_SW, + FIELD_PREP(R2_REFSEL_SW, 2)); + + return 0; +} + +static unsigned long cdce6214_clk_out0_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct cdce6214_clock *clock =3D hw_to_cdce6214_clk(hw); + struct cdce6214 *priv =3D clock->priv; + unsigned int val, div; + + regmap_read(priv->regmap, 25, &val); + + div =3D FIELD_GET(R25_IP_RDIV, val); + + if (!div) + return parent_rate * 2; + + return DIV_ROUND_UP_ULL((u64)parent_rate, div); +} + +static long cdce6214_clk_out0_round_rate(struct clk_hw *hw, unsigned long = rate, + unsigned long *best_parent_rate) +{ + unsigned int div; + + if (rate >=3D *best_parent_rate) + return *best_parent_rate * 2; + + div =3D DIV_ROUND_CLOSEST(*best_parent_rate, rate); + + return DIV_ROUND_UP_ULL((u64)*best_parent_rate, div); +} + +static int cdce6214_clk_out0_set_rate(struct clk_hw *hw, unsigned long rat= e, + unsigned long parent_rate) +{ + struct cdce6214_clock *clock =3D hw_to_cdce6214_clk(hw); + struct cdce6214 *priv =3D clock->priv; + unsigned int div; + + if (rate >=3D parent_rate) { + regmap_update_bits(priv->regmap, 25, R25_IP_RDIV, FIELD_PREP(R25_IP_RDIV= , 0)); + return 0; + } + + div =3D DIV_ROUND_CLOSEST(parent_rate, rate); + if (div > R25_IP_RDIV) + div =3D R25_IP_RDIV; + + regmap_update_bits(priv->regmap, 25, R25_IP_RDIV, FIELD_PREP(R25_IP_RDIV,= div)); + + return 0; +} + +static u8 cdce6214_clk_out0_get_parent(struct clk_hw *hw) +{ + struct cdce6214_clock *clock =3D hw_to_cdce6214_clk(hw); + struct cdce6214 *priv =3D clock->priv; + unsigned int val, idx; + + regmap_read(priv->regmap, 2, &val); + + idx =3D FIELD_GET(R2_REFSEL_SW, val); + + switch (idx) { + case 0: + case 1: + idx =3D 0; + break; + case 2: + idx =3D 1; + break; + case 3: + idx =3D 0; + break; + }; + + return idx; +} + +static int cdce6214_clk_out0_set_parent(struct clk_hw *hw, u8 index) +{ + struct cdce6214_clock *clock =3D hw_to_cdce6214_clk(hw); + struct cdce6214 *priv =3D clock->priv; + + regmap_update_bits(priv->regmap, 25, R25_REF_CH_MUX, FIELD_PREP(R25_REF_C= H_MUX, index)); + + return 0; +} + +static const struct clk_ops cdce6214_clk_out0_ops =3D { + .recalc_rate =3D cdce6214_clk_out0_recalc_rate, + .round_rate =3D cdce6214_clk_out0_round_rate, + .set_rate =3D cdce6214_clk_out0_set_rate, + .get_parent =3D cdce6214_clk_out0_get_parent, + .set_parent =3D cdce6214_clk_out0_set_parent, +}; + +static int cdce6214_clk_out_ldo(struct clk_hw *hw, int enable) +{ + struct cdce6214_clock *clock =3D hw_to_cdce6214_clk(hw); + struct cdce6214 *priv =3D clock->priv; + unsigned int mask, val; + + switch (clock->index) { + case CDCE6214_CLK_OUT1: + mask =3D R4_CH1_PD; + break; + case CDCE6214_CLK_OUT2: + mask =3D R4_CH2_PD; + break; + case CDCE6214_CLK_OUT3: + mask =3D R4_CH3_PD; + break; + case CDCE6214_CLK_OUT4: + mask =3D R4_CH4_PD; + break; + default: + return -EINVAL; + }; + + if (enable > 0) { + regmap_clear_bits(priv->regmap, 4, mask); + } else if (!enable) { + regmap_set_bits(priv->regmap, 4, mask); + } else { + regmap_read(priv->regmap, 4, &val); + return !(val & mask); + } + + return 0; +} + +static int cdce6214_clk_out_prepare(struct clk_hw *hw) +{ + return cdce6214_clk_out_ldo(hw, 1); +} + +static void cdce6214_clk_out_unprepare(struct clk_hw *hw) +{ + cdce6214_clk_out_ldo(hw, 0); +} + +static int cdce6214_clk_out_is_prepared(struct clk_hw *hw) +{ + return cdce6214_clk_out_ldo(hw, -1); +} + +static unsigned long cdce6214_clk_out_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct cdce6214_clock *clock =3D hw_to_cdce6214_clk(hw); + struct cdce6214 *priv =3D clock->priv; + unsigned int val, div; + unsigned long r; + + switch (clock->index) { + case CDCE6214_CLK_OUT1: + regmap_read(priv->regmap, 56, &val); + div =3D FIELD_GET(R56_CH1_DIV, val); + break; + case CDCE6214_CLK_OUT2: + regmap_read(priv->regmap, 62, &val); + div =3D FIELD_GET(R62_CH2_DIV, val); + break; + case CDCE6214_CLK_OUT3: + regmap_read(priv->regmap, 67, &val); + div =3D FIELD_GET(R67_CH3_DIV, val); + break; + case CDCE6214_CLK_OUT4: + regmap_read(priv->regmap, 72, &val); + div =3D FIELD_GET(R72_CH4_DIV, val); + break; + }; + + if (!div) + div =3D 1; + + r =3D DIV_ROUND_UP_ULL((u64)parent_rate, div); + + return r; +} + +static int cdce6214_get_out_div(unsigned long rate, unsigned long parent_r= ate) +{ + unsigned int div =3D DIV_ROUND_CLOSEST(parent_rate, rate); + + if (div < 1) + div =3D 1; + + if (div > R72_CH4_DIV) + div =3D R72_CH4_DIV; + + return div; +} + +static long cdce6214_clk_out_round_rate(struct clk_hw *hw, unsigned long r= ate, + unsigned long *best_parent_rate) +{ + unsigned int div =3D cdce6214_get_out_div(rate, *best_parent_rate); + + return DIV_ROUND_UP_ULL((u64)*best_parent_rate, div); +} + +static int cdce6214_clk_out_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + unsigned int div =3D cdce6214_get_out_div(rate, parent_rate); + struct cdce6214_clock *clock =3D hw_to_cdce6214_clk(hw); + struct cdce6214 *priv =3D clock->priv; + + switch (clock->index) { + case CDCE6214_CLK_OUT1: + regmap_update_bits(priv->regmap, 56, R56_CH1_DIV, + FIELD_PREP(R56_CH1_DIV, div)); + break; + case CDCE6214_CLK_OUT2: + regmap_update_bits(priv->regmap, 62, R62_CH2_DIV, + FIELD_PREP(R62_CH2_DIV, div)); + break; + case CDCE6214_CLK_OUT3: + regmap_update_bits(priv->regmap, 67, R67_CH3_DIV, + FIELD_PREP(R67_CH3_DIV, div)); + break; + case CDCE6214_CLK_OUT4: + regmap_update_bits(priv->regmap, 72, R72_CH4_DIV, + FIELD_PREP(R72_CH4_DIV, div)); + break; + }; + + return 0; +} + +static u8 cdce6214_clk_out_get_parent(struct clk_hw *hw) +{ + struct cdce6214_clock *clock =3D hw_to_cdce6214_clk(hw); + struct cdce6214 *priv =3D clock->priv; + unsigned int val, idx; + + switch (clock->index) { + case CDCE6214_CLK_OUT1: + regmap_read(priv->regmap, 56, &val); + idx =3D FIELD_GET(R56_CH1_MUX, val); + break; + case CDCE6214_CLK_OUT2: + regmap_read(priv->regmap, 62, &val); + idx =3D FIELD_GET(R62_CH2_MUX, val); + break; + case CDCE6214_CLK_OUT3: + regmap_read(priv->regmap, 67, &val); + idx =3D FIELD_GET(R67_CH3_MUX, val); + break; + case CDCE6214_CLK_OUT4: + regmap_read(priv->regmap, 72, &val); + idx =3D FIELD_GET(R72_CH4_MUX, val); + break; + }; + + return idx; +} + +static int cdce6214_clk_out_set_parent(struct clk_hw *hw, u8 index) +{ + struct cdce6214_clock *clock =3D hw_to_cdce6214_clk(hw); + struct cdce6214 *priv =3D clock->priv; + + switch (clock->index) { + case CDCE6214_CLK_OUT1: + regmap_update_bits(priv->regmap, 56, R56_CH1_MUX, FIELD_PREP(R56_CH1_MUX= , index)); + break; + case CDCE6214_CLK_OUT2: + regmap_update_bits(priv->regmap, 62, R62_CH2_MUX, FIELD_PREP(R62_CH2_MUX= , index)); + break; + case CDCE6214_CLK_OUT3: + regmap_update_bits(priv->regmap, 67, R67_CH3_MUX, FIELD_PREP(R67_CH3_MUX= , index)); + break; + case CDCE6214_CLK_OUT4: + regmap_update_bits(priv->regmap, 72, R72_CH4_MUX, FIELD_PREP(R72_CH4_MUX= , index)); + break; + }; + + return 0; +} + +static const struct clk_ops cdce6214_clk_out_ops =3D { + .prepare =3D cdce6214_clk_out_prepare, + .unprepare =3D cdce6214_clk_out_unprepare, + .is_prepared =3D cdce6214_clk_out_is_prepared, + .recalc_rate =3D cdce6214_clk_out_recalc_rate, + .round_rate =3D cdce6214_clk_out_round_rate, + .set_rate =3D cdce6214_clk_out_set_rate, + .get_parent =3D cdce6214_clk_out_get_parent, + .set_parent =3D cdce6214_clk_out_set_parent, +}; + +static int pll_calc_values(unsigned long parent_rate, unsigned long out, + unsigned long *ndiv, unsigned long *num, unsigned long *den) +{ + u64 a; + + if (out < CDCE6214_VCO_MIN || out > CDCE6214_VCO_MAX) + return -EINVAL; + + *den =3D 10000000; + *ndiv =3D out / parent_rate; + a =3D (out % parent_rate); + a *=3D *den; + do_div(a, parent_rate); + *num =3D a; + + return 0; +} + +static unsigned long cdce6214_clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct cdce6214_clock *clock =3D hw_to_cdce6214_clk(hw); + struct cdce6214 *priv =3D clock->priv; + unsigned long ndiv, num, den; + unsigned int val; + + regmap_read(priv->regmap, 30, &val); + ndiv =3D FIELD_GET(R30_PLL_NDIV, val); + + regmap_read(priv->regmap, 31, &val); + num =3D FIELD_GET(R31_PLL_NUM_15_0, val); + + regmap_read(priv->regmap, 32, &val); + num |=3D FIELD_GET(R32_PLL_NUM_23_16, val) << 16; + + regmap_read(priv->regmap, 33, &val); + den =3D FIELD_GET(R33_PLL_DEN_15_0, val); + + regmap_read(priv->regmap, 34, &val); + den |=3D FIELD_GET(R34_PLL_DEN_23_16, val) << 16; + + if (!den) + den =3D CDCE6214_DENOM_DEFAULT; + + return parent_rate * ndiv + DIV_ROUND_CLOSEST(parent_rate * num, den); +} + +static long cdce6214_clk_pll_round_rate(struct clk_hw *hw, unsigned long r= ate, + unsigned long *best_parent_rate) +{ + if (rate < CDCE6214_VCO_MIN) + rate =3D CDCE6214_VCO_MIN; + if (rate > CDCE6214_VCO_MAX) + rate =3D CDCE6214_VCO_MAX; + if (rate < *best_parent_rate * 24) + return -EINVAL; + + return rate; +} + +static bool cdce6214_pll_locked(struct cdce6214 *priv) +{ + unsigned int val; + + regmap_read(priv->regmap, 7, &val); + + return val & R7_LOCK_DET; +} + +static int cdce6214_wait_pll_lock(struct cdce6214 *priv) +{ + unsigned int val; + int ret; + + ret =3D regmap_read_poll_timeout(priv->regmap, 7, val, + val & R7_LOCK_DET, 0, 1000); + if (ret) + dev_err(priv->dev, "Timeout waiting for PLL lock\n"); + + return ret; +} + +#define R5_PLL_POWER_BITS (R5_PLL_VCOBUFF_LDO_PD | \ + R5_PLL_VCO_LDO_PD | \ + R5_PLL_VCO_BUFF_PD) + +static int cdce6214_clk_pll_prepare(struct clk_hw *hw) +{ + struct cdce6214_clock *clock =3D hw_to_cdce6214_clk(hw); + struct cdce6214 *priv =3D clock->priv; + + regmap_clear_bits(priv->regmap, 5, R5_PLL_POWER_BITS); + + regmap_set_bits(priv->regmap, 0, RO_RECAL); + + return cdce6214_wait_pll_lock(priv); +} + +static void cdce6214_clk_pll_unprepare(struct clk_hw *hw) +{ + struct cdce6214_clock *clock =3D hw_to_cdce6214_clk(hw); + struct cdce6214 *priv =3D clock->priv; + + regmap_set_bits(priv->regmap, 5, R5_PLL_POWER_BITS); +} + +static bool cdce6214_clk_pll_powered(struct cdce6214 *priv) +{ + unsigned int val; + + regmap_read(priv->regmap, 5, &val); + + return (val & R5_PLL_POWER_BITS) =3D=3D 0; +} + +static int cdce6214_clk_pll_is_prepared(struct clk_hw *hw) +{ + struct cdce6214_clock *clock =3D hw_to_cdce6214_clk(hw); + struct cdce6214 *priv =3D clock->priv; + + return cdce6214_pll_locked(priv); +} + +static int cdce6214_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct cdce6214_clock *clock =3D hw_to_cdce6214_clk(hw); + struct cdce6214 *priv =3D clock->priv; + unsigned long ndiv, num, den; + int ret; + + ret =3D pll_calc_values(parent_rate, rate, &ndiv, &num, &den); + if (ret < 0) + return ret; + + if (den =3D=3D CDCE6214_DENOM_DEFAULT) + den =3D 0; + + regmap_update_bits(priv->regmap, 34, R34_PLL_DEN_23_16, + FIELD_PREP(R34_PLL_DEN_23_16, den >> 16)); + regmap_update_bits(priv->regmap, 33, R33_PLL_DEN_15_0, + FIELD_PREP(R33_PLL_DEN_15_0, den & 0xffff)); + regmap_update_bits(priv->regmap, 32, R32_PLL_NUM_23_16, + FIELD_PREP(R32_PLL_NUM_23_16, num >> 16)); + regmap_update_bits(priv->regmap, 31, R31_PLL_NUM_15_0, + FIELD_PREP(R31_PLL_NUM_15_0, num & 0xffff)); + regmap_update_bits(priv->regmap, 30, R30_PLL_NDIV, + FIELD_PREP(R30_PLL_NDIV, ndiv)); + + regmap_update_bits(priv->regmap, 3, R3_FREQ_INC_DEC_REG_MODE | R3_FREQ_IN= C_DEC_EN, + R3_FREQ_INC_DEC_REG_MODE | R3_FREQ_INC_DEC_EN); + + if (cdce6214_clk_pll_powered(priv)) { + regmap_set_bits(priv->regmap, 0, RO_RECAL); + ret =3D cdce6214_wait_pll_lock(priv); + } + + return ret; +} + +static const struct clk_ops cdce6214_clk_pll_ops =3D { + .prepare =3D cdce6214_clk_pll_prepare, + .unprepare =3D cdce6214_clk_pll_unprepare, + .is_prepared =3D cdce6214_clk_pll_is_prepared, + .recalc_rate =3D cdce6214_clk_pll_recalc_rate, + .round_rate =3D cdce6214_clk_pll_round_rate, + .set_rate =3D cdce6214_clk_pll_set_rate, +}; + +static int cdce6214_clk_psx_ldo(struct clk_hw *hw, int enable) +{ + struct cdce6214_clock *clock =3D hw_to_cdce6214_clk(hw); + struct cdce6214 *priv =3D clock->priv; + unsigned int mask, val; + + switch (clock->index) { + case CDCE6214_CLK_PSA: + mask =3D R5_PLL_PSA_PD; + break; + case CDCE6214_CLK_PSB: + mask =3D R5_PLL_PSB_PD; + break; + default: + return -EINVAL; + }; + + if (enable > 0 ) { + regmap_clear_bits(priv->regmap, 5, mask); + } else if (!enable) { + regmap_set_bits(priv->regmap, 5, mask); + } else { + regmap_read(priv->regmap, 5, &val); + + return !(val & mask); + } + + return 0; +} + +static int cdce6214_clk_psx_prepare(struct clk_hw *hw) +{ + return cdce6214_clk_psx_ldo(hw, 1); +} + +static void cdce6214_clk_psx_unprepare(struct clk_hw *hw) +{ + cdce6214_clk_psx_ldo(hw, 0); +} + +static int cdce6214_clk_psx_is_prepared(struct clk_hw *hw) +{ + return cdce6214_clk_psx_ldo(hw, -1); +} + +static unsigned long cdce6214_clk_psx_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct cdce6214_clock *clock =3D hw_to_cdce6214_clk(hw); + struct cdce6214 *priv =3D clock->priv; + unsigned int psx[] =3D { 4, 5, 6, 6 }; + unsigned int val, div; + + regmap_read(priv->regmap, 47, &val); + + switch (clock->index) { + case CDCE6214_CLK_PSA: + div =3D psx[FIELD_GET(R47_PLL_PSA, val)]; + break; + case CDCE6214_CLK_PSB: + div =3D psx[FIELD_GET(R47_PLL_PSB, val)]; + break; + }; + + return DIV_ROUND_UP_ULL((u64)parent_rate, div); +} + +static int cdce6214_get_psx_div(unsigned long rate, unsigned long parent_r= ate) +{ + unsigned int div =3D DIV_ROUND_CLOSEST(parent_rate, rate); + + if (div < 4) + div =3D 4; + + if (div > 6) + div =3D 6; + + return div; +} + +static long cdce6214_clk_psx_round_rate(struct clk_hw *hw, unsigned long r= ate, + unsigned long *best_parent_rate) +{ + unsigned int div =3D cdce6214_get_psx_div(rate, *best_parent_rate); + + return DIV_ROUND_UP_ULL((u64)*best_parent_rate, div); +} + +static int cdce6214_clk_psx_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + unsigned int div =3D cdce6214_get_psx_div(rate, parent_rate); + struct cdce6214_clock *clock =3D hw_to_cdce6214_clk(hw); + struct cdce6214 *priv =3D clock->priv; + + switch (clock->index) { + case CDCE6214_CLK_PSA: + regmap_update_bits(priv->regmap, 47, R47_PLL_PSA, + FIELD_PREP(R47_PLL_PSA, div)); + break; + case CDCE6214_CLK_PSB: + regmap_update_bits(priv->regmap, 47, R47_PLL_PSB, + FIELD_PREP(R47_PLL_PSB, div)); + break; + }; +=09 + return 0; +} + +static const struct clk_ops cdce6214_clk_psx_ops =3D { + .prepare =3D cdce6214_clk_psx_prepare, + .unprepare =3D cdce6214_clk_psx_unprepare, + .is_prepared =3D cdce6214_clk_psx_is_prepared, + .recalc_rate =3D cdce6214_clk_psx_recalc_rate, + .round_rate =3D cdce6214_clk_psx_round_rate, + .set_rate =3D cdce6214_clk_psx_set_rate, +}; + +static int cdce6214_clk_register(struct cdce6214 *priv) +{ + struct clk_init_data init[CDCE6214_NUM_CLOCKS] =3D { 0 }; + struct clk_parent_data pdata_out0[2] =3D {}; + struct clk_parent_data pdata_out[4] =3D {}; + struct clk_parent_data pdata_pll =3D {}; + struct clk_parent_data pdata_psx =3D {}; + int i, ret; + + pdata_out0[0].fw_name =3D "priref"; + pdata_out0[1].fw_name =3D "secref"; + + init[CDCE6214_CLK_OUT0].ops =3D &cdce6214_clk_out0_ops; + init[CDCE6214_CLK_OUT0].num_parents =3D 2; + init[CDCE6214_CLK_OUT0].parent_data =3D pdata_out0; + init[CDCE6214_CLK_OUT0].flags =3D CLK_SET_RATE_NO_REPARENT; + + pdata_out[0].hw =3D &priv->clk[CDCE6214_CLK_PSA].hw; + pdata_out[1].hw =3D &priv->clk[CDCE6214_CLK_PSB].hw; + pdata_out[3].hw =3D &priv->clk[CDCE6214_CLK_OUT0].hw; + + for (i =3D CDCE6214_CLK_OUT1; i <=3D CDCE6214_CLK_OUT4; i++) { + init[i].ops =3D &cdce6214_clk_out_ops; + init[i].num_parents =3D 4; + init[i].parent_data =3D pdata_out; + init[i].flags =3D CLK_SET_RATE_NO_REPARENT; + } + + init[CDCE6214_CLK_PLL].ops =3D &cdce6214_clk_pll_ops; + init[CDCE6214_CLK_PLL].num_parents =3D 1; + pdata_pll.hw =3D &priv->clk[CDCE6214_CLK_OUT0].hw; + init[CDCE6214_CLK_PLL].parent_data =3D &pdata_pll; + + pdata_psx.hw =3D &priv->clk[CDCE6214_CLK_PLL].hw; + for (i =3D CDCE6214_CLK_PSA; i <=3D CDCE6214_CLK_PSB; i++) { + init[i].ops =3D &cdce6214_clk_psx_ops; + init[i].num_parents =3D 1; + init[i].parent_data =3D &pdata_psx; + } + + for (i =3D 0; i < CDCE6214_NUM_CLOCKS; i++) { + struct cdce6214_clock *clk =3D &priv->clk[i]; + char name[128]; + + if (!init[i].ops) + continue; + + snprintf(name, sizeof(name), "%s_%s", dev_name(priv->dev), clk_names[i]); + init[i].name =3D name; + clk->hw.init =3D &init[i]; + clk->priv =3D priv; + clk->index =3D i; + ret =3D devm_clk_hw_register(priv->dev, &clk->hw); + if (ret) + return ret; + } + + return 0; +} + +static inline int regmap_clrset_bit(struct cdce6214 *priv, unsigned int re= g, + unsigned int bit, bool set) +{ + return regmap_update_bits(priv->regmap, reg, bit, set ? bit : 0); +} + +static int cdce6214_parse_subnode(struct cdce6214 *priv, struct device_nod= e *np) +{ + unsigned int idx, mode; + struct cdce6214_clock *clk; + bool lphcsl, lvds, cmosp, cmosn, ref_xtal, ref_lvcmos, ref_diff; + int ret; + + ret =3D of_property_read_u32(np, "reg", &idx); + if (ret) { + dev_err(priv->dev, "missing reg property in child: %s\n", + np->full_name); + return ret; + } + + if (idx >=3D CDCE6214_NUM_CLOCKS) + return -EINVAL; + + clk =3D &priv->clk[idx]; + + lphcsl =3D of_property_read_bool(np, "ti,lphcsl"); + lvds =3D of_property_read_bool(np, "ti,lvds"); + cmosp =3D of_property_read_bool(np, "ti,cmosp"); + cmosn =3D of_property_read_bool(np, "ti,cmosn"); + + ref_xtal =3D of_property_read_bool(np, "ti,ref-xtal"); + ref_lvcmos =3D of_property_read_bool(np, "ti,ref-lvcmos"); + ref_diff =3D of_property_read_bool(np, "ti,ref-diff"); + + switch (idx) { + case CDCE6214_CLK_OUT1: + regmap_clrset_bit(priv, 57, R57_CH1_LPHCSL_EN, lphcsl); + regmap_clrset_bit(priv, 59, R59_CH1_LVDS_EN, lvds); + regmap_clrset_bit(priv, 59, R59_CH1_CMOSP_EN, cmosp); + regmap_clrset_bit(priv, 59, R59_CH1_CMOSN_EN, cmosn); + lphcsl =3D lvds =3D cmosp =3D cmosn =3D false; + break; + case CDCE6214_CLK_OUT2: + regmap_clrset_bit(priv, 63, R63_CH2_LPHCSL_EN, lphcsl); + regmap_clrset_bit(priv, 65, R65_CH2_LVDS_EN, lvds); + lphcsl =3D lvds =3D false; + break; + case CDCE6214_CLK_OUT3: + regmap_clrset_bit(priv, 68, R68_CH3_LPHCSL_EN, lphcsl); + regmap_clrset_bit(priv, 70, R70_CH3_LVDS_EN, lvds); + lphcsl =3D lvds =3D false; + break; + case CDCE6214_CLK_OUT4: + regmap_clrset_bit(priv, 73, R73_CH4_LPHCSL_EN, lphcsl); + regmap_clrset_bit(priv, 75, R75_CH4_LVDS_EN, lvds); + regmap_clrset_bit(priv, 75, R75_CH4_CMOSP_EN, cmosp); + regmap_clrset_bit(priv, 75, R75_CH4_CMOSN_EN, cmosn); + lphcsl =3D lvds =3D cmosp =3D cmosn =3D false; + break; + case CDCE6214_CLK_PRIREF: + if (ref_lvcmos + ref_diff !=3D 1) { + dev_err(priv->dev, "Multiple or no input modes in %pOF\n", np); + return -EINVAL; + } + + if (ref_lvcmos) + regmap_clear_bits(priv->regmap, 24, R24_IP_PRIREF_BUF_SEL); + if (ref_diff) + regmap_set_bits(priv->regmap, 24, R24_IP_PRIREF_BUF_SEL); + + ref_lvcmos =3D ref_diff =3D false; + break; + case CDCE6214_CLK_SECREF: + if (ref_xtal + ref_lvcmos + ref_diff !=3D 1) { + dev_err(priv->dev, "Multiple or no input modes in %pOF\n", np); + return -EINVAL; + } + + if (ref_xtal) + mode =3D R24_IP_SECREF_BUF_SEL_XTAL; + else if (ref_lvcmos) + mode =3D R24_IP_SECREF_BUF_SEL_LVCMOS; + else + mode =3D R24_IP_SECREF_BUF_SEL_DIFF; + + regmap_update_bits(priv->regmap, 24, R24_IP_SECREF_BUF_SEL, mode); + ref_xtal =3D ref_lvcmos =3D ref_diff =3D false; + break; + } + + if (lphcsl || lvds || cmosp || cmosn || ref_xtal || ref_lvcmos || ref_dif= f) + dev_warn(priv->dev, "%pOF contains unhandled properties\n", np); + + return 0; +} + +static int cdce6214_probe(struct i2c_client *client) +{ + struct device *dev =3D &client->dev; + struct device_node *child; + struct cdce6214 *priv; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->config =3D device_get_match_data(dev); + priv->client =3D client; + priv->dev =3D dev; + i2c_set_clientdata(client, priv); + dev_set_drvdata(dev, priv); + + priv->reset_gpio =3D devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(priv->reset_gpio)) { + return dev_err_probe(dev, PTR_ERR(priv->reset_gpio), + "failed to get reset gpio\n"); + } + + priv->regmap =3D devm_regmap_init_i2c(client, &cdce6214_regmap_config); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + ret =3D cdce6214_configure(priv); + if (ret) + return ret; + + for_each_child_of_node(dev->of_node, child) { + ret =3D cdce6214_parse_subnode(priv, child); + if (ret) + return ret; + } + + ret =3D cdce6214_clk_register(priv); + if (ret) + return ret; + + ret =3D devm_of_clk_add_hw_provider(dev, cdce6214_of_clk_get, priv); + if (ret) + return ret; + + return 0; +} + +static const struct of_device_id cdce6214_ids[] =3D { + { + .compatible =3D "ti,cdce6214-24mhz", + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, cdce6214_ids); + +static struct i2c_driver cdce6214_driver =3D { + .driver =3D { + .name =3D "cdce6214", + .of_match_table =3D cdce6214_ids, + .probe_type =3D PROBE_PREFER_ASYNCHRONOUS, + }, + .probe =3D cdce6214_probe, +}; +module_i2c_driver(cdce6214_driver); + +MODULE_AUTHOR("Alvin =C5=A0ipraga "); +MODULE_AUTHOR("Sascha Hauer "); +MODULE_DESCRIPTION("TI CDCE6214 driver"); +MODULE_LICENSE("GPL"); diff --git a/include/dt-bindings/clock/ti,cdce6214.h b/include/dt-bindings/= clock/ti,cdce6214.h new file mode 100644 index 0000000000000..1b41060896cc3 --- /dev/null +++ b/include/dt-bindings/clock/ti,cdce6214.h @@ -0,0 +1,24 @@ +#ifndef _DT_BINDINGS_CLK_TI_CDCE6214_H +#define _DT_BINDINGS_CLK_TI_CDCE6214_H + +/* + * primary/secondary inputs. Not registered as clocks, but used + * as reg properties for the subnodes specifying the input properties + */ +#define CDCE6214_CLK_PRIREF 0 +#define CDCE6214_CLK_SECREF 1 + +/* + * Clock indices for the clocks provided by the CDCE6214. Also used + * as reg properties for the subnodes specifying the output properties + */ +#define CDCE6214_CLK_OUT0 2 +#define CDCE6214_CLK_OUT1 3 +#define CDCE6214_CLK_OUT2 4 +#define CDCE6214_CLK_OUT3 5 +#define CDCE6214_CLK_OUT4 6 +#define CDCE6214_CLK_PLL 7 +#define CDCE6214_CLK_PSA 8 +#define CDCE6214_CLK_PSB 9 + +#endif /* _DT_BINDINGS_CLK_TI_CDCE6214_H */ --=20 2.39.5 From nobody Mon Feb 9 05:00:09 2026 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F25826A08E for ; Tue, 8 Apr 2025 12:00:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744113654; cv=none; b=uChaBC7yb//EQCxXH/lKxW5GJz8DXd8zzgsU7MNtlq5evYC3bRBXVymtQBonOZ8jfGwIo4DaiofnK4zt8Z7txjLDCjLvdDhcGv1oL25D19mH3le5EtscgyUKtG5V4/U7loSuDmVZ46CBvFh9rRhx5Af0ILQ7Fmso6B9pPlxbj+A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744113654; c=relaxed/simple; bh=uURuyUTyytSYMJNGPupFetyuh35vrylqZdU9Re4s1aQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XM1R0QSyNC1ANt+y2g1CB5cmCuB0hAJ58DrpHENPpbypSdQrlB0YLEikkl42pdWKBw95kkb9Bu57H2xmRv54JmV0AUsTjVrM7g00a80kS8XV+q2++StOvw/qDplfnFqFdkoV+GkGIZ9RPI507pS32HTdjKvGhAQ5ZGtt00f6rSE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1u27d0-0000js-Eg; Tue, 08 Apr 2025 14:00:30 +0200 Received: from dude02.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::28]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1u27d0-003vQ2-0F; Tue, 08 Apr 2025 14:00:30 +0200 Received: from localhost ([::1] helo=dude02.red.stw.pengutronix.de) by dude02.red.stw.pengutronix.de with esmtp (Exim 4.96) (envelope-from ) id 1u27cz-00GJS1-39; Tue, 08 Apr 2025 14:00:29 +0200 From: Sascha Hauer Date: Tue, 08 Apr 2025 14:00:24 +0200 Subject: [PATCH 3/3] dt-bindings: clock: add TI CDCE6214 binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250408-clk-cdce6214-v1-3-bd4e7092a91f@pengutronix.de> References: <20250408-clk-cdce6214-v1-0-bd4e7092a91f@pengutronix.de> In-Reply-To: <20250408-clk-cdce6214-v1-0-bd4e7092a91f@pengutronix.de> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kernel@pengutronix.de, =?utf-8?q?Alvin_=C5=A0ipraga?= , Sascha Hauer X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1744113629; l=4324; i=s.hauer@pengutronix.de; s=20230412; h=from:subject:message-id; bh=uURuyUTyytSYMJNGPupFetyuh35vrylqZdU9Re4s1aQ=; b=K4OMnI4y9egZSBvm+YcCLbmzWTT7hfJvzhqG1mLa0W7eEaCKAaxpCqFlVKNXBYBE8eNhDrqKv lk0/7v5kURTDuqaV52EZ4M808ihhoa1fmRdLabo5NHLL1z3pQI+1jCv X-Developer-Key: i=s.hauer@pengutronix.de; a=ed25519; pk=4kuc9ocmECiBJKWxYgqyhtZOHj5AWi7+d0n/UjhkwTg= X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: s.hauer@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org The CDCE6214 is a Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, Two Inputs, and Internal EEPROM. This patch adds the device tree binding for this chip. Signed-off-by: Sascha Hauer --- .../devicetree/bindings/clock/ti,cdce6214.yaml | 157 +++++++++++++++++= ++++ 1 file changed, 157 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/ti,cdce6214.yaml b/Doc= umentation/devicetree/bindings/clock/ti,cdce6214.yaml new file mode 100644 index 0000000000000..63e6c9d9b1771 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/ti,cdce6214.yaml @@ -0,0 +1,157 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,cdce6214.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI CDCE6214 programmable clock generator with PLL + +maintainers: + - Sascha Hauer + +description: | + Ultra-Low Power Clock Generator With One PLL, Four Differential Outputs, + Two Inputs, and Internal EEPROM + + - CDCE6214: https://www.ti.com/product/CDCE6214 + +properties: + compatible: + enum: + - ti,cdce6214 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: priref + - const: secref + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + "#clock-cells": + const: 1 + +patternProperties: + "^clk@[0-1]$": + type: object + description: | + optional child node that can be used to specify input pin parameters= . The reg + properties match the CDCE6214_CLK_* defines. + + additionalProperties: false + + properties: + reg: + description: + clock input identifier. + minimum: 0 + maximum: 1 + + ti,ref-xtal: + type: boolean + description: | + If true use input as XTAL input + + ti,ref-lvcmos: + type: boolean + description: | + If true use input as LVCMOS input + + ti,ref-diff: + type: boolean + description: | + If true use input as differential input + + "^clk@[2-9]$": + type: object + description: | + optional child node that can be used to specify output pin parameter= s. The reg + properties match the CDCE6214_CLK_* defines. + + additionalProperties: false + + properties: + reg: + description: + clock output identifier. + minimum: 2 + maximum: 9 + + ti,lphcsl: + type: boolean + description: | + If true enable LP-HCSL output mode for this clock + + ti,lvds: + type: boolean + description: | + If true enable LVDS output mode for this clock + + ti,cmosp: + type: boolean + description: | + If true enable CMOSP output for this clock + + ti,cmosn: + type: boolean + description: | + If true enable CMOSN output for this clock + +required: + - compatible + - reg + - clocks + - "#clock-cells" + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + clock-generator@67 { + compatible =3D "ti,cdce6214"; + reg =3D <0x67>; + #address-cells =3D <1>; + #size-cells =3D <0>; + #clock-cells =3D <1>; + clocks =3D <&clock_ref25m>; + clock-names =3D "priref"; + + clk@CDCE6214_CLK_SECREF { + reg =3D ; + ti,ref-xtal; + }; + + clk@CDCE6214_CLK_OUT1 { + reg =3D ; + ti,cmosp; + ti,cmosn; + }; + + clk@CDCE6214_CLK_OUT2 { + reg =3D ; + ti,lvds; + }; + + clk@CDCE6214_CLK_OUT4 { + reg =3D ; + ti,cmosp; + ti,cmosn; + }; + }; + }; --=20 2.39.5