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Mon, 07 Apr 2025 12:16:42 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:78b9:80c2:5373:1b49]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c30096bb2sm12994453f8f.12.2025.04.07.12.16.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 12:16:42 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 01/12] dt-bindings: soc: renesas: Document Renesas RZ/V2N SoC variants and EVK Date: Mon, 7 Apr 2025 20:16:17 +0100 Message-ID: <20250407191628.323613-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250407191628.323613-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250407191628.323613-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Document the Renesas RZ/V2N (R9A09G056) SoC variants, distinguishing between configurations with and without specific hardware features such as GPU, ISP, and cryptographic extensions. Also, document the "renesas,rzv2n-evk" compatible string for the RZ/V2N EVK board. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2 - Squashed the RZ/V2N EVK and SoC variant documentation into a single commit. - Updated the commit message. --- .../devicetree/bindings/soc/renesas/renesas.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/D= ocumentation/devicetree/bindings/soc/renesas/renesas.yaml index 6874f425bf1f..92eb99e82465 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -551,6 +551,21 @@ properties: - renesas,r9a09g047e58 # Quad Cortex-A55 + Cortex-M33 + Etho= s-U55 (21mm BGA) - const: renesas,r9a09g047 =20 + - description: RZ/V2N (R9A09G056) + items: + - enum: + - renesas,rzv2n-evk # RZ/V2N EVK + - enum: + - renesas,r9a09g056n41 # RZ/V2N + - renesas,r9a09g056n42 # RZ/V2N with Mali-G31 support + - renesas,r9a09g056n43 # RZ/V2N with Mali-C55 support + - renesas,r9a09g056n44 # RZ/V2N with Mali-G31 + Mali-C55 sup= port + - renesas,r9a09g056n45 # RZ/V2N with cryptographic extension= support + - renesas,r9a09g056n46 # RZ/V2N with Mali-G31 + cryptographi= c extension support + - renesas,r9a09g056n47 # RZ/V2N with Mali-C55 + cryptographi= c extension support + - renesas,r9a09g056n48 # RZ/V2N with Mali-G31 + Mali-C55 + c= ryptographic extension support + - const: renesas,r9a09g056 + - description: RZ/V2H(P) (R9A09G057) items: - enum: --=20 2.49.0 From nobody Fri Dec 19 16:05:39 2025 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFAFB22D795; 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Mon, 07 Apr 2025 12:16:43 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:78b9:80c2:5373:1b49]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c30096bb2sm12994453f8f.12.2025.04.07.12.16.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 12:16:43 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 02/12] soc: renesas: Add config option for RZ/V2N (R9A09G056) SoC Date: Mon, 7 Apr 2025 20:16:18 +0100 Message-ID: <20250407191628.323613-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250407191628.323613-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250407191628.323613-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add a new Kconfig option, ARCH_R9A09G056, to enable ARM64 platform support for the Renesas RZ/V2N SoC. Default this option to "y" when ARCH_RENESAS is enabled, ensuring that support for the RZ/V2N SoC is automatically included. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1-v2: - Selected the SoC by default when ARCH_RENESAS is enabled. - Updated the commit message --- drivers/soc/renesas/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index abf3526a1b69..3fa5ed36d20b 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -393,6 +393,12 @@ config ARCH_R9A09G047 help This enables support for the Renesas RZ/G3E SoC variants. =20 +config ARCH_R9A09G056 + bool "ARM64 Platform support for RZ/V2N" + default y if ARCH_RENESAS + help + This enables support for the Renesas RZ/V2N SoC variants. + config ARCH_R9A09G057 bool "ARM64 Platform support for RZ/V2H(P)" default y if ARCH_RENESAS --=20 2.49.0 From nobody Fri Dec 19 16:05:39 2025 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EECF522FE18; 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charset="utf-8" From: Lad Prabhakar Add the RZ/V2N (R9A09G056) variant to the existing RZ/V2H(P) System Controller (SYS) binding, as both IPs are very similar. However, they have different SoC IDs, and the RZ/V2N does not have PCIE1 configuration registers, unlike the RZ/V2H(P) SYS IP. To handle these differences, introduce a new compatible string `renesas,r9a09g056-sys`. Signed-off-by: Lad Prabhakar Acked-by: Rob Herring (Arm) Reviewed-by: Geert Uytterhoeven --- v1->v2 - Added ack from Rob --- .../devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g05= 7-sys.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g05= 7-sys.yaml index e0f7503a9f35..c41dcaea568a 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.y= aml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r9a09g057-sys.y= aml @@ -25,6 +25,7 @@ properties: items: - enum: - renesas,r9a09g047-sys # RZ/G3E + - renesas,r9a09g056-sys # RZ/V2N - renesas,r9a09g057-sys # RZ/V2H =20 reg: --=20 2.49.0 From nobody Fri Dec 19 16:05:39 2025 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 637F625334C; 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Mon, 07 Apr 2025 12:16:46 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:78b9:80c2:5373:1b49]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c30096bb2sm12994453f8f.12.2025.04.07.12.16.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 12:16:45 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 04/12] soc: renesas: sysc: Add SoC identification for RZ/V2N SoC Date: Mon, 7 Apr 2025 20:16:20 +0100 Message-ID: <20250407191628.323613-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250407191628.323613-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250407191628.323613-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add SoC identification for the RZ/V2N SoC using the System Controller (SYS) block. Signed-off-by: Lad Prabhakar --- v1->v2: - No changes in the code. --- drivers/soc/renesas/Kconfig | 5 ++ drivers/soc/renesas/Makefile | 1 + drivers/soc/renesas/r9a09g056-sys.c | 107 ++++++++++++++++++++++++++++ drivers/soc/renesas/rz-sysc.c | 3 + drivers/soc/renesas/rz-sysc.h | 1 + 5 files changed, 117 insertions(+) create mode 100644 drivers/soc/renesas/r9a09g056-sys.c diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index 3fa5ed36d20b..7f4b4088a14e 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -396,6 +396,7 @@ config ARCH_R9A09G047 config ARCH_R9A09G056 bool "ARM64 Platform support for RZ/V2N" default y if ARCH_RENESAS + select SYS_R9A09G056 help This enables support for the Renesas RZ/V2N SoC variants. =20 @@ -451,6 +452,10 @@ config SYS_R9A09G047 bool "Renesas RZ/G3E System controller support" if COMPILE_TEST select SYSC_RZ =20 +config SYS_R9A09G056 + bool "Renesas RZ/V2N System controller support" if COMPILE_TEST + select SYSC_RZ + config SYS_R9A09G057 bool "Renesas RZ/V2H System controller support" if COMPILE_TEST select SYSC_RZ diff --git a/drivers/soc/renesas/Makefile b/drivers/soc/renesas/Makefile index 81d4c5726e4c..3bdcc6a395d5 100644 --- a/drivers/soc/renesas/Makefile +++ b/drivers/soc/renesas/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_ARCH_R9A06G032) +=3D r9a06g032-smp.o endif obj-$(CONFIG_SYSC_R9A08G045) +=3D r9a08g045-sysc.o obj-$(CONFIG_SYS_R9A09G047) +=3D r9a09g047-sys.o +obj-$(CONFIG_SYS_R9A09G056) +=3D r9a09g056-sys.o obj-$(CONFIG_SYS_R9A09G057) +=3D r9a09g057-sys.o =20 # Family diff --git a/drivers/soc/renesas/r9a09g056-sys.c b/drivers/soc/renesas/r9a0= 9g056-sys.c new file mode 100644 index 000000000000..3bea674c785e --- /dev/null +++ b/drivers/soc/renesas/r9a09g056-sys.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/V2N System controller (SYS) driver + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include + +#include "rz-sysc.h" + +/* Register Offsets */ +#define SYS_LSI_MODE 0x300 +#define SYS_LSI_MODE_SEC_EN BIT(16) +/* + * BOOTPLLCA[1:0] + * [0,0] =3D> 1.1GHZ + * [0,1] =3D> 1.5GHZ + * [1,0] =3D> 1.6GHZ + * [1,1] =3D> 1.7GHZ + */ +#define SYS_LSI_MODE_STAT_BOOTPLLCA55 GENMASK(12, 11) +#define SYS_LSI_MODE_CA55_1_7GHZ 0x3 + +#define SYS_LSI_PRR 0x308 +#define SYS_LSI_PRR_GPU_DIS BIT(0) +#define SYS_LSI_PRR_ISP_DIS BIT(4) + +#define SYS_RZV2N_FEATURE_G31 BIT(0) +#define SYS_RZV2N_FEATURE_C55 BIT(1) +#define SYS_RZV2N_FEATURE_SEC BIT(2) + +static void rzv2n_sys_print_id(struct device *dev, + void __iomem *sysc_base, + struct soc_device_attribute *soc_dev_attr) +{ + unsigned int part_number; + char features[75] =3D ""; + u32 prr_val, mode_val; + u8 feature_flags; + + prr_val =3D readl(sysc_base + SYS_LSI_PRR); + mode_val =3D readl(sysc_base + SYS_LSI_MODE); + + /* Check GPU, ISP and Cryptographic configuration */ + feature_flags =3D !(prr_val & SYS_LSI_PRR_GPU_DIS) ? SYS_RZV2N_FEATURE_G3= 1 : 0; + feature_flags |=3D !(prr_val & SYS_LSI_PRR_ISP_DIS) ? SYS_RZV2N_FEATURE_C= 55 : 0; + feature_flags |=3D (mode_val & SYS_LSI_MODE_SEC_EN) ? SYS_RZV2N_FEATURE_S= EC : 0; + + part_number =3D 41; + if (feature_flags & SYS_RZV2N_FEATURE_G31) + part_number++; + if (feature_flags & SYS_RZV2N_FEATURE_C55) + part_number +=3D 2; + if (feature_flags & SYS_RZV2N_FEATURE_SEC) + part_number +=3D 4; + + if (feature_flags) { + unsigned int features_len =3D sizeof(features); + + strscpy(features, "with "); + if (feature_flags & SYS_RZV2N_FEATURE_G31) + strlcat(features, "GE3D (Mali-G31)", features_len); + + if (feature_flags =3D=3D (SYS_RZV2N_FEATURE_G31 | + SYS_RZV2N_FEATURE_C55 | + SYS_RZV2N_FEATURE_SEC)) + strlcat(features, ", ", features_len); + else if ((feature_flags & SYS_RZV2N_FEATURE_G31) && + (feature_flags & (SYS_RZV2N_FEATURE_C55 | SYS_RZV2N_FEATURE_SEC))) + strlcat(features, " and ", features_len); + + if (feature_flags & SYS_RZV2N_FEATURE_SEC) + strlcat(features, "Cryptographic engine", features_len); + + if ((feature_flags & SYS_RZV2N_FEATURE_SEC) && + (feature_flags & SYS_RZV2N_FEATURE_C55)) + strlcat(features, " and ", features_len); + + if (feature_flags & SYS_RZV2N_FEATURE_C55) + strlcat(features, "ISP (Mali-C55)", features_len); + } + dev_info(dev, "Detected Renesas %s %sn%d Rev %s %s\n", soc_dev_attr->fami= ly, + soc_dev_attr->soc_id, part_number, soc_dev_attr->revision, features); + + /* Check CA55 PLL configuration */ + if (FIELD_GET(SYS_LSI_MODE_STAT_BOOTPLLCA55, mode_val) !=3D SYS_LSI_MODE_= CA55_1_7GHZ) + dev_warn(dev, "CA55 PLL is not set to 1.7GHz\n"); +} + +static const struct rz_sysc_soc_id_init_data rzv2n_sys_soc_id_init_data __= initconst =3D { + .family =3D "RZ/V2N", + .id =3D 0x867d447, + .devid_offset =3D 0x304, + .revision_mask =3D GENMASK(31, 28), + .specific_id_mask =3D GENMASK(27, 0), + .print_id =3D rzv2n_sys_print_id, +}; + +const struct rz_sysc_init_data rzv2n_sys_init_data =3D { + .soc_id_init_data =3D &rzv2n_sys_soc_id_init_data, +}; diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index 14db508f669f..ffa65fb4dade 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -88,6 +88,9 @@ static const struct of_device_id rz_sysc_match[] =3D { #ifdef CONFIG_SYS_R9A09G047 { .compatible =3D "renesas,r9a09g047-sys", .data =3D &rzg3e_sys_init_data= }, #endif +#ifdef CONFIG_SYS_R9A09G056 + { .compatible =3D "renesas,r9a09g056-sys", .data =3D &rzv2n_sys_init_data= }, +#endif #ifdef CONFIG_SYS_R9A09G057 { .compatible =3D "renesas,r9a09g057-sys", .data =3D &rzv2h_sys_init_data= }, #endif diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h index aa83948c5117..56bc047a1bff 100644 --- a/drivers/soc/renesas/rz-sysc.h +++ b/drivers/soc/renesas/rz-sysc.h @@ -42,5 +42,6 @@ struct rz_sysc_init_data { extern const struct rz_sysc_init_data rzg3e_sys_init_data; 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Mon, 07 Apr 2025 12:16:47 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:78b9:80c2:5373:1b49]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c30096bb2sm12994453f8f.12.2025.04.07.12.16.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 12:16:46 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 05/12] dt-bindings: serial: renesas: Document RZ/V2N SCIF Date: Mon, 7 Apr 2025 20:16:21 +0100 Message-ID: <20250407191628.323613-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250407191628.323613-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250407191628.323613-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Document SCIF bindings for the Renesas RZ/V2N (a.k.a R9A09G056) SoC. The SCIF interface in Renesas RZ/V2N is identical to the one available in RZ/V2H(P), so `renesas,scif-r9a09g057` will be used as a fallback, allowing reuse of the existing driver without modifications. Signed-off-by: Lad Prabhakar Acked-by: Rob Herring (Arm) Reviewed-by: Geert Uytterhoeven --- v1->v2 - Added ack from Rob --- Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/D= ocumentation/devicetree/bindings/serial/renesas,scif.yaml index 8e82999e6acb..24819b204ebf 100644 --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml @@ -86,6 +86,7 @@ properties: - items: - enum: - renesas,scif-r9a09g047 # RZ/G3E + - renesas,scif-r9a09g056 # RZ/V2N - const: renesas,scif-r9a09g057 # RZ/V2H fallback =20 reg: --=20 2.49.0 From nobody Fri Dec 19 16:05:39 2025 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 135122566E2; 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charset="utf-8" From: Lad Prabhakar Document the device tree bindings for the Renesas RZ/V2N (R9A09G056) SoC Clock Pulse Generator (CPG). Update `renesas,rzv2h-cpg.yaml` to include the compatible string for RZ/V2N SoC and adjust the title and description accordingly. Additionally, introduce `renesas,r9a09g056-cpg.h` to define core clock constants for the RZ/V2N SoC. Note the existing RZ/V2H(P) family-specific clock driver will be reused for this SoC. Signed-off-by: Lad Prabhakar Acked-by: Rob Herring (Arm) Reviewed-by: Geert Uytterhoeven --- v1->v2 - Added ack from Rob --- .../bindings/clock/renesas,rzv2h-cpg.yaml | 5 ++-- .../dt-bindings/clock/renesas,r9a09g056-cpg.h | 24 +++++++++++++++++++ 2 files changed, 27 insertions(+), 2 deletions(-) create mode 100644 include/dt-bindings/clock/renesas,r9a09g056-cpg.h diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml= b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml index c3fe76abd549..f261445bf341 100644 --- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml @@ -4,13 +4,13 @@ $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# =20 -title: Renesas RZ/{G3E,V2H(P)} Clock Pulse Generator (CPG) +title: Renesas RZ/{G3E,V2H(P),V2N} Clock Pulse Generator (CPG) =20 maintainers: - Lad Prabhakar =20 description: - On Renesas RZ/{G3E,V2H(P)} SoCs, the CPG (Clock Pulse Generator) handles + On Renesas RZ/{G3E,V2H(P),V2N} SoCs, the CPG (Clock Pulse Generator) han= dles generation and control of clock signals for the IP modules, generation a= nd control of resets, and control over booting, low power consumption and p= ower supply domains. @@ -19,6 +19,7 @@ properties: compatible: enum: - renesas,r9a09g047-cpg # RZ/G3E + - renesas,r9a09g056-cpg # RZ/V2N - renesas,r9a09g057-cpg # RZ/V2H =20 reg: diff --git a/include/dt-bindings/clock/renesas,r9a09g056-cpg.h b/include/dt= -bindings/clock/renesas,r9a09g056-cpg.h new file mode 100644 index 000000000000..f4905b27f8d9 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a09g056-cpg.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ + +#include + +/* Core Clock list */ +#define R9A09G056_SYS_0_PCLK 0 +#define R9A09G056_CA55_0_CORE_CLK0 1 +#define R9A09G056_CA55_0_CORE_CLK1 2 +#define R9A09G056_CA55_0_CORE_CLK2 3 +#define R9A09G056_CA55_0_CORE_CLK3 4 +#define R9A09G056_CA55_0_PERIPHCLK 5 +#define R9A09G056_CM33_CLK0 6 +#define R9A09G056_CST_0_SWCLKTCK 7 +#define R9A09G056_IOTOP_0_SHCLK 8 +#define R9A09G056_USB2_0_CLK_CORE0 9 +#define R9A09G056_GBETH_0_CLK_PTP_REF_I 10 +#define R9A09G056_GBETH_1_CLK_PTP_REF_I 11 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G056_CPG_H__ */ --=20 2.49.0 From nobody Fri Dec 19 16:05:39 2025 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F5452571DD; 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charset="utf-8" From: Lad Prabhakar Reorder the compatible entries in `rzv2h_cpg_match[]` to follow a numerical sequence based on the SoC part numbers. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2: - No changes in the code. --- drivers/clk/renesas/rzv2h-cpg.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cp= g.c index 3b4f520df627..37fca3b6bde7 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -1363,17 +1363,17 @@ static int __init rzv2h_cpg_probe(struct platform_d= evice *pdev) } =20 static const struct of_device_id rzv2h_cpg_match[] =3D { -#ifdef CONFIG_CLK_R9A09G057 - { - .compatible =3D "renesas,r9a09g057-cpg", - .data =3D &r9a09g057_cpg_info, - }, -#endif #ifdef CONFIG_CLK_R9A09G047 { .compatible =3D "renesas,r9a09g047-cpg", .data =3D &r9a09g047_cpg_info, }, +#endif +#ifdef CONFIG_CLK_R9A09G057 + { + .compatible =3D "renesas,r9a09g057-cpg", + .data =3D &r9a09g057_cpg_info, + }, #endif { /* sentinel */ } }; --=20 2.49.0 From nobody Fri Dec 19 16:05:39 2025 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 891492571AB; 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Mon, 07 Apr 2025 12:16:50 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:78b9:80c2:5373:1b49]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c30096bb2sm12994453f8f.12.2025.04.07.12.16.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 12:16:50 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 08/12] clk: renesas: rzv2h: Add support for RZ/V2N SoC Date: Mon, 7 Apr 2025 20:16:24 +0100 Message-ID: <20250407191628.323613-9-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250407191628.323613-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250407191628.323613-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar The clock structure for RZ/V2N is almost identical to RZ/V2H(P) SoC with less IP blocks compared to RZ/V2H(P). For eg: CRU2/3 are present only on the RZ/V2H(P) SoC. Add minimal clock and reset entries required to boot the Renesas RZ/V2N EVK and binds it with the RZ/V2H CPG family driver. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2: - No changes in the code. --- drivers/clk/renesas/Kconfig | 5 + drivers/clk/renesas/Makefile | 1 + drivers/clk/renesas/r9a09g056-cpg.c | 152 ++++++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.c | 6 ++ drivers/clk/renesas/rzv2h-cpg.h | 1 + 5 files changed, 165 insertions(+) create mode 100644 drivers/clk/renesas/r9a09g056-cpg.c diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 3f9c4deb4c25..45f9ae5b6ef1 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -41,6 +41,7 @@ config CLK_RENESAS select CLK_R9A08G045 if ARCH_R9A08G045 select CLK_R9A09G011 if ARCH_R9A09G011 select CLK_R9A09G047 if ARCH_R9A09G047 + select CLK_R9A09G056 if ARCH_R9A09G056 select CLK_R9A09G057 if ARCH_R9A09G057 select CLK_R9A09G077 if ARCH_R9A09G077 select CLK_SH73A0 if ARCH_SH73A0 @@ -200,6 +201,10 @@ config CLK_R9A09G047 bool "RZ/G3E clock support" if COMPILE_TEST select CLK_RZV2H =20 +config CLK_R9A09G056 + bool "RZ/V2N clock support" if COMPILE_TEST + select CLK_RZV2H + config CLK_R9A09G057 bool "RZ/V2H(P) clock support" if COMPILE_TEST select CLK_RZV2H diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index 3989515dfec3..59e1a4489d18 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_CLK_R9A07G054) +=3D r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A08G045) +=3D r9a08g045-cpg.o obj-$(CONFIG_CLK_R9A09G011) +=3D r9a09g011-cpg.o obj-$(CONFIG_CLK_R9A09G047) +=3D r9a09g047-cpg.o +obj-$(CONFIG_CLK_R9A09G056) +=3D r9a09g056-cpg.o obj-$(CONFIG_CLK_R9A09G057) +=3D r9a09g057-cpg.o obj-$(CONFIG_CLK_SH73A0) +=3D clk-sh73a0.o =20 diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a0= 9g056-cpg.c new file mode 100644 index 000000000000..e2712a25c43a --- /dev/null +++ b/drivers/clk/renesas/r9a09g056-cpg.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/V2N CPG driver + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#include + +#include "rzv2h-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK =3D R9A09G056_GBETH_1_CLK_PTP_REF_I, + + /* External Input Clocks */ + CLK_AUDIO_EXTAL, + CLK_RTXIN, + CLK_QEXTAL, + + /* PLL Clocks */ + CLK_PLLCM33, + CLK_PLLCLN, + CLK_PLLDTY, + CLK_PLLCA55, + + /* Internal Core Clocks */ + CLK_PLLCM33_DIV16, + CLK_PLLCLN_DIV2, + CLK_PLLCLN_DIV8, + CLK_PLLDTY_ACPU, + CLK_PLLDTY_ACPU_DIV4, + + /* Module Clocks */ + MOD_CLK_BASE, +}; + +static const struct clk_div_table dtable_1_8[] =3D { + {0, 1}, + {1, 2}, + {2, 4}, + {3, 8}, + {0, 0}, +}; + +static const struct clk_div_table dtable_2_64[] =3D { + {0, 2}, + {1, 4}, + {2, 8}, + {3, 16}, + {4, 64}, + {0, 0}, +}; + +static const struct cpg_core_clk r9a09g056_core_clks[] __initconst =3D { + /* External Clock Inputs */ + DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), + DEF_INPUT("rtxin", CLK_RTXIN), + DEF_INPUT("qextal", CLK_QEXTAL), + + /* PLL Clocks */ + DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), + DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), + DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), + DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), + + /* Internal Core Clocks */ + DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), + + DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), + DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), + + DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dta= ble_2_64), + DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, = 4), + + /* Core Clocks */ + DEF_FIXED("sys_0_pclk", R9A09G056_SYS_0_PCLK, CLK_QEXTAL, 1, 1), + DEF_DDIV("ca55_0_coreclk0", R9A09G056_CA55_0_CORE_CLK0, CLK_PLLCA55, + CDDIV1_DIVCTL0, dtable_1_8), + DEF_DDIV("ca55_0_coreclk1", R9A09G056_CA55_0_CORE_CLK1, CLK_PLLCA55, + CDDIV1_DIVCTL1, dtable_1_8), + DEF_DDIV("ca55_0_coreclk2", R9A09G056_CA55_0_CORE_CLK2, CLK_PLLCA55, + CDDIV1_DIVCTL2, dtable_1_8), + DEF_DDIV("ca55_0_coreclk3", R9A09G056_CA55_0_CORE_CLK3, CLK_PLLCA55, + CDDIV1_DIVCTL3, dtable_1_8), + DEF_FIXED("iotop_0_shclk", R9A09G056_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1,= 1), +}; + +static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst =3D { + DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, + BUS_MSTOP(3, BIT(5))), + DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, + BUS_MSTOP(3, BIT(14))), + DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, + BUS_MSTOP(8, BIT(2))), + DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, + BUS_MSTOP(8, BIT(2))), + DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5, + BUS_MSTOP(8, BIT(2))), + DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6, + BUS_MSTOP(8, BIT(2))), + DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7, + BUS_MSTOP(8, BIT(3))), + DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8, + BUS_MSTOP(8, BIT(3))), + DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9, + BUS_MSTOP(8, BIT(3))), + DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10, + BUS_MSTOP(8, BIT(3))), + DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11, + BUS_MSTOP(8, BIT(4))), + DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12, + BUS_MSTOP(8, BIT(4))), + DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13, + BUS_MSTOP(8, BIT(4))), + DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, + BUS_MSTOP(8, BIT(4))), +}; + +static const struct rzv2h_reset r9a09g056_resets[] __initconst =3D { + DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ + DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ + DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ + DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ + DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ + DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ + DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ +}; + +const struct rzv2h_cpg_info r9a09g056_cpg_info __initconst =3D { + /* Core Clocks */ + .core_clks =3D r9a09g056_core_clks, + .num_core_clks =3D ARRAY_SIZE(r9a09g056_core_clks), + .last_dt_core_clk =3D LAST_DT_CORE_CLK, + .num_total_core_clks =3D MOD_CLK_BASE, + + /* Module Clocks */ + .mod_clks =3D r9a09g056_mod_clks, + .num_mod_clks =3D ARRAY_SIZE(r9a09g056_mod_clks), + .num_hw_mod_clks =3D 25 * 16, + + /* Resets */ + .resets =3D r9a09g056_resets, + .num_resets =3D ARRAY_SIZE(r9a09g056_resets), + + .num_mstop_bits =3D 192, +}; diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cp= g.c index 37fca3b6bde7..59df9a56c22b 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -1369,6 +1369,12 @@ static const struct of_device_id rzv2h_cpg_match[] = =3D { .data =3D &r9a09g047_cpg_info, }, #endif +#ifdef CONFIG_CLK_R9A09G056 + { + .compatible =3D "renesas,r9a09g056-cpg", + .data =3D &r9a09g056_cpg_info, + }, +#endif #ifdef CONFIG_CLK_R9A09G057 { .compatible =3D "renesas,r9a09g057-cpg", diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cp= g.h index d0678ff1c7cb..50e09fd6bbf6 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -339,6 +339,7 @@ struct rzv2h_cpg_info { }; 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charset="utf-8" From: Lad Prabhakar Add documentation for the pin controller found on the Renesas RZ/V2N (R9A09G056) SoC. The RZ/V2N PFC differs slightly from the RZ/G2L family and is almost identical to the RZ/V2H(P) SoC, except that the RZ/V2H(P) SoC has an additional dedicated pin. To account for this, a SoC-specific compatible string, 'renesas,r9a09g056-pinctrl', is introduced for the RZ/V2N SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2: - Dropped `renesas,r9a09g056-pinctrl.h` header file. --- .../devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctr= l.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.ya= ml index 768bb3c2b456..5156d54b240b 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -27,6 +27,7 @@ properties: - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - renesas,r9a08g045-pinctrl # RZ/G3S - renesas,r9a09g047-pinctrl # RZ/G3E + - renesas,r9a09g056-pinctrl # RZ/V2N - renesas,r9a09g057-pinctrl # RZ/V2H(P) =20 - items: @@ -145,6 +146,7 @@ allOf: contains: enum: - renesas,r9a09g047-pinctrl + - renesas,r9a09g056-pinctrl - renesas,r9a09g057-pinctrl then: properties: --=20 2.49.0 From nobody Fri Dec 19 16:05:39 2025 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBE0F2580FA; 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charset="utf-8" From: Lad Prabhakar Add pinctrl support for the Renesas RZ/V2N SoC by reusing the existing RZ/V2H(P) pin configuration data. The PFC block is nearly identical, with the only difference being the absence of `PCIE1_RSTOUTB` on RZ/V2N. To accommodate this, move the `PCIE1_RSTOUTB` entry to the end of the `rzv2h_dedicated_pins` array and set `.n_dedicated_pins` to `ARRAY_SIZE(rzv2h_dedicated_pins) - 1` in the RZ/V2N OF data. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2: - No changes in the code. --- drivers/pinctrl/renesas/Kconfig | 1 + drivers/pinctrl/renesas/pinctrl-rzg2l.c | 36 ++++++++++++++++++++++++- 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kcon= fig index 3c18d908b21e..e16034fc1bbf 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -42,6 +42,7 @@ config PINCTRL_RENESAS select PINCTRL_RZG2L if ARCH_RZG2L select PINCTRL_RZV2M if ARCH_R9A09G011 select PINCTRL_RZG2L if ARCH_R9A09G047 + select PINCTRL_RZG2L if ARCH_R9A09G056 select PINCTRL_RZG2L if ARCH_R9A09G057 select PINCTRL_PFC_SH7203 if CPU_SUBTYPE_SH7203 select PINCTRL_PFC_SH7264 if CPU_SUBTYPE_SH7264 diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index c72e250f4a15..ae5e040f3276 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -2304,7 +2304,6 @@ static struct rzg2l_dedicated_configs rzv2h_dedicated= _pins[] =3D { { "SD1DAT3", RZG2L_SINGLE_PIN_PACK(0xc, 3, (PIN_CFG_IOLH_RZV2H | PIN_CFG_= SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, { "PCIE0_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 0, (PIN_CFG_IOLH_RZV2H | PI= N_CFG_SR)) }, - { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PI= N_CFG_SR)) }, { "ET0_MDIO", RZG2L_SINGLE_PIN_PACK(0xf, 0, (PIN_CFG_IOLH_RZV2H | PIN_CFG= _SR | PIN_CFG_IEN | PIN_CFG_PUPD)) }, { "ET0_MDC", RZG2L_SINGLE_PIN_PACK(0xf, 1, (PIN_CFG_IOLH_RZV2H | PIN_CFG_= SR | @@ -2359,6 +2358,14 @@ static struct rzg2l_dedicated_configs rzv2h_dedicate= d_pins[] =3D { { "ET1_RXD1", RZG2L_SINGLE_PIN_PACK(0x14, 5, (PIN_CFG_PUPD)) }, { "ET1_RXD2", RZG2L_SINGLE_PIN_PACK(0x14, 6, (PIN_CFG_PUPD)) }, { "ET1_RXD3", RZG2L_SINGLE_PIN_PACK(0x14, 7, (PIN_CFG_PUPD)) }, + + /* + * This pin is only available on the RZ/V2H(P) SoC and not on the RZ/V2N. + * Since this array is shared with the RZ/V2N SoC, this entry should be p= laced + * at the end. This ensures that on the RZ/V2N, we can set + * `.n_dedicated_pins =3D ARRAY_SIZE(rzv2h_dedicated_pins) - 1,`. + */ + { "PCIE1_RSTOUTB", RZG2L_SINGLE_PIN_PACK(0xe, 1, (PIN_CFG_IOLH_RZV2H | PI= N_CFG_SR)) }, }; =20 static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] =3D { @@ -3349,6 +3356,29 @@ static struct rzg2l_pinctrl_data r9a09g047_data =3D { .bias_param_to_hw =3D &rzv2h_bias_param_to_hw, }; =20 +static struct rzg2l_pinctrl_data r9a09g056_data =3D { + .port_pins =3D rzv2h_gpio_names, + .port_pin_configs =3D r9a09g057_gpio_configs, + .n_ports =3D ARRAY_SIZE(r9a09g057_gpio_configs), + .dedicated_pins =3D rzv2h_dedicated_pins, + .n_port_pins =3D ARRAY_SIZE(r9a09g057_gpio_configs) * RZG2L_PINS_PER_PORT, + .n_dedicated_pins =3D ARRAY_SIZE(rzv2h_dedicated_pins) - 1, + .hwcfg =3D &rzv2h_hwcfg, + .variable_pin_cfg =3D r9a09g057_variable_pin_cfg, + .n_variable_pin_cfg =3D ARRAY_SIZE(r9a09g057_variable_pin_cfg), + .num_custom_params =3D ARRAY_SIZE(renesas_rzv2h_custom_bindings), + .custom_params =3D renesas_rzv2h_custom_bindings, +#ifdef CONFIG_DEBUG_FS + .custom_conf_items =3D renesas_rzv2h_conf_items, +#endif + .pwpr_pfc_lock_unlock =3D &rzv2h_pwpr_pfc_lock_unlock, + .pmc_writeb =3D &rzv2h_pmc_writeb, + .oen_read =3D &rzv2h_oen_read, + .oen_write =3D &rzv2h_oen_write, + .hw_to_bias_param =3D &rzv2h_hw_to_bias_param, + .bias_param_to_hw =3D &rzv2h_bias_param_to_hw, +}; + static struct rzg2l_pinctrl_data r9a09g057_data =3D { .port_pins =3D rzv2h_gpio_names, .port_pin_configs =3D r9a09g057_gpio_configs, @@ -3389,6 +3419,10 @@ static const struct of_device_id rzg2l_pinctrl_of_ta= ble[] =3D { .compatible =3D "renesas,r9a09g047-pinctrl", .data =3D &r9a09g047_data, }, + { + .compatible =3D "renesas,r9a09g056-pinctrl", + .data =3D &r9a09g056_data, + }, { .compatible =3D "renesas,r9a09g057-pinctrl", .data =3D &r9a09g057_data, --=20 2.49.0 From nobody Fri Dec 19 16:05:39 2025 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B1B62586EA; Mon, 7 Apr 2025 19:16:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744053418; cv=none; b=bDx14lavW/NauJ/2T4eibXWYBsCFWn0FtGPQu7+nQRlCYx1jpL/1RmrsabBeNQStne87J41kVPoX/PzS78JN2yGTFesMY1uJTbVTPwJ7RKJIhr7W+wx2386jedIZ757LbDhaFiRfUmzDeEUCVAarLRNG4YQsBRQQFM8ChRwcG58= ARC-Message-Signature: i=1; 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Mon, 07 Apr 2025 12:16:54 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:78b9:80c2:5373:1b49]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c30096bb2sm12994453f8f.12.2025.04.07.12.16.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 12:16:53 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 11/12] arm64: dts: renesas: Add initial SoC DTSI for RZ/V2N Date: Mon, 7 Apr 2025 20:16:27 +0100 Message-ID: <20250407191628.323613-12-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250407191628.323613-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250407191628.323613-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add the initial Device Tree Source Include (DTSI) file for the Renesas RZ/V2N (R9A09G056) SoC. Include support for the following components: - CPU (Cortex-A55 cores with operating points) - External clocks (audio, qextal, rtxin) - Pin controller (GPIO support) - Clock Pulse Generator (CPG) - System controller (SYS) - Serial Communication Interface (SCIF) - Secure Digital Host Interface (SDHI 0/1/2) - Generic Interrupt Controller (GIC) - ARMv8 timer Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2: - Added RZV2N_Px, RZV2N_PORT_PINMUX, and RZV2N_GPIO macros in SoC DTSI as we are re-using renesas,r9a09g057-pinctrl.h in pictrl driver hence to keep the consistency with the RZ/V2H(P) SoC these macros are added. --- arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 282 +++++++++++++++++++++ 1 file changed, 282 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g056.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/d= ts/renesas/r9a09g056.dtsi new file mode 100644 index 000000000000..90964bd864cc --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2N SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include +#include +#include + +/* RZV2N_Px =3D Offset address of PFC_P_mn - 0x20 */ +#define RZV2N_P0 0 +#define RZV2N_P1 1 +#define RZV2N_P2 2 +#define RZV2N_P3 3 +#define RZV2N_P4 4 +#define RZV2N_P5 5 +#define RZV2N_P6 6 +#define RZV2N_P7 7 +#define RZV2N_P8 8 +#define RZV2N_P9 9 +#define RZV2N_PA 10 +#define RZV2N_PB 11 + +#define RZV2N_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZV2N_P##b, p, f) +#define RZV2N_GPIO(port, pin) RZG2L_GPIO(RZV2N_P##port, pin) + +/ { + compatible =3D "renesas,r9a09g056"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + audio_extal_clk: audio-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + /* + * The default cluster table is based on the assumption that the PLLCA55 = clock + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally = can be + * clocked to 1.8GHz as well). The table below should be overridden in th= e board + * DTS based on the PLLCA55 clock frequency. + */ + cluster0_opp: opp-table-0 { + compatible =3D "operating-points-v2"; + + opp-1700000000 { + opp-hz =3D /bits/ 64 <1700000000>; + opp-microvolt =3D <900000>; + clock-latency-ns =3D <300000>; + }; + opp-850000000 { + opp-hz =3D /bits/ 64 <850000000>; + opp-microvolt =3D <800000>; + clock-latency-ns =3D <300000>; + }; + opp-425000000 { + opp-hz =3D /bits/ 64 <425000000>; + opp-microvolt =3D <800000>; + clock-latency-ns =3D <300000>; + }; + opp-212500000 { + opp-hz =3D /bits/ 64 <212500000>; + opp-microvolt =3D <800000>; + clock-latency-ns =3D <300000>; + opp-suspend; + }; + }; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a55"; + reg =3D <0>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>; + operating-points-v2 =3D <&cluster0_opp>; + }; + + cpu1: cpu@100 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x100>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>; + operating-points-v2 =3D <&cluster0_opp>; + }; + + cpu2: cpu@200 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x200>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>; + operating-points-v2 =3D <&cluster0_opp>; + }; + + cpu3: cpu@300 { + compatible =3D "arm,cortex-a55"; + reg =3D <0x300>; + device_type =3D "cpu"; + next-level-cache =3D <&L3_CA55>; + enable-method =3D "psci"; + clocks =3D <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>; + operating-points-v2 =3D <&cluster0_opp>; + }; + + L3_CA55: cache-controller-0 { + compatible =3D "cache"; + cache-unified; + cache-size =3D <0x100000>; + cache-level =3D <3>; + }; + }; + + psci { + compatible =3D "arm,psci-1.0", "arm,psci-0.2"; + method =3D "smc"; + }; + + qextal_clk: qextal-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + rtxin_clk: rtxin-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by the board */ + clock-frequency =3D <0>; + }; + + soc: soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + pinctrl: pinctrl@10410000 { + compatible =3D "renesas,r9a09g056-pinctrl"; + reg =3D <0 0x10410000 0 0x10000>; + clocks =3D <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pinctrl 0 0 96>; + power-domains =3D <&cpg>; + resets =3D <&cpg 0xa5>, <&cpg 0xa6>; + }; + + cpg: clock-controller@10420000 { + compatible =3D "renesas,r9a09g056-cpg"; + reg =3D <0 0x10420000 0 0x10000>; + clocks =3D <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; + clock-names =3D "audio_extal", "rtxin", "qextal"; + #clock-cells =3D <2>; + #reset-cells =3D <1>; + #power-domain-cells =3D <0>; + }; + + sys: system-controller@10430000 { + compatible =3D "renesas,r9a09g056-sys"; + reg =3D <0 0x10430000 0 0x10000>; + clocks =3D <&cpg CPG_CORE R9A09G056_SYS_0_PCLK>; + resets =3D <&cpg 0x30>; + }; + + scif: serial@11c01400 { + compatible =3D "renesas,scif-r9a09g056", + "renesas,scif-r9a09g057"; + reg =3D <0 0x11c01400 0 0x400>; + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "eri", "rxi", "txi", "bri", "dri", + "tei", "tei-dri", "rxi-edge", "txi-edge"; + clocks =3D <&cpg CPG_MOD 0x8f>; + clock-names =3D "fck"; + power-domains =3D <&cpg>; + resets =3D <&cpg 0x95>; + status =3D "disabled"; + }; + + gic: interrupt-controller@14900000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x14900000 0 0x20000>, + <0x0 0x14940000 0 0x80000>; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupt-controller; + interrupts =3D ; + }; + + sdhi0: mmc@15c00000 { + compatible =3D "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; + reg =3D <0x0 0x15c00000 0 0x10000>; + interrupts =3D , + ; + clocks =3D <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, + <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; + clock-names =3D "core", "clkh", "cd", "aclk"; + resets =3D <&cpg 0xa7>; + power-domains =3D <&cpg>; + status =3D "disabled"; + + sdhi0_vqmmc: vqmmc-regulator { + regulator-name =3D "SDHI0-VQMMC"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + status =3D "disabled"; + }; + }; + + sdhi1: mmc@15c10000 { + compatible =3D "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; + reg =3D <0x0 0x15c10000 0 0x10000>; + interrupts =3D , + ; + clocks =3D <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, + <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; + clock-names =3D "core", "clkh", "cd", "aclk"; + resets =3D <&cpg 0xa8>; + power-domains =3D <&cpg>; + status =3D "disabled"; + + sdhi1_vqmmc: vqmmc-regulator { + regulator-name =3D "SDHI1-VQMMC"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + status =3D "disabled"; + }; + }; + + sdhi2: mmc@15c20000 { + compatible =3D "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; + reg =3D <0x0 0x15c20000 0 0x10000>; + interrupts =3D , + ; + clocks =3D <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, + <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; + clock-names =3D "core", "clkh", "cd", "aclk"; + resets =3D <&cpg 0xa9>; + power-domains =3D <&cpg>; + status =3D "disabled"; + + sdhi2_vqmmc: vqmmc-regulator { + regulator-name =3D "SDHI2-VQMMC"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + status =3D "disabled"; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts-extended =3D <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names =3D "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; +}; --=20 2.49.0 From nobody Fri Dec 19 16:05:39 2025 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BA1F258CF3; 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Mon, 07 Apr 2025 12:16:55 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:78b9:80c2:5373:1b49]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c30096bb2sm12994453f8f.12.2025.04.07.12.16.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 12:16:54 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Linus Walleij , Greg Kroah-Hartman , Jiri Slaby , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 12/12] arm64: dts: renesas: Add initial device tree for RZ/V2N EVK Date: Mon, 7 Apr 2025 20:16:28 +0100 Message-ID: <20250407191628.323613-13-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250407191628.323613-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250407191628.323613-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add the initial device tree for the Renesas RZ/V2N EVK board, based on the R9A09G056N48 SoC. Enable basic board functionality, including: - Memory mapping (reserve the first 128MB for the secure area) - Clock inputs (QEXTAL, RTXIN, AUDIO_EXTAL) - PINCTRL configurations for peripherals - Serial console (SCIF) - SDHI1 with power control and UHS modes Update the Makefile to include the new DTB. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1->v2 - Followed DTS coding style guidelines --- arch/arm64/boot/dts/renesas/Makefile | 2 + .../dts/renesas/r9a09g056n48-rzv2n-evk.dts | 114 ++++++++++++++++++ 2 files changed, 116 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/ren= esas/Makefile index 5b99c337763a..ea7f93b7d2b3 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -152,6 +152,8 @@ dtb-$(CONFIG_ARCH_R9A09G011) +=3D r9a09g011-v2mevk2.dtb =20 dtb-$(CONFIG_ARCH_R9A09G047) +=3D r9a09g047e57-smarc.dtb =20 +dtb-$(CONFIG_ARCH_R9A09G056) +=3D r9a09g056n48-rzv2n-evk.dtb + dtb-$(CONFIG_ARCH_R9A09G057) +=3D r9a09g057h44-rzv2h-evk.dtb dtb-$(CONFIG_ARCH_R9A09G057) +=3D r9a09g057h48-kakip.dtb =20 diff --git a/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts b/arch/= arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts new file mode 100644 index 000000000000..f379871c39cc --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2N EVK board + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include +#include "r9a09g056.dtsi" + +/ { + model =3D "Renesas RZ/V2N EVK Board based on r9a09g056n48"; + compatible =3D "renesas,rzv2n-evk", "renesas,r9a09g056n48", "renesas,r9a0= 9g056"; + + aliases { + mmc1 =3D &sdhi1; + serial0 =3D &scif; + }; + + chosen { + bootargs =3D "ignore_loglevel"; + stdout-path =3D "serial0:115200n8"; + }; + + memory@48000000 { + device_type =3D "memory"; + /* first 128MB is reserved for secure area. */ + reg =3D <0x0 0x48000000 0x1 0xf8000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed-3.3V"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vqmmc_sdhi1: regulator-vqmmc-sdhi1 { + compatible =3D "regulator-gpio"; + regulator-name =3D "SDHI1 VqmmC"; + gpios =3D <&pinctrl RZV2N_GPIO(A, 2) GPIO_ACTIVE_HIGH>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + gpios-states =3D <0>; + states =3D <3300000 0>, <1800000 1>; + }; +}; + +&audio_extal_clk { + clock-frequency =3D <22579200>; +}; + +&pinctrl { + scif_pins: scif { + pins =3D "SCIF_TXD", "SCIF_RXD"; + renesas,output-impedance =3D <1>; + }; + + sd1-pwr-en-hog { + gpio-hog; + gpios =3D ; + output-high; + line-name =3D "sd1_pwr_en"; + }; + + sdhi1_pins: sd1 { + sd1-dat-cmd { + pins =3D "SD1DAT0", "SD1DAT1", "SD1DAT2", "SD1DAT3", "SD1CMD"; + input-enable; + renesas,output-impedance =3D <3>; + slew-rate =3D <0>; + }; + + sd1-clk { + pins =3D "SD1CLK"; + renesas,output-impedance =3D <3>; + slew-rate =3D <0>; + }; + + sd1-cd { + pinmux =3D ; /* SD1_CD */ + }; + }; +}; + +&qextal_clk { + clock-frequency =3D <24000000>; +}; + +&rtxin_clk { + clock-frequency =3D <32768>; +}; + +&scif { + pinctrl-0 =3D <&scif_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&sdhi1 { + pinctrl-0 =3D <&sdhi1_pins>; + pinctrl-1 =3D <&sdhi1_pins>; + pinctrl-names =3D "default", "state_uhs"; + vmmc-supply =3D <®_3p3v>; + vqmmc-supply =3D <&vqmmc_sdhi1>; + bus-width =3D <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status =3D "okay"; +}; --=20 2.49.0