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Mon, 07 Apr 2025 09:52:22 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:78b9:80c2:5373:1b49]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec16ba978sm139272305e9.23.2025.04.07.09.52.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 09:52:22 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 6/9] clk: renesas: rzv2h-cpg: Ignore monitoring CLK_MON bits for external clocks Date: Mon, 7 Apr 2025 17:51:59 +0100 Message-ID: <20250407165202.197570-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250407165202.197570-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250407165202.197570-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Ignore CLK_MON bits when turning on/off module clocks that use an external clock source. Introduce the `DEF_MOD_EXTERNAL()` macro for defining module clocks that may have an external clock source. Update `rzv2h_cpg_register_mod_clk()` to update mon_index. Signed-off-by: Lad Prabhakar --- drivers/clk/renesas/rzv2h-cpg.c | 24 ++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 28 ++++++++++++++++++++++++---- 2 files changed, 48 insertions(+), 4 deletions(-) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cp= g.c index c75ed6ed087b..dca0940b3df9 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -569,6 +569,25 @@ static void rzv2h_mod_clock_mstop_disable(struct rzv2h= _cpg_priv *priv, spin_unlock_irqrestore(&priv->rmw_lock, flags); } =20 +static bool rzv2h_mod_clock_is_external(struct rzv2h_cpg_priv *priv, + u16 ext_clk_offset, + u8 ext_clk_bit, + u8 ext_cond) +{ + u32 value; + + if (!ext_clk_offset) + return false; + + value =3D readl(priv->base + ext_clk_offset) & BIT(ext_clk_bit); + value >>=3D ext_clk_bit; + + if (value =3D=3D ext_cond) + return true; + + return false; +} + static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw) { struct mod_clock *clock =3D to_mod_clock(hw); @@ -691,6 +710,11 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk = *mod, clock->on_index =3D mod->on_index; clock->on_bit =3D mod->on_bit; clock->mon_index =3D mod->mon_index; + /* If clock is coming from external source ignore the monitor bit for it = */ + if (rzv2h_mod_clock_is_external(priv, mod->external_clk_offset, + mod->external_clk_bit, + mod->external_cond)) + clock->mon_index =3D -1; clock->mon_bit =3D mod->mon_bit; clock->no_pm =3D mod->no_pm; clock->priv =3D priv; diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cp= g.h index 97054f207113..c64cfead6dc1 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -192,6 +192,10 @@ enum clk_types { * @on_bit: ON bit * @mon_index: monitor register index * @mon_bit: monitor bit + * @external_clk_offset: Offset to check to determine if the clock is exte= rnal + * @external_clk_bit: Bit to check to determine if the clock is external + * @external_cond: Condition to determine whether a given clock source is = external; + * it can be either 0 or 1. */ struct rzv2h_mod_clk { const char *name; @@ -203,9 +207,14 @@ struct rzv2h_mod_clk { u8 on_bit; s8 mon_index; u8 mon_bit; + u16 external_clk_offset:10; + u8 external_clk_bit:5; + u8 external_cond:1; }; =20 -#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, = _onbit, _monindex, _monbit) \ +#define DEF_MOD_BASE(_name, _mstop, _parent, _critical, _no_pm, _onindex, \ + _onbit, _monindex, _monbit, _external_clk_offset, \ + _external_clk_bit, _external_cond) \ { \ .name =3D (_name), \ .mstop_data =3D (_mstop), \ @@ -216,16 +225,27 @@ struct rzv2h_mod_clk { .on_bit =3D (_onbit), \ .mon_index =3D (_monindex), \ .mon_bit =3D (_monbit), \ + .external_clk_offset =3D (_external_clk_offset), \ + .external_clk_bit =3D (_external_clk_bit), \ + .external_cond =3D (_external_cond), \ } =20 #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit, _mst= op) \ - DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _mon= index, _monbit) + DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _mon= index, _monbit, \ + 0, 0, 0) =20 #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _mon= bit, _mstop) \ - DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _moni= ndex, _monbit) + DEF_MOD_BASE(_name, _mstop, _parent, true, false, _onindex, _onbit, _moni= ndex, _monbit, \ + 0, 0, 0) =20 #define DEF_MOD_NO_PM(_name, _parent, _onindex, _onbit, _monindex, _monbit= , _mstop) \ - DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _moni= ndex, _monbit) + DEF_MOD_BASE(_name, _mstop, _parent, false, true, _onindex, _onbit, _moni= ndex, _monbit, \ + 0, 0, 0) + +#define DEF_MOD_EXTERNAL(_name, _parent, _onindex, _onbit, _monindex, _mon= bit, _mstop, \ + _external_clk_offset, _external_clk_bit, _external_cond) \ + DEF_MOD_BASE(_name, _mstop, _parent, false, false, _onindex, _onbit, _mon= index, _monbit, \ + _external_clk_offset, _external_clk_bit, _external_cond) =20 /** * struct rzv2h_reset - Reset definitions --=20 2.49.0