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Mon, 07 Apr 2025 09:52:18 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:78b9:80c2:5373:1b49]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec16ba978sm139272305e9.23.2025.04.07.09.52.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 09:52:17 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v2 2/9] clk: renesas: rzv2h-cpg: Add macro for defining static dividers Date: Mon, 7 Apr 2025 17:51:55 +0100 Message-ID: <20250407165202.197570-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250407165202.197570-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250407165202.197570-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Unlike dynamic dividers, static dividers do not have a monitor bit. Introduce the `DEF_CSDIV()` macro for defining static dividers, ensuring consistency with existing dynamic divider macros. Additionally, introduce the `CSDIV_NO_MON` macro to indicate the absence of a monitor bit, allowing the monitoring step to be skipped when `mon` is set to `CSDIV_NO_MON`. Note, `rzv2h_cpg_ddiv_clk_register()` will be re-used instead of generic `clk_hw_register_divider_table()` for registering satic dividers as some of the static dividers require RMW operations. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/clk/renesas/rzv2h-cpg.c | 3 +++ drivers/clk/renesas/rzv2h-cpg.h | 10 ++++++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cp= g.c index 4cda36d7f0a7..4123c30e8663 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -298,6 +298,9 @@ static inline int rzv2h_cpg_wait_ddiv_clk_update_done(v= oid __iomem *base, u8 mon u32 bitmask =3D BIT(mon); u32 val; =20 + if (mon =3D=3D CSDIV_NO_MON) + return 0; + return readl_poll_timeout_atomic(base + CPG_CLKSTATUS0, val, !(val & bitm= ask), 10, 200); } =20 diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cp= g.h index 03e602d70f69..00b52b459aad 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -45,6 +45,14 @@ struct ddiv { unsigned int monbit:5; }; =20 +/* + * On RZ/V2H(P), the dynamic divider clock supports up to 19 monitor bits, + * while on RZ/G3E, it supports up to 16 monitor bits. Use the maximum val= ue + * `0x1f` to indicate that monitor bits are not supported for static divid= er + * clocks. + */ +#define CSDIV_NO_MON (0x1f) + #define DDIV_PACK(_offset, _shift, _width, _monbit) \ ((struct ddiv){ \ .offset =3D _offset, \ @@ -150,6 +158,8 @@ enum clk_types { .parent =3D _parent, \ .dtable =3D _dtable, \ .flag =3D CLK_DIVIDER_HIWORD_MASK) +#define DEF_CSDIV(_name, _id, _parent, _ddiv_packed, _dtable) \ + DEF_DDIV(_name, _id, _parent, _ddiv_packed, _dtable) #define DEF_SMUX(_name, _id, _smux_packed, _parent_names) \ DEF_TYPE(_name, _id, CLK_TYPE_SMUX, \ .cfg.smux =3D _smux_packed, \ --=20 2.49.0