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Bottomley" , "Martin K. Petersen" CC: , , , , , , , Subject: [PATCH V6 2/3] scsi: ufs-qcom: Add support to dump MCQ registers Date: Mon, 7 Apr 2025 19:51:09 +0530 Message-ID: <20250407142110.16925-3-quic_mapa@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250407142110.16925-1-quic_mapa@quicinc.com> References: <20250407142110.16925-1-quic_mapa@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: _1KhEidujFBpVQb5QGP9ZaBhSa7GUxdb X-Authority-Analysis: v=2.4 cv=LLlmQIW9 c=1 sm=1 tr=0 ts=67f3df6b cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=XR8D0OoHHMoA:10 a=COk6AnOGAAAA:8 a=9gNdh71IRGoVKlRnfDUA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: _1KhEidujFBpVQb5QGP9ZaBhSa7GUxdb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1095,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-04-07_04,2025-04-03_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 clxscore=1015 mlxlogscore=915 malwarescore=0 phishscore=0 lowpriorityscore=0 priorityscore=1501 mlxscore=0 spamscore=0 adultscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2504070101 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support to dump UFS MCQ registers to enhance debugging capabilities for the Qualcomm UFS Host Controller. Signed-off-by: Manish Pandey --- drivers/ufs/host/ufs-qcom.c | 83 +++++++++++++++++++++++++++++++++++++ drivers/ufs/host/ufs-qcom.h | 2 + 2 files changed, 85 insertions(+) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 028833acb3db..3a8eac62967e 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1542,6 +1542,77 @@ int ufs_qcom_testbus_config(struct ufs_qcom_host *ho= st) return 0; } =20 +int ufs_qcom_dump_regs(struct ufs_hba *hba, size_t offset, size_t len, + const char *prefix, enum ufshcd_res id) +{ + u32 *regs __free(kfree) =3D NULL; + size_t pos; + + if (offset % 4 !=3D 0 || len % 4 !=3D 0) + return -EINVAL; + + regs =3D kzalloc(len, GFP_ATOMIC); + if (!regs) + return -ENOMEM; + + for (pos =3D 0; pos < len; pos +=3D 4) + regs[pos / 4] =3D readl(hba->res[id].base + offset + pos); + + print_hex_dump(KERN_ERR, prefix, + len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE, + 16, 4, regs, len, false); + + return 0; +} + +static void ufs_qcom_dump_mcq_hci_regs(struct ufs_hba *hba) +{ + /* voluntarily yield the CPU to prevent CPU hog during data dumps */ + /* RES_MCQ_1 */ + ufs_qcom_dump_regs(hba, 0x0, 256 * 4, "MCQ HCI 1da0000-1da03f0", RES_MCQ); + cond_resched(); + + /* RES_MCQ_2 */ + ufs_qcom_dump_regs(hba, 0x400, 256 * 4, "MCQ HCI 1da0400-1da07f0", RES_MC= Q); + cond_resched(); + + /*RES_MCQ_VS */ + ufs_qcom_dump_regs(hba, 0x0, 5 * 4, "MCQ VS 1da4000-1da4010", RES_MCQ_VS); + cond_resched(); + + /* RES_MCQ_SQD_1 */ + ufs_qcom_dump_regs(hba, 0x0, 256 * 4, "MCQ SQD 1da5000-1da53f0", RES_MCQ_= SQD); + cond_resched(); + + /* RES_MCQ_SQD_2 */ + ufs_qcom_dump_regs(hba, 0x400, 256 * 4, "MCQ SQD 1da5400-1da57f0", RES_MC= Q_SQD); + cond_resched(); + + /* RES_MCQ_SQD_3 */ + ufs_qcom_dump_regs(hba, 0x800, 256 * 4, "MCQ SQD 1da5800-1da5bf0", RES_MC= Q_SQD); + cond_resched(); + + /* RES_MCQ_SQD_4 */ + ufs_qcom_dump_regs(hba, 0xc00, 256 * 4, "MCQ SQD 1da5c00-1da5ff0", RES_MC= Q_SQD); + cond_resched(); + + /* RES_MCQ_SQD_5 */ + ufs_qcom_dump_regs(hba, 0x1000, 256 * 4, "MCQ SQD 1da6000-1da63f0", RES_M= CQ_SQD); + cond_resched(); + + /* RES_MCQ_SQD_6 */ + ufs_qcom_dump_regs(hba, 0x1400, 256 * 4, "MCQ SQD 1da6400-1da67f0", RES_M= CQ_SQD); + cond_resched(); + + /* RES_MCQ_SQD_7 */ + ufs_qcom_dump_regs(hba, 0x1800, 256 * 4, "MCQ SQD 1da6800-1da6bf0", RES_M= CQ_SQD); + cond_resched(); + + /* RES_MCQ_SQD_8 */ + ufs_qcom_dump_regs(hba, 0x1c00, 256 * 4, "MCQ SQD 1da6c00-1da6ff0", RES_M= CQ_SQD); + cond_resched(); +} + static void ufs_qcom_dump_dbg_regs(struct ufs_hba *hba) { u32 reg; @@ -1600,6 +1671,18 @@ static void ufs_qcom_dump_dbg_regs(struct ufs_hba *h= ba) =20 reg =3D ufs_qcom_get_debug_reg_offset(host, UFS_DBG_RD_REG_TMRLUT); ufshcd_dump_regs(hba, reg, 9 * 4, "UFS_DBG_RD_REG_TMRLUT "); + + if (hba->mcq_enabled) { + reg =3D ufs_qcom_get_debug_reg_offset(host, UFS_RD_REG_MCQ); + ufshcd_dump_regs(hba, reg, 64 * 4, "HCI MCQ Debug Registers "); + } + + /* ensure below dumps occur only in task context due to blocking calls. */ + if (in_task()) { + /* Dump MCQ Host Vendor Specific Registers */ + if (hba->mcq_enabled) + ufs_qcom_dump_mcq_hci_regs(hba); + } } =20 /** diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index a5bf1282ddbe..6087fd1534b4 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -50,6 +50,8 @@ enum { */ UFS_AH8_CFG =3D 0xFC, =20 + UFS_RD_REG_MCQ =3D 0xD00, + REG_UFS_CFG3 =3D 0x271C, =20 REG_UFS_DEBUG_SPARE_CFG =3D 0x284C, --=20 2.17.1