From nobody Mon Feb 9 16:13:19 2026 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F0DD23AE8B for ; Mon, 7 Apr 2025 11:13:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744024400; cv=none; b=ZF/hyyOSXqCbNANjdpoesCpN92GjCKnu8f4eecnpKw1zXRjcwFiRg0zz0wFiVy7mqxw/kiwpgMvxYzyDXnRGQgjKev1VeX00R8X03UHd4U8yshkRlxTb/3Fx6hAWqHwUdvPVCc+vrfJMx1cQ1HKfAlZnkToE1w7RkiNuHart7zw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744024400; c=relaxed/simple; bh=M6FpkVRtxGORrbTAyIXtmXdXTm4QW5v28hjznZvm/vs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=V+tk45IM/bCUQOdycDMt+vVKWEgIwFxsIOQVzpzTaSaHSmD0Hwx1WVxIi0y0cozyvHlpG0UXR4EMBUrHc/N/5wgZDcDJUQ4ZQ6c5jMK8933qC2zMpDVDn56hMnmTGU6VGN6G4KH57WXJVnBhllNV/+ajnlEsTncSeuZYIU5wyv4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 537Ao0Jh001895 for ; Mon, 7 Apr 2025 18:50:00 +0800 (+08) (envelope-from ben717@andestech.com) Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 537Ang5P001561 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 7 Apr 2025 18:49:42 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Mon, 7 Apr 2025 18:49:42 +0800 From: Ben Zong-You Xie To: , , CC: , , , , , , , , , , , "Ben Zong-You Xie" Subject: [PATCH 2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings Date: Mon, 7 Apr 2025 18:49:30 +0800 Message-ID: <20250407104937.315783-3-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250407104937.315783-1-ben717@andestech.com> References: <20250407104937.315783-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 537Ao0Jh001895 Content-Type: text/plain; charset="utf-8" Add DT binding documentation for the Andes QiLai SoC and the Voyager development board. Signed-off-by: Ben Zong-You Xie Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/riscv/andes.yaml | 25 +++++++++++++++++++ MAINTAINERS | 5 ++++ 2 files changed, 30 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/andes.yaml diff --git a/Documentation/devicetree/bindings/riscv/andes.yaml b/Documenta= tion/devicetree/bindings/riscv/andes.yaml new file mode 100644 index 000000000000..aa1edf1fdec7 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/andes.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/andes.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes SoC-based boards + +maintainers: + - Ben Zong-You Xie + +description: + Andes SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - andestech,voyager + - const: andestech,qilai + +additionalProperties: true diff --git a/MAINTAINERS b/MAINTAINERS index 96b827049501..a0ccac1cca29 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20725,6 +20725,11 @@ F: drivers/irqchip/irq-riscv-intc.c F: include/linux/irqchip/riscv-aplic.h F: include/linux/irqchip/riscv-imsic.h =20 +RISC-V ANDES SoC Support +M: Ben Zong-You Xie +S: Maintained +F: Documentation/devicetree/bindings/riscv/andes.yaml + RISC-V ARCHITECTURE M: Paul Walmsley M: Palmer Dabbelt --=20 2.34.1