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[211.75.127.162]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-229785c0153sm74635035ad.65.2025.04.07.00.59.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 00:59:50 -0700 (PDT) Received: from hqs-appsw-a2o.mp600.macronix.com (linux-patcher [172.17.236.67]) by twhmp6px (Postfix) with ESMTPS id 515A880580; Mon, 7 Apr 2025 16:08:47 +0800 (CST) From: Cheng Ming Lin To: tudor.ambarus@linaro.org, pratyush@kernel.org, mwalle@kernel.org, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: alvinzhou@mxic.com.tw, leoyu@mxic.com.tw, Cheng Ming Lin Subject: [PATCH v2 3/3] mtd: spi-nor: macronix: Add fixups for MX25L3255E Date: Mon, 7 Apr 2025 15:54:00 +0800 Message-Id: <20250407075400.1113177-4-linchengming884@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250407075400.1113177-1-linchengming884@gmail.com> References: <20250407075400.1113177-1-linchengming884@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cheng Ming Lin SFDP of MX25L3255E is JESD216, which does not include the Quad Enable bit Requirement in BFPT. As a result, during BFPT parsing, the quad_enable method is not set to spi_nor_sr1_bit6_quad_enable. Therefore, it is necessary to correct this setting by late_init. In addition, MX25L3255E also supports 1-4-4 page program in 3-byte address mode. However, since the 3-byte address 1-4-4 page program is not defined in SFDP, it needs to be configured in late_init. Signed-off-by: Cheng Ming Lin Acked-by: Pratyush Yadav --- drivers/mtd/spi-nor/macronix.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c index 07e0bd0b70a0..4bbd3b651cec 100644 --- a/drivers/mtd/spi-nor/macronix.c +++ b/drivers/mtd/spi-nor/macronix.c @@ -58,6 +58,31 @@ macronix_qpp4b_post_sfdp_fixups(struct spi_nor *nor) return 0; } =20 +static int +mx25l3255e_late_init_fixups(struct spi_nor *nor) +{ + /* + * SFDP of MX25L3255E is JESD216, which does not include the Quad + * Enable bit Requirement in BFPT. As a result, during BFPT parsing, + * the quad_enable method is not set to spi_nor_sr1_bit6_quad_enable. + * Therefore, it is necessary to correct this setting by late_init. + */ + nor->params->quad_enable =3D spi_nor_sr1_bit6_quad_enable; + + /* + * In addition, MX25L3255E also supports 1-4-4 page program in 3-byte + * address mode. However, since the 3-byte address 1-4-4 page program + * is not defined in SFDP, it needs to be configured in late_init. + */ + struct spi_nor_flash_parameter *params =3D nor->params; + + params->hwcaps.mask |=3D SNOR_HWCAPS_PP_1_4_4; + spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_4_4], + SPINOR_OP_PP_1_4_4, SNOR_PROTO_1_4_4); + + return 0; +} + static const struct spi_nor_fixups mx25l25635_fixups =3D { .post_bfpt =3D mx25l25635_post_bfpt_fixups, .post_sfdp =3D macronix_qpp4b_post_sfdp_fixups, @@ -67,6 +92,10 @@ static const struct spi_nor_fixups macronix_qpp4b_fixups= =3D { .post_sfdp =3D macronix_qpp4b_post_sfdp_fixups, }; =20 +static const struct spi_nor_fixups mx25l3255e_fixups =3D { + .late_init =3D mx25l3255e_late_init_fixups, +}; + static const struct flash_info macronix_nor_parts[] =3D { { .id =3D SNOR_ID(0xc2, 0x20, 0x10), @@ -199,6 +228,7 @@ static const struct flash_info macronix_nor_parts[] =3D= { }, { /* MX25L3255E */ .id =3D SNOR_ID(0xc2, 0x9e, 0x16), + .fixups =3D &mx25l3255e_fixups, }, /* * This spares us of adding new flash entries for flashes that can be --=20 2.25.1