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([199.182.234.55]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-739d97ee60dsm7787598b3a.40.2025.04.07.00.22.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 00:22:05 -0700 (PDT) From: Longbin Li To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: ghost <2990955050@qq.com>, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Longbin Li Subject: [PATCH 2/2] pwm: sophgo: add driver for SG2044 Date: Mon, 7 Apr 2025 15:20:39 +0800 Message-ID: <20250407072056.8629-3-looong.bin@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250407072056.8629-1-looong.bin@gmail.com> References: <20250407072056.8629-1-looong.bin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: ghost <2990955050@qq.com> Add PWM controller for SG2044. Signed-off-by: Longbin Li --- drivers/pwm/pwm-sophgo-sg2042.c | 162 +++++++++++++++++++++++++++----- 1 file changed, 138 insertions(+), 24 deletions(-) diff --git a/drivers/pwm/pwm-sophgo-sg2042.c b/drivers/pwm/pwm-sophgo-sg204= 2.c index ff4639d849ce..c62e8c758d87 100644 --- a/drivers/pwm/pwm-sophgo-sg2042.c +++ b/drivers/pwm/pwm-sophgo-sg2042.c @@ -26,20 +26,22 @@ #include #include -/* - * Offset RegisterName - * 0x0000 HLPERIOD0 - * 0x0004 PERIOD0 - * 0x0008 HLPERIOD1 - * 0x000C PERIOD1 - * 0x0010 HLPERIOD2 - * 0x0014 PERIOD2 - * 0x0018 HLPERIOD3 - * 0x001C PERIOD3 - * Four groups and every group is composed of HLPERIOD & PERIOD - */ -#define SG2042_PWM_HLPERIOD(chan) ((chan) * 8 + 0) -#define SG2042_PWM_PERIOD(chan) ((chan) * 8 + 4) +#define REG_HLPERIOD 0x0 +#define REG_PERIOD 0x4 +#define REG_GROUP 0x8 +#define REG_POLARITY 0x40 + +#define REG_PWMSTART 0x44 +#define REG_PWMUPDATE 0x4C +#define REG_SHIFTCOUNT 0x80 +#define REG_SHIFTSTART 0x90 +#define REG_PWM_OE 0xD0 + +#define PWM_REG_NUM 0x80 + +#define PWM_POLARITY_MASK(n) BIT(n) +#define PWM_HLPERIOD(chan) ((chan) * REG_GROUP + REG_HLPERIOD) +#define PWM_PERIOD(chan) ((chan) * REG_GROUP + REG_PERIOD) #define SG2042_PWM_CHANNELNUM 4 @@ -51,6 +53,12 @@ struct sg2042_pwm_ddata { void __iomem *base; unsigned long clk_rate_hz; + struct mutex lock; +}; + +struct sg2042_chip_data { + const struct pwm_ops ops; + bool atomic; }; /* @@ -62,8 +70,8 @@ static void pwm_sg2042_config(struct sg2042_pwm_ddata *dd= ata, unsigned int chan, { void __iomem *base =3D ddata->base; - writel(period_ticks, base + SG2042_PWM_PERIOD(chan)); - writel(hlperiod_ticks, base + SG2042_PWM_HLPERIOD(chan)); + writel(period_ticks, base + PWM_PERIOD(chan)); + writel(hlperiod_ticks, base + PWM_HLPERIOD(chan)); } static int pwm_sg2042_apply(struct pwm_chip *chip, struct pwm_device *pwm, @@ -104,8 +112,8 @@ static int pwm_sg2042_get_state(struct pwm_chip *chip, = struct pwm_device *pwm, u32 hlperiod_ticks; u32 period_ticks; - period_ticks =3D readl(ddata->base + SG2042_PWM_PERIOD(chan)); - hlperiod_ticks =3D readl(ddata->base + SG2042_PWM_HLPERIOD(chan)); + period_ticks =3D readl(ddata->base + PWM_PERIOD(chan)); + hlperiod_ticks =3D readl(ddata->base + PWM_HLPERIOD(chan)); if (!period_ticks) { state->enabled =3D false; @@ -123,13 +131,112 @@ static int pwm_sg2042_get_state(struct pwm_chip *chi= p, struct pwm_device *pwm, return 0; } -static const struct pwm_ops pwm_sg2042_ops =3D { - .apply =3D pwm_sg2042_apply, - .get_state =3D pwm_sg2042_get_state, +static void pwm_sg2044_config(struct sg2042_pwm_ddata *ddata, struct pwm_d= evice *pwm, bool enabled) +{ + u32 pwm_value; + + pwm_value =3D readl(ddata->base + REG_PWMSTART); + + if (enabled) + writel(pwm_value | BIT(pwm->hwpwm), ddata->base + REG_PWMSTART); + else + writel(pwm_value & ~BIT(pwm->hwpwm), ddata->base + REG_PWMSTART); +} + +static void pwm_sg2044_set_outputenable(struct sg2042_pwm_ddata *ddata, st= ruct pwm_device *pwm, + bool enabled) +{ + u32 pwm_value; + + pwm_value =3D readl(ddata->base + REG_PWM_OE); + + if (enabled) + writel(pwm_value | BIT(pwm->hwpwm), ddata->base + REG_PWM_OE); + else + writel(pwm_value & ~BIT(pwm->hwpwm), ddata->base + REG_PWM_OE); +} + +static int pwm_sg2044_set_polarity(struct sg2042_pwm_ddata *ddata, struct = pwm_device *pwm, + const struct pwm_state *state) +{ + enum pwm_polarity polarity; + u32 pwm_value; + + pwm_value =3D readl(ddata->base + REG_POLARITY); + + polarity =3D state->polarity; + + if (polarity =3D=3D PWM_POLARITY_NORMAL) + pwm_value &=3D ~BIT(pwm->hwpwm); + else + pwm_value |=3D BIT(pwm->hwpwm); + + writel(pwm_value, ddata->base + REG_POLARITY); + + return 0; +} + +static int pwm_sg2044_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct sg2042_pwm_ddata *ddata =3D pwmchip_get_drvdata(chip); + u32 hlperiod_ticks; + u32 period_ticks; + + if (!state->enabled) { + pwm_sg2044_config(ddata, pwm, false); + return 0; + } + + pwm_sg2044_set_polarity(ddata, pwm, state); + + /* + * Duration of High level (duty_cycle) =3D HLPERIOD x Period_of_input_clk + * Duration of One Cycle (period) =3D PERIOD x Period_of_input_clk + */ + period_ticks =3D min(mul_u64_u64_div_u64(ddata->clk_rate_hz, state->perio= d, + NSEC_PER_SEC), U32_MAX); + hlperiod_ticks =3D min(mul_u64_u64_div_u64(ddata->clk_rate_hz, state->dut= y_cycle, + NSEC_PER_SEC), U32_MAX); + + dev_dbg(pwmchip_parent(chip), "chan[%u]: PERIOD=3D%u, HLPERIOD=3D%u\n", + pwm->hwpwm, period_ticks, hlperiod_ticks); + + pwm_sg2042_config(ddata, pwm->hwpwm, period_ticks, hlperiod_ticks); + + guard(mutex)(&ddata->lock); + + /* + * re-enable PWMSTART to refresh the register period + */ + pwm_sg2044_config(ddata, pwm, false); + pwm_sg2044_set_outputenable(ddata, pwm, true); + pwm_sg2044_config(ddata, pwm, true); + + return 0; +} + +static const struct sg2042_chip_data sg2042_chip_data =3D { + .ops =3D { + .apply =3D pwm_sg2042_apply, + .get_state =3D pwm_sg2042_get_state, + }, + .atomic =3D true, +}; + +static const struct sg2042_chip_data sg2044_chip_data =3D { + .ops =3D { + .apply =3D pwm_sg2044_apply, + .get_state =3D pwm_sg2042_get_state, + }, + .atomic =3D false, }; static const struct of_device_id sg2042_pwm_ids[] =3D { - { .compatible =3D "sophgo,sg2042-pwm" }, + { .compatible =3D "sophgo,sg2042-pwm", + .data =3D &sg2042_chip_data }, + { .compatible =3D "sophgo,sg2044-pwm", + .data =3D &sg2044_chip_data }, { } }; MODULE_DEVICE_TABLE(of, sg2042_pwm_ids); @@ -137,17 +244,24 @@ MODULE_DEVICE_TABLE(of, sg2042_pwm_ids); static int pwm_sg2042_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; + const struct sg2042_chip_data *chip_data; struct sg2042_pwm_ddata *ddata; struct reset_control *rst; struct pwm_chip *chip; struct clk *clk; int ret; + chip_data =3D device_get_match_data(dev); + if (!chip_data) + return -ENODEV; + chip =3D devm_pwmchip_alloc(dev, SG2042_PWM_CHANNELNUM, sizeof(*ddata)); if (IS_ERR(chip)) return PTR_ERR(chip); ddata =3D pwmchip_get_drvdata(chip); + mutex_init(&ddata->lock); + ddata->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(ddata->base)) return PTR_ERR(ddata->base); @@ -170,8 +284,8 @@ static int pwm_sg2042_probe(struct platform_device *pde= v) if (IS_ERR(rst)) return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset\n"); - chip->ops =3D &pwm_sg2042_ops; - chip->atomic =3D true; + chip->ops =3D &chip_data->ops; + chip->atomic =3D chip_data->atomic; ret =3D devm_pwmchip_add(dev, chip); if (ret < 0) -- 2.48.1