From nobody Mon Feb 9 04:07:43 2026 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3EDA1FCFD3 for ; Mon, 7 Apr 2025 15:24:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744039465; cv=none; b=pOywaSzCufCDX1mzuvPi4IISUnXPOsunpBrflqAM4WsrokjX2RxlzGyWnLO+aP8S0VrYoQHg7/98m9kQmReZvvRJoDvECcl663NIpM+EdxmYhuFmfwMiZmcrnT49eaH0LuoTlyQdBnKRN+K3PhpO9tALKIlrwGL/76pa0Y8XZPE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744039465; c=relaxed/simple; bh=CeUr7VtrtDVG3f4pna9r8Lu1ToiXfg1Ot4m0nP20rJw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GjxaS252Y4rluAPpPUr7ilehOEloHEgUM5TlWHgiHqT4Y1kMoT2xI0qPshfPoBaZ//KjmazXX2X1OtXUHDBxNu3kf3Jzh/K7THhgEdrG/0ozjOoOvIwshYwt8TdvURwH/FE4ZVkp5CVRF0u4CCuwAsA28haXxwXUOXRWPVKMWwY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=s1Fyc7ef; arc=none smtp.client-ip=209.85.221.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="s1Fyc7ef" Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-391342fc0b5so3558934f8f.3 for ; Mon, 07 Apr 2025 08:24:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1744039461; x=1744644261; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=PvIr3fZaBEgjprc2ipD5ThXrnHkh3G3Z/8wBWGmdR/A=; b=s1Fyc7efjBUg1LBDy6rYE1R1mZP97obsToRZrhy3BXiZ0bl7B6+LdVNMepVftD6kZz Y+Nt2CrWvTnPWjKXrBbN82fhMofjdZUVqNBZT1lGg1zeSDxqEerNqIoKmVCHkELmWnaQ PnnCX2cntBPZaPddxGRIRUZQT8rJ+eij8AkGsMwk2O21UZMpqi8GZ3LSecSv2yaY2kiW objBNHVkSZmfpn1eP+PiTVFyLfnuCSFPC3LtRlin2A3E6KhM/SF38tLLMgrMkrUtOion dGWs9n+uB2RdBm7z/mbKUKd9/7LUzPM8VtMelQyi37YySJ2YfJ68lvgG1hTWU60rHiW+ 0GvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744039461; x=1744644261; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PvIr3fZaBEgjprc2ipD5ThXrnHkh3G3Z/8wBWGmdR/A=; b=XykTUJFVxO4/9UGpwlhT4cUv59jcrFDkaIQts4Wv/RlAfutqo32bQ2DF+CMVV6XuKz fO6rGkb6bMNFmh9YeYeCf6DNzaU2bOdMvdvDFeyQwhqt4nF5KKxasnn0WVaMYYz1iEQV 10bhxkjlY6Dm4CdZUm69vxXvIA2ZDDPjLkVd7LOBwdS074lLgAxQS8lC/CYAU+kkt1cc 0OsxJxb1G7sR+p9g0mkFz3mZ/By3Tm+pjSrLp1ceVkYyt5BT1yl29UHXls6ddoMei8tq nw0MgYlOv1M8ctNHYH2/7LmSCszapunRxzSN/14+KZRg3V2U5deYfJP3QnqOwgqri/lN gkCQ== X-Forwarded-Encrypted: i=1; AJvYcCUnMm2F8MyZPiaLTyfqACIlfV3uYbdpHU53/vIGAG4oTa2fh+zODqQNKTeLYORQn8z5qaoa8DhhF5MnyhQ=@vger.kernel.org X-Gm-Message-State: AOJu0YxJxY84JvQ2ExSOsK7v0Arf6jK9CbQhz+CBL3THIZb7l5+UZ3wp FGm/49wSHuIlybh5AFue6Db7NLK3AKaB9z7cfqAUBXzZ76Uc9g8LctSiXvq95KcoKNACFcpRxPQ P X-Gm-Gg: ASbGncuShaPzDU4ZCZEP0nGc9HhsLxB78fxnJJ43I54TbWLijwc8Lqw17KkzQpUPQoC FOHmxSrK2hK2kjySs+gCC3t325r6I28HRmzJrZ2Fq/vZIFOblIHS4nUP2KGXXC0f9un2ePRFFxg rXhraZ0UoSdcu1TZlpaot8G1t7aU7WiMXjZzWFvTQ9yr4Yvl2Yg5geU2MKt+h3oUZzZLjeWPwRd N9MLCX/8kRi8CWcfFvTUp5ukN83QXrR2U0WIdvPMkV7dtZzKMsJLu/jm5bcG8soJPwuHgE4F0lO IWznELJ4fI2NKqW3bGvu8YmF9uCcDypFJSOq83rIg1JqSHgSuWH7cdOnV4rTmvt37w== X-Google-Smtp-Source: AGHT+IHDvNkFMbe0TQoAjLEsRn6aHFXvNsA/xJyh/TzfjeC5kl1IMD7S/50UpNYPAwREaXC+RsXCWA== X-Received: by 2002:a05:6000:250c:b0:391:298c:d673 with SMTP id ffacd0b85a97d-39cba9827afmr11110612f8f.40.1744039461083; Mon, 07 Apr 2025 08:24:21 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c301b42besm12212001f8f.41.2025.04.07.08.24.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 08:24:20 -0700 (PDT) From: Neil Armstrong Date: Mon, 07 Apr 2025 17:24:13 +0200 Subject: [PATCH v3 1/5] dt-bindings: media: qcom,sm8550-iris: document SM8650 IRIS accelerator Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250407-topic-sm8x50-iris-v10-v3-1-63569f6d04aa@linaro.org> References: <20250407-topic-sm8x50-iris-v10-v3-0-63569f6d04aa@linaro.org> In-Reply-To: <20250407-topic-sm8x50-iris-v10-v3-0-63569f6d04aa@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2083; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=CeUr7VtrtDVG3f4pna9r8Lu1ToiXfg1Ot4m0nP20rJw=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBn8+4h/z7HWBd83Gst2hqpaTLu6ts1CrD8MZEN+M3g zR819MqJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ/PuIQAKCRB33NvayMhJ0TudD/ 4jh0ymmQzp5rU3R4//ei293Upl0nBCujyw+FQ+b+kB3SvkHMHpnD61P/sOteVebXw+Q7zq+7zrl68b Xn8r+yMLhUjKPlqWdqgM8+Wbt9S23DTyOqmMRpW/KdfvjPxG58yhejZWskd7bv5Lvg/fm8+F/C36x4 O4As0zjuSYtrxJAteqvVopaG8zNxH7QRIevQiSlx2E03t7A3s6n4ZNxc1cvpbM/Pkwm+vWYx3M/Dge IrZ7Eo6nDMnqNthvsZnkcE1uW/h2JXvdkawynD0EVXVa9LHXcvbanwkPJRkfLQqOpVXQwNtbV6u2nB s3qqV0kns4+3YXZkdRo21LLj3hMRIpzK47Kzytq9u5rDDrNORjVhmEw1HZmXQcCIiHmeXmstxJ3gwG t6TiJaDmW4lG6Ys4uM4C+VYjU/jlXuhtvu+Pg4pk56ID1Bnf+kfYXSO3c9Wdclcm5eM/M0t+grQ+SE P+z1yRROcTqcbION2KBrwfhn2hpChfXpaxn2/fMyNtwhqrKa0+5xSoDYtVTRedeiVUWgLaDPxkZSEP tLsRu1RfzmBQsrkoXNRxTDgsHNBZQ0zjNzRYxf5rqbUASo6jCPIMBEwGuLE0eQ1eONS+xv1Ch1pMHQ B/JyrvtQA3D7JdXY4KiALqqM6bCqSm8AXbSJn6UUrM7IgN/Wz/MjX1YzFsjg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Document the IRIS video decoder and encoder accelerator found in the SM8650 platform, it requires 2 more reset lines in addition to the properties required for the SM8550 platform. Reviewed-by: Rob Herring (Arm) Reviewed-by: Vikash Garodia Reviewed-by: Bryan O'Donoghue Signed-off-by: Neil Armstrong Tested-by: Bryan O'Donoghue # x1e Dell=20 --- .../bindings/media/qcom,sm8550-iris.yaml | 33 ++++++++++++++++++= ---- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml = b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml index e424ea84c211f473a799481fd5463a16580187ed..536cf458dcb08141e5a1ec8c3df= 964196e599a57 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml @@ -14,12 +14,11 @@ description: The iris video processing unit is a video encode and decode accelerator present on Qualcomm platforms. =20 -allOf: - - $ref: qcom,venus-common.yaml# - properties: compatible: - const: qcom,sm8550-iris + enum: + - qcom,sm8550-iris + - qcom,sm8650-iris =20 power-domains: maxItems: 4 @@ -49,11 +48,15 @@ properties: - const: video-mem =20 resets: - maxItems: 1 + minItems: 1 + maxItems: 3 =20 reset-names: + minItems: 1 items: - const: bus + - const: xo + - const: core =20 iommus: maxItems: 2 @@ -75,6 +78,26 @@ required: - iommus - dma-coherent =20 +allOf: + - $ref: qcom,venus-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm8650-iris + then: + properties: + resets: + minItems: 3 + reset-names: + minItems: 3 + else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 + unevaluatedProperties: false =20 examples: --=20 2.34.1 From nobody Mon Feb 9 04:07:43 2026 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEB961FCFDB for ; Mon, 7 Apr 2025 15:24:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744039466; cv=none; b=SJpbNe//zEvIrP4mGj8VHeYR5Y90e3rm6FInx3KfRBjVxHO5kA+8oPf2XpvSTHeKdUEM70lOdvHMRunSa2WPHsd5ciBb8gRFd27o9Ce0C7pk62pfxLTlb/xw4Q2dSmC2g950Iw0fpVfFPlXdbZ6Y6NDVWGPV0PDq8z7cJT2KExo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744039466; c=relaxed/simple; bh=RVAZyY5IcoBzQEHI3gKR0pYiz9xjpwuFm7lVMrzCleI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DOH6wrBjV1fOU10rSoCU8kaSaGyVWX3qkSMzY5eti8P7PzxzwKBlKGwp87J7UhtUqN7o95HZCIe7ApPc0po9QYWr8mBq3uHJJeKNOylLCnqtyMKwAMDoSOuuYdtcP36aDZ3irjFu8CCYrCR9CIP1KEjFW84Mh0rIUKvg6RRdk9E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=GXG9qmOL; arc=none smtp.client-ip=209.85.221.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="GXG9qmOL" Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-39c30d9085aso2633831f8f.1 for ; Mon, 07 Apr 2025 08:24:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1744039462; x=1744644262; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=rFhBT6qWaqm/ORgbP/ajYYPXDSwWN3XeFcOKJs5rzCY=; b=GXG9qmOLC3FyKdd1A6xKb9j5z6/RzEia7hqJqVJm74J7zK4VIyWWyU6WPpwtSubzU+ Xnihhg/E8SxILR9j1LJRUfh4uyQLuk4Zj3YZZWntwljNW8M33zofr7pJtPjqfXrdsktO u6CCh1QrMOzryXYh+KzKL17qyZwV1yOoSnHtyEQzawYDrJojcxztApKHDbB7O8k893Nx wJib7FYBV0j7vhiiRQJgFf2iWR7jbuzf2ptqtbdxF8azebjUkUqW8lWAeJlRvyVgWQSW wCfM7WxVsxEwJcU/e2ap2BtGESsbhTIgbgY+BHtEslG7GXDFr+ICL0ob/NONZiM6QNu+ DtcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744039462; x=1744644262; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rFhBT6qWaqm/ORgbP/ajYYPXDSwWN3XeFcOKJs5rzCY=; b=BVQ91b1hDSHHh8Ire/tRSB4BI0CL6lNaHW1r+ItFYa2tPOHtgLYX8Ffk8P/3AkAz32 F8w9imRDsITu6obK2XctzjKHhIdiFv2M4sbxwWJnX9U6aYT/jgEbs0XigLSiJgPSmTQj ZnbsxWg+HY8NYO/6lHrWuWjfYhqHliH/Mn9JxG7NCqaCZw79BLCzfFIYVMIzCdeaUyvP f09NB9PiejO5zyhPeFuOlI7N8OM7LrkduV4PLo9uwkKtxaZ4i8HxmySbhAkYQLpNuG0r 5exTWAbVzinElAjIYBKq9lFYtcunhM3G6plPcyU4GQEN4ENQxYzNxgm67qBhJ3+Hsyel o5pw== X-Forwarded-Encrypted: i=1; AJvYcCVfQ6BaCQ4uNQRhrYYQUgtHsQWl/dIZAWJjHJ3Q829gQT5jJuhHHfIHYPzHdwFSxqEqzQFynJCdsXSXok0=@vger.kernel.org X-Gm-Message-State: AOJu0Yzqbo2JlwT0vXox8vmt7C0UFn87KdFwEIH65A+xQLg8E637pxvo SdLpEkDE0B7gcSSpsXob6LB3tsFkjVTdEyTeHF1P5cXViuVUsgSspZ4C8wUl6pr/nNluR5L0jry d X-Gm-Gg: ASbGncsqc5w/z2IgKZ9Wp8tpGlxmhLSqvoiPifGNdxXovJcg7varFhzbpF2byZr/CW9 bMy+ByUVlSiHP/YbE0M567JCSSbRexrWCbXSlJxo0fh1LZer5HIBzClPtkV2cPDhY0+9tMXgdmf VuYs6MYKg7AdZTkaA18ghcoe6MKx/PPzpD9bVKrznHjiilzqKZXap7upJrb3ulgrNr+RdBKJmf/ NmJeKwS9ohrLNMN8//ucPYnC8BfRvjd4wWpnZalQcifK7fZw5xqysaPUKImUh7SoD8SeCGBdiko AOhYus7AZD+OIJNYDBCKVd7/RMutKfFBoyRk8S+RftStOtg5PfRqGBALtq+HJlQcfw== X-Google-Smtp-Source: AGHT+IGKeErGsgt3xcPUWlAhrhw6nxkHOMynywbipAzVLMif+RkANCAk8iXT2yS7MJ0iTjz0ErJlAw== X-Received: by 2002:a05:6000:220b:b0:39c:2692:4259 with SMTP id ffacd0b85a97d-39cb35981fdmr11848571f8f.21.1744039461842; Mon, 07 Apr 2025 08:24:21 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c301b42besm12212001f8f.41.2025.04.07.08.24.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 08:24:21 -0700 (PDT) From: Neil Armstrong Date: Mon, 07 Apr 2025 17:24:14 +0200 Subject: [PATCH v3 2/5] media: platform: qcom/iris: add power_off_controller to vpu_ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250407-topic-sm8x50-iris-v10-v3-2-63569f6d04aa@linaro.org> References: <20250407-topic-sm8x50-iris-v10-v3-0-63569f6d04aa@linaro.org> In-Reply-To: <20250407-topic-sm8x50-iris-v10-v3-0-63569f6d04aa@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3736; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=RVAZyY5IcoBzQEHI3gKR0pYiz9xjpwuFm7lVMrzCleI=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBn8+4hQgEq2YcIQTOlrbncUouTzB4PzdefeSFsA/tC k+lqsHSJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ/PuIQAKCRB33NvayMhJ0e9yD/ 0SWf4xKtoipk/G7pbt95vkS/sum8uS2GA0eVAILuEVoEHlWkfvTUeAy9FqDA96hN3op5Kb+dOSHqHf CVou7r5z8NX3LN+ZoHyYVQ8m3IPO5yTyWKu0D61IcHL/qzp+MYXiBMDycYqld6V3o9RSmSSedxQwjw U8Lnbng0DASYQJ0HeM8/cVtJOavX6eibot1s9WERleYwfG53a6ZdFVUO5D9vAqpGPutVWB0auYNrLd VGynC6TeDJ2EqPAFHC/7AjZLmRr2SJO9hKDNClw+X0ZHOmwdM3nyRI6jZYmpm98BjhtZU6lDgdNw3p 2c2BllQ+3sAoMTk5fiFX0/em3pe5dAyP5/Y+w/uv8uIWMuy39lsevtna/jWkfVGd0UBCywWoI6LOd7 LzWXSH7YkDDoXbtqmlLYpTkpdhm+Lomj8gh8wfYEUSz8sUu6BbVBldd3MFW0GWfpRyzS8ZpvM1i9M0 9hjI0cV87lHr8bJ2TQV1p1/s7hCdGND7tPfSO7o7KsVS6TOaKxbsNfurxaqmwCFpNRwqDQ0DceZyb0 GZonbkraSxGo0T90kyocm9TnFa40i7RU6wGqLwn/f1+2FNceWPhe4cYuhfk+njgJm9KTTDHweYEU1d AxsZ6I+44KP1IJO/t9smd3fkiMyLuXYFg27JyrMt0IHXFFiP+R7+E/3UCsSA== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE In order to support the SM8650 iris33 hardware, we need to provide a specific constoller power off sequences via the vpu_ops callbacks. Add the callback, and use the current helper for currently supported platforms. Signed-off-by: Neil Armstrong Reviewed-by: Bryan O'Donoghue Reviewed-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e Dell=20 --- drivers/media/platform/qcom/iris/iris_vpu2.c | 1 + drivers/media/platform/qcom/iris/iris_vpu3.c | 1 + drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 ++-- drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 ++ 4 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/p= latform/qcom/iris/iris_vpu2.c index 8f502aed43ce2fa6a272a2ce14ff1ca54d3e63a2..7cf1bfc352d34b897451061b5c1= 4fbe90276433d 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c @@ -34,5 +34,6 @@ static u64 iris_vpu2_calc_freq(struct iris_inst *inst, si= ze_t data_size) =20 const struct vpu_ops iris_vpu2_ops =3D { .power_off_hw =3D iris_vpu_power_off_hw, + .power_off_controller =3D iris_vpu_power_off_controller, .calc_freq =3D iris_vpu2_calc_freq, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu3.c b/drivers/media/p= latform/qcom/iris/iris_vpu3.c index b484638e6105a69319232f667ee7ae95e3853698..13dab61427b8bd0491b69a9bc5f= 5144d27d17362 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3.c @@ -118,5 +118,6 @@ static u64 iris_vpu3_calculate_frequency(struct iris_in= st *inst, size_t data_siz =20 const struct vpu_ops iris_vpu3_ops =3D { .power_off_hw =3D iris_vpu3_power_off_hardware, + .power_off_controller =3D iris_vpu_power_off_controller, .calc_freq =3D iris_vpu3_calculate_frequency, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index fe9896d66848cdcd8c67bd45bbf3b6ce4a01ab10..268e45acaa7c0e3fe237123c62f= 0133d9dface14 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -211,7 +211,7 @@ int iris_vpu_prepare_pc(struct iris_core *core) return -EAGAIN; } =20 -static int iris_vpu_power_off_controller(struct iris_core *core) +int iris_vpu_power_off_controller(struct iris_core *core) { u32 val =3D 0; int ret; @@ -264,7 +264,7 @@ void iris_vpu_power_off(struct iris_core *core) { dev_pm_opp_set_rate(core->dev, 0); core->iris_platform_data->vpu_ops->power_off_hw(core); - iris_vpu_power_off_controller(core); + core->iris_platform_data->vpu_ops->power_off_controller(core); iris_unset_icc_bw(core); =20 if (!iris_vpu_watchdog(core, core->intr_status)) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index 63fa1fa5a4989e48aebdb6c7619c140000c0b44c..f8965661c602f990d5a7057565f= 79df4112d097e 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -13,6 +13,7 @@ extern const struct vpu_ops iris_vpu3_ops; =20 struct vpu_ops { void (*power_off_hw)(struct iris_core *core); + int (*power_off_controller)(struct iris_core *core); u64 (*calc_freq)(struct iris_inst *inst, size_t data_size); }; =20 @@ -22,6 +23,7 @@ void iris_vpu_clear_interrupt(struct iris_core *core); int iris_vpu_watchdog(struct iris_core *core, u32 intr_status); int iris_vpu_prepare_pc(struct iris_core *core); int iris_vpu_power_on(struct iris_core *core); +int iris_vpu_power_off_controller(struct iris_core *core); void iris_vpu_power_off_hw(struct iris_core *core); void iris_vpu_power_off(struct iris_core *core); =20 --=20 2.34.1 From nobody Mon Feb 9 04:07:43 2026 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D88A1FDA97 for ; Mon, 7 Apr 2025 15:24:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744039467; cv=none; b=lksEmrJI/lTuZEVkFCZWVZvhcsrNVy+cZssNy6LGJcbgICy3RaDptfHGJkPo7N6XoXSLSZvbXxJTLnO7KMcOvMsimikNYbbcc42rpn2lpO5RHEt67o9Dda1p9GTkdz5rQm4jfhi2/VLSojIgUgFEah/fDBUIxH4a7A6rFULQSPk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744039467; c=relaxed/simple; bh=yF/nZpFIBaoPgtK083tpBRuL0o6ITykxH9hfKXrn2O0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SIAyHYvq5jGzitypqdy+oiOEUaeuteGVPNd+U7IjPUtd1U/uSVbYuyktqI3KmeDjY+RKtTl9IuFt4A3ni+9K3j5xg7YpWL1xBG3gGDi2a0RHodMTRJoya4ZK4J7TBfxE1ieNDALfw2znIob5QuZwwmaHDOQ+9QJymjX31B3tBh4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=zFXNDVs3; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="zFXNDVs3" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-39ac56756f6so3871804f8f.2 for ; Mon, 07 Apr 2025 08:24:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1744039463; x=1744644263; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=IcSjwmZr8ORweNU9kIIwQdANNDnxoTJTNwIPGaZvALc=; b=zFXNDVs3VzihPdvE7Bja5ASLiF7MlJDgxaxC210zD32Z52Ik/Ca0aA6LbGRb5BnQur eWpt9vVZCsKHnLBkcC/VfirNgE8JE16GH1MFWNryj1tl3mZKP2qo4UGRlkpOQ3aiKsPv o5hLpnbge1+alRru5/I9kV0pQgbEXna6VWnpGpM2zkNObhhGl4Qq26elZbdRwba/VDjP 3hpgIJF98WfB3TjpZmQLT7j5nUYvkf5bR0LwwbvYmgTp//Bz+Fzpc+bu8oJvlxiCe0O9 9I2ktBMq3ahiZEH/xLn9w+QNkkTvNxQVjW2a9vrcMrjfFQCjUekIF6vq8lwVn+vnL2AV OBAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744039463; x=1744644263; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IcSjwmZr8ORweNU9kIIwQdANNDnxoTJTNwIPGaZvALc=; b=sBoq9kfTkZhDTvHPuAboDjoTrX2uoaOuerepQvXJ/i0E4ZLqFG5hyej1MTJe8D/Pqq 8kU7Ulki6FJ2feaJm6B701VZBUmhUVlSfJKdsCcvLnz1Labuy1tF91CGpnCIgzs3UZL4 mMpn+WyuM7wnW3YIg8U3rJcY1HyxdONFh3ANAKR5soBbToLHmbUDvGSy4kpcpnLYU1X9 dqzhSr0wcZ68o+hX0ROyL+YuZlTixnDqhho9MBRqMJ9fWeWJ4oZgh53XjCV7yzEI8g2x qSj2pYd6nQ00kgTgueXrYsIMnpOrUtfGPwpAuFPr2qr6fs9r/SAuiVaGqi8n41/zVJO/ l1Pw== X-Forwarded-Encrypted: i=1; AJvYcCXEp4CEPcrt5jLLzszRzYfc7Hs87cAesNr0/HwlSUaaXcm/8UVQW7PGHlvf67a5pG5jTJCHelMYhp6nWBs=@vger.kernel.org X-Gm-Message-State: AOJu0YwYi1pCVEFpYrKsDgVf92R6rioDiOtWRBb/GfsaZLJ5hdNtMDVC hh9D8Io19I8uJPTdjGmFMfgOGfiQZogIxNVbF82aED8CeCWe64euP2q6jToltEQ/WnDjfkrAa2j 0 X-Gm-Gg: ASbGnctbHUsFKY6xb+1CrdgkkSjWWcak+9Sdewbwe3TQ2UWAfSPuzkWsKb6wbJB1nso 8FdCF7WzIJuCfGQqwRYDU2Im/9ChORQPv2KiDKawFZvVw2Jw7+HynQjjr+RIttXrZCFzOFjy9fm ALw11Du+3XmKYPvgrPBNxZ12oStpK8tjDuDJz4qV1BEvONWLPOUyqVVQ7bF/u76hA5PBBdoMeWQ ird3G0bNKtvg9NSXhq5WGP0EP9m6n3T+vyGixlUvk9M6CMyFoWcdZaNNxEMys7ltI8QsR2JR9DF NKM3R7Xuh0AoU0hlpyueVgDSm5hmCVZLBiOxF7Gf2JXfijBMBKTLp3E6wmGiRORTOg== X-Google-Smtp-Source: AGHT+IEiztIgBCTamZNWx7wXWdVS9Mdv/TxnRw3HiOV9XILWkE1LHblkaE4EeM/P1T2cQOYdvHuaPA== X-Received: by 2002:a05:6000:4312:b0:390:e9e0:5cb3 with SMTP id ffacd0b85a97d-39cb36b2a91mr10562781f8f.12.1744039462633; Mon, 07 Apr 2025 08:24:22 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c301b42besm12212001f8f.41.2025.04.07.08.24.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 08:24:22 -0700 (PDT) From: Neil Armstrong Date: Mon, 07 Apr 2025 17:24:15 +0200 Subject: [PATCH v3 3/5] media: platform: qcom/iris: introduce optional controller_rst_tbl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250407-topic-sm8x50-iris-v10-v3-3-63569f6d04aa@linaro.org> References: <20250407-topic-sm8x50-iris-v10-v3-0-63569f6d04aa@linaro.org> In-Reply-To: <20250407-topic-sm8x50-iris-v10-v3-0-63569f6d04aa@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong , Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3992; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=yF/nZpFIBaoPgtK083tpBRuL0o6ITykxH9hfKXrn2O0=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBn8+4ipaaLhBnlbScsYbBzP5yhs0djrxvD3iyc0RFs V5IeTC6JAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ/PuIgAKCRB33NvayMhJ0VIREA CJei6IXdQrW7QLe/TcP/GwmC3F+un8EItAZKWCQAeJD6KaR/kab+E2OhirbnLJOQG/BSPFB77n6z3x mI2ZZqkYYH+0gA2HTu+i1JzhWUxeYC2Dcga5WZupLkTs0hLrgoZnzsiC1h0GvNtlcwQiyGr65pJm3q /UcSj7QdL2Zo8vR3PNlZq0cAT2w/V5U6XjRm3/G9VTR5z/YUx6sykWIsWL4GaM/EK2TsU8J9BeJiuq 2JTote7vWKuZ2elPL5AzWDl2VKG8+gVMtItQr90kHv04j40HuBNvx2+BNZzdPld5Qa3m6KXT69AOR6 Q21OHGRif1Dxt9kfEFZb0m849oJyDz78xPptarZr0qrPeuDI5KmwX1o37vfHzFJm6QLxdry971Gjgx 3mWBU660QE/DEBtGYsYuDPZOiQoW57zcHHIbpMDTRlZHWzF6ENyAJFyL2e5kQDs6vUVU+S0COKRJTs 6W9KaBHxsNRSBSW86jHQ61hDD9quViZKWyvi27iRfhWo/vbKkOPD4ZB6pm75ih5NakrhngMhNghKdc dQxYGwKSUfK7vyAvYHDd6Qb+eA+nQLn+XYG0nqPtIA1q5/1oqNqjRWqC1/+NTBjeuhzaHbHqws0skY erL5ZWLM+8ciDgkBD9Bmem1ClaDc1AgPYjafMzLx/FJWeQ0x6RnKYW7+2Mgg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Introduce an optional controller_rst_tbl use to store reset lines used to reset part of the controller. This is necessary for the vpu3 support, when the xo reset line must be asserted separately from the other reset line on power off operation. Factor the iris_init_resets() logic to allow requesting multiple reset tables. Reviewed-by: Bryan O'Donoghue Signed-off-by: Neil Armstrong Tested-by: Bryan O'Donoghue # x1e Dell=20 --- drivers/media/platform/qcom/iris/iris_core.h | 1 + .../platform/qcom/iris/iris_platform_common.h | 2 ++ drivers/media/platform/qcom/iris/iris_probe.c | 39 +++++++++++++++---= ---- 3 files changed, 30 insertions(+), 12 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/p= latform/qcom/iris/iris_core.h index 37fb4919fecc62182784b4dca90fcab47dd38a80..78143855b277cd3ebdc7a1e7f35= f6df284aa364c 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -82,6 +82,7 @@ struct iris_core { struct clk_bulk_data *clock_tbl; u32 clk_count; struct reset_control_bulk_data *resets; + struct reset_control_bulk_data *controller_resets; const struct iris_platform_data *iris_platform_data; enum iris_core_state state; dma_addr_t iface_q_table_daddr; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index f6b15d2805fb2004699709bb12cd7ce9b052180c..fdd40fd80178c4c66b37e392d07= a0a62f492f108 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -156,6 +156,8 @@ struct iris_platform_data { unsigned int clk_tbl_size; const char * const *clk_rst_tbl; unsigned int clk_rst_tbl_size; + const char * const *controller_rst_tbl; + unsigned int controller_rst_tbl_size; u64 dma_mask; const char *fwname; u32 pas_id; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index aca442dcc153830e6252d1dca87afb38c0b9eb8f..4f8bce6e2002bffee4c93dcaaf6= e52bf4e40992e 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -91,25 +91,40 @@ static int iris_init_clocks(struct iris_core *core) return 0; } =20 -static int iris_init_resets(struct iris_core *core) +static int iris_init_reset_table(struct iris_core *core, + struct reset_control_bulk_data **resets, + const char * const *rst_tbl, u32 rst_tbl_size) { - const char * const *rst_tbl; - u32 rst_tbl_size; u32 i =3D 0; =20 - rst_tbl =3D core->iris_platform_data->clk_rst_tbl; - rst_tbl_size =3D core->iris_platform_data->clk_rst_tbl_size; - - core->resets =3D devm_kzalloc(core->dev, - sizeof(*core->resets) * rst_tbl_size, - GFP_KERNEL); - if (!core->resets) + *resets =3D devm_kzalloc(core->dev, + sizeof(struct reset_control_bulk_data) * rst_tbl_size, + GFP_KERNEL); + if (!*resets) return -ENOMEM; =20 for (i =3D 0; i < rst_tbl_size; i++) - core->resets[i].id =3D rst_tbl[i]; + (*resets)[i].id =3D rst_tbl[i]; + + return devm_reset_control_bulk_get_exclusive(core->dev, rst_tbl_size, *re= sets); +} + +static int iris_init_resets(struct iris_core *core) +{ + int ret; + + ret =3D iris_init_reset_table(core, &core->resets, + core->iris_platform_data->clk_rst_tbl, + core->iris_platform_data->clk_rst_tbl_size); + if (ret) + return ret; + + if (!core->iris_platform_data->controller_rst_tbl_size) + return 0; =20 - return devm_reset_control_bulk_get_exclusive(core->dev, rst_tbl_size, cor= e->resets); + return iris_init_reset_table(core, &core->controller_resets, + core->iris_platform_data->controller_rst_tbl, + core->iris_platform_data->controller_rst_tbl_size); } =20 static int iris_init_resources(struct iris_core *core) --=20 2.34.1 From nobody Mon Feb 9 04:07:43 2026 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EB161FDE11 for ; Mon, 7 Apr 2025 15:24:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744039469; cv=none; b=Rp2a6bX12SpyUoGc5qUebJRav9BbNCSHPJio23YDI7AOHqoidAWqhZmo9jBs8XRpm6AQePmsktdN5vO4qLrVn7NMkjt8j1LCMvUAEH3qjnXBG/QqZag/dH/SNJvDSGzUyLiNTpt5KTSDJ7gz2TkXb8LxHrJtY/DuT3uE7dVdPcs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744039469; c=relaxed/simple; bh=IyC6JW//NbJzVtegnLef5xtYp51ySL42pB1CufF2oxE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=atx7UtVlPlnHTZyewl/QjNmWljdZH7rzqrOje9zGKcNMJPUu6+f69Ft5WzJoDnA7sGuhJuYrv41WPUCk9Et0yKffj4pfrwkmV5bG1N6pzCLk9hWH2jeRaZudaJUBvrVia29n3alsTfwg7Gl84KLqXDV1pDdRA3iMs7ghu/FkILs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=YHIJnjJG; arc=none smtp.client-ip=209.85.221.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="YHIJnjJG" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-3914a5def6bso2655634f8f.1 for ; Mon, 07 Apr 2025 08:24:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1744039463; x=1744644263; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=AtVW2rGRagVdMOph9/UNvZYKMcGWGQRR+J3UbKnxtRQ=; b=YHIJnjJGTON+IjyEPMFnQA1GN6Y2H4zjSP1dRLaDfOXFDSPHn8On1QoBBTaR3uegU3 Tjsm/xHzJXvDR8qKgzlGgDCHNGxUl1Pa+8YzqrWo6jkB6iL3Ma+WR6Qv3lZr5n5T7Mee i2DGE242j4ywr90/Gf5QmTBJGEx/psuRQJgd++MPGeorZb9fO7GGTXAHr6Hf52A+X87W iqKG5J7XLWmA0MCg0a2POtcEHqM5roThV+HWtjJEH5oHaQZgsvlpV3Y8hcojNPPGCu61 3UNsX+IgQn0ICIBvwz/YIiLD1c9W9avu3pYy9jN8+/6PKP2wMWXadbFaDq7VpHeOTNvq kSig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744039463; x=1744644263; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AtVW2rGRagVdMOph9/UNvZYKMcGWGQRR+J3UbKnxtRQ=; b=v7WAdbYdf2kWtL3lew9ipGNppWQrUYRI9vLn99Pi5YK5LcqFw1uqy3ERq9bjK/bp2L kUK5thKKEvyVxR39PGqxWcdbHXjOeBWHFu67dxd3h8scw5+DxJMbINtVky/G9TE/oCMN wPDSu4iCkXLyROC4OUJRCRpbcFfb/u2oTc8foIyiSiDveMGbNajCSZN/mB1FIbuZZvwE dgfi06ya3IAmeJ4padYsU6gS9NCJzeLgfSjhIMtSQYM6DnoX6pdiaUuMLZ2lrqA5KH7w ExGHsnhAvzieVg2+5G6FqlEBeqBY4YbRNbkzcKU77F1UIPENyXMl44HERDgPkMdhMaPB 6NVg== X-Forwarded-Encrypted: i=1; AJvYcCXYMBmcMpKY1OICJcoy9RervRfwAVBZFWQF/3080pQeE7kp17l/o/NLPOPZBh8iwSSyVuFr2ZIDk66zajY=@vger.kernel.org X-Gm-Message-State: AOJu0Yw6rwLWLkzeaxMq/6xIqs7nMFbbS6NHL4qTX7X1QmBtvDOkn1R9 zz2xoqX56q+ic8v+sVf4l55FMdRc3OgneGxi+zbD9ztg6vJIwFKIZpQu6o7ndpUVxZA5X0FrfI9 f X-Gm-Gg: ASbGncsZJ71LRzmidgMgTWeAb4ac9TJXnJYu6D55ir3+1i3CnPVSp1K99xZb0WyKzpg 6FqoeCIYT8YhY0ooD0yu60ZmnPm0Y3euoDds7F07pCMGmZxTpp/8fMExRb/o5jmBDnkPkZJ1AHy xbcDr0LejVrdg3Zgdl7RxnI3QEEVeVlOnVvl8YF/dkjzBa1E3bwveFWTvHIh5y3/vG27P9zcBFf 5B/rl6C01YzQjMAIoaWzCGJ/EV0/BH39kXyZpgKItPjhFbEKq4t9C/vaJclOcSEKsJcQaMI45GG D9QZLGc2GU6LnCf7Vgm3hIfV2YC5HwU2K3StdP8gRUjS2qNFYEaDbaGW9GYXfaHW6w== X-Google-Smtp-Source: AGHT+IFbcn28uMZN/VHUjDzDXKzulv27c+dG/hO7Xql0YkhQNwvzxwRfwlPVTt5OTVGfaiuaUTcl8Q== X-Received: by 2002:a05:6000:1a8d:b0:391:487f:282a with SMTP id ffacd0b85a97d-39cba93cdd3mr10870523f8f.50.1744039463476; Mon, 07 Apr 2025 08:24:23 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c301b42besm12212001f8f.41.2025.04.07.08.24.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 08:24:23 -0700 (PDT) From: Neil Armstrong Date: Mon, 07 Apr 2025 17:24:16 +0200 Subject: [PATCH v3 4/5] media: platform: qcom/iris: rename iris_vpu3 to iris_vpu3x Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250407-topic-sm8x50-iris-v10-v3-4-63569f6d04aa@linaro.org> References: <20250407-topic-sm8x50-iris-v10-v3-0-63569f6d04aa@linaro.org> In-Reply-To: <20250407-topic-sm8x50-iris-v10-v3-0-63569f6d04aa@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=16029; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=IyC6JW//NbJzVtegnLef5xtYp51ySL42pB1CufF2oxE=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBn8+4iwswrcFxiJoi81s3xGGFHQKofr0E8S771rlF0 qutd0eOJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ/PuIgAKCRB33NvayMhJ0SDED/ 9KIB7Cx1AySZFS5MkbZlh15EvXzpdgILWqpesKTPf+zv2HbkLUH+AY07gvKqeLoKDKW0TZnuJuHTop 7pDbYAeYkRAfdI77xbJ2NDopMiI7xFIddb8rIyEee464qcOjvvDDVVIYNixlayDmje1rJ3uCKuWZ0N y1Fjc6ifkoXTYToOyBraz4TB2o2Lk4TN5wBxGSbh28dGBlKnOjo2/72bRWAGNydxj6phjPqMrgXLVA 5axZwfa5eBpZ1Osic55dNGjShw75jTNpaWGYrfjTzUipLtoGtUcPCLevd8PYUG1WaQLTf13aBfD5Cs PjNGTcADC90Lb/RFDCqS14tMCTyXMI4BGhlshYxLmVwrQYLx2nYDF9LXhot46cf5yRpUWQGK5se0H8 d3pQyV7KkYfovh/cMZNxBEqQwlbSgV8KjR4GMmuKa+ceNaQh+BwqKwDhnsR37VpHjzfmeFVkYPpaHl YRPIqHpz1ccGLlZ1AE4Fbu44dMvv1bxjneMkYAQBAcOtgyh6G7Q6NG0I7t2uABLROADzTL+ysWbsCO hdlTGX82TxZYGPwYtvpgMROxRij2sW0lETu11czbi+rQZmADShldG1XcUqeygZ2BJZvmm13o4Ax8DU gojMKbLCkp7MJ2K2xGZiYAvrn/W4+sT7s6VU+0h+En8ZJvdH+HTpGUAk+aew== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The vpu33 HW is very close to vpu3, and shares most of the operations, so rename file to vpu3x since we'll handle all vpu3 variants in it. Reviewed-by: Dikshita Agarwal Signed-off-by: Neil Armstrong Tested-by: Bryan O'Donoghue # x1e Dell=20 --- drivers/media/platform/qcom/iris/Makefile | 2 +- drivers/media/platform/qcom/iris/iris_vpu3.c | 123 --------- drivers/media/platform/qcom/iris/iris_vpu3x.c | 277 +++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_vpu_common.h | 3 + 4 files changed, 281 insertions(+), 124 deletions(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 35390534534e93f4617c1036a05ca0921567ba1d..473aaf655448180ade917e64228= 9677fc1277f99 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -20,7 +20,7 @@ qcom-iris-objs +=3D \ iris_vb2.o \ iris_vdec.o \ iris_vpu2.o \ - iris_vpu3.o \ + iris_vpu3x.o \ iris_vpu_buffer.o \ iris_vpu_common.o \ =20 diff --git a/drivers/media/platform/qcom/iris/iris_vpu3.c b/drivers/media/p= latform/qcom/iris/iris_vpu3.c deleted file mode 100644 index 13dab61427b8bd0491b69a9bc5f5144d27d17362..000000000000000000000000000= 0000000000000 --- a/drivers/media/platform/qcom/iris/iris_vpu3.c +++ /dev/null @@ -1,123 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. - */ - -#include - -#include "iris_instance.h" -#include "iris_vpu_common.h" -#include "iris_vpu_register_defines.h" - -#define AON_MVP_NOC_RESET 0x0001F000 - -#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) -#define CORE_CLK_RUN 0x0 - -#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) -#define CORE_BRIDGE_SW_RESET BIT(0) -#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) - -#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) -#define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1)) - -#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004) - -#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) - -static bool iris_vpu3_hw_power_collapsed(struct iris_core *core) -{ - u32 value, pwr_status; - - value =3D readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); - pwr_status =3D value & BIT(1); - - return pwr_status ? false : true; -} - -static void iris_vpu3_power_off_hardware(struct iris_core *core) -{ - u32 reg_val =3D 0, value, i; - int ret; - - if (iris_vpu3_hw_power_collapsed(core)) - goto disable_power; - - dev_err(core->dev, "video hw is power on\n"); - - value =3D readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); - if (value) - writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); - - for (i =3D 0; i < core->iris_platform_data->num_vpp_pipe; i++) { - ret =3D readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN + 4 *= i, - reg_val, reg_val & 0x400000, 2000, 20000); - if (ret) - goto disable_power; - } - - writel(VIDEO_NOC_RESET_REQ, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_RE= Q); - - ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, - reg_val, reg_val & 0x3, 200, 2000); - if (ret) - goto disable_power; - - writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ); - - ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, - reg_val, !(reg_val & 0x3), 200, 2000); - if (ret) - goto disable_power; - - writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, - core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); - writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_S= YNC_RESET); - writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); - -disable_power: - iris_vpu_power_off_hw(core); -} - -static u64 iris_vpu3_calculate_frequency(struct iris_inst *inst, size_t da= ta_size) -{ - struct platform_inst_caps *caps =3D inst->core->iris_platform_data->inst_= caps; - struct v4l2_format *inp_f =3D inst->fmt_src; - u32 height, width, mbs_per_second, mbpf; - u64 fw_cycles, fw_vpp_cycles; - u64 vsp_cycles, vpp_cycles; - u32 fps =3D DEFAULT_FPS; - - width =3D max(inp_f->fmt.pix_mp.width, inst->crop.width); - height =3D max(inp_f->fmt.pix_mp.height, inst->crop.height); - - mbpf =3D NUM_MBS_PER_FRAME(height, width); - mbs_per_second =3D mbpf * fps; - - fw_cycles =3D fps * caps->mb_cycles_fw; - fw_vpp_cycles =3D fps * caps->mb_cycles_fw_vpp; - - vpp_cycles =3D mult_frac(mbs_per_second, caps->mb_cycles_vpp, (u32)inst->= fw_caps[PIPE].value); - /* 21 / 20 is minimum overhead factor */ - vpp_cycles +=3D max(div_u64(vpp_cycles, 20), fw_vpp_cycles); - - /* 1.059 is multi-pipe overhead */ - if (inst->fw_caps[PIPE].value > 1) - vpp_cycles +=3D div_u64(vpp_cycles * 59, 1000); - - vsp_cycles =3D fps * data_size * 8; - vsp_cycles =3D div_u64(vsp_cycles, 2); - /* VSP FW overhead 1.05 */ - vsp_cycles =3D div_u64(vsp_cycles * 21, 20); - - if (inst->fw_caps[STAGE].value =3D=3D STAGE_1) - vsp_cycles =3D vsp_cycles * 3; - - return max3(vpp_cycles, vsp_cycles, fw_cycles); -} - -const struct vpu_ops iris_vpu3_ops =3D { - .power_off_hw =3D iris_vpu3_power_off_hardware, - .power_off_controller =3D iris_vpu_power_off_controller, - .calc_freq =3D iris_vpu3_calculate_frequency, -}; diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c new file mode 100644 index 0000000000000000000000000000000000000000..ea7be2e0a3a255f61e236740e10= 82e7c9207250d --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#include +#include + +#include "iris_instance.h" +#include "iris_vpu_common.h" +#include "iris_vpu_register_defines.h" + +#define WRAPPER_TZ_BASE_OFFS 0x000C0000 +#define AON_BASE_OFFS 0x000E0000 +#define AON_MVP_NOC_RESET 0x0001F000 + +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54) +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) +#define REQ_POWER_DOWN_PREP BIT(0) +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) +#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) +#define CORE_CLK_RUN 0x0 + +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14) +#define CTL_AXI_CLK_HALT BIT(0) +#define CTL_CLK_HALT BIT(1) + +#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18) +#define RESET_HIGH BIT(0) + +#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) +#define CORE_BRIDGE_SW_RESET BIT(0) +#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) + +#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) +#define MSK_SIGNAL_FROM_TENSILICA BIT(0) +#define MSK_CORE_POWER_ON BIT(1) + +#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) +#define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1)) + +#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004) + +#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) + +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) + +#define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18) +#define SW_RESET BIT(0) +#define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20) +#define NOC_HALT BIT(0) +#define AON_WRAPPER_SPARE (AON_BASE_OFFS + 0x28) + +static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core) +{ + u32 value, pwr_status; + + value =3D readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); + pwr_status =3D value & BIT(1); + + return pwr_status ? false : true; +} + +static int iris_vpu3x_power_off_hardware_begin(struct iris_core *core) +{ + u32 reg_val =3D 0, value, i; + int ret; + + if (iris_vpu3x_hw_power_collapsed(core)) + return 1; + + dev_err(core->dev, "video hw is power on\n"); + + value =3D readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + if (value) + writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + + for (i =3D 0; i < core->iris_platform_data->num_vpp_pipe; i++) { + ret =3D readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN + 4 *= i, + reg_val, reg_val & 0x400000, 2000, 20000); + if (ret) + return ret; + } + + return 0; +} + +static void iris_vpu3x_power_off_hardware_end(struct iris_core *core) +{ + writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, + core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_S= YNC_RESET); + writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); +} + +static void iris_vpu3_power_off_hardware(struct iris_core *core) +{ + u32 reg_val =3D 0; + int ret; + + ret =3D iris_vpu3x_power_off_hardware_begin(core); + if (ret) + goto disable_power; + + writel(VIDEO_NOC_RESET_REQ, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_RE= Q); + + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, + reg_val, reg_val & 0x3, 200, 2000); + if (ret) + goto disable_power; + + writel(0x0, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_REQ); + + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, + reg_val, !(reg_val & 0x3), 200, 2000); + if (ret) + goto disable_power; + + iris_vpu3x_power_off_hardware_end(core); + +disable_power: + iris_vpu_power_off_hw(core); +} + +static void iris_vpu33_power_off_hardware(struct iris_core *core) +{ + u32 reg_val =3D 0; + int ret; + + ret =3D iris_vpu3x_power_off_hardware_begin(core); + if (ret) + goto disable_power; + + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATU= S, + reg_val, reg_val & BIT(0), 200, 2000); + if (ret) + goto disable_power; + + /* set MNoC to low power, set PD_NOC_QREQ (bit 0) */ + writel(BIT(0), core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + + iris_vpu3x_power_off_hardware_end(core); + +disable_power: + iris_vpu_power_off_hw(core); +} + +static int iris_vpu33_power_off_controller(struct iris_core *core) +{ + u32 xo_rst_tbl_size =3D core->iris_platform_data->controller_rst_tbl_size; + u32 clk_rst_tbl_size =3D core->iris_platform_data->clk_rst_tbl_size; + u32 val =3D 0; + int ret; + + writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CP= U_CS_X2RPMH); + + writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CON= TROL); + + ret =3D readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STAT= US, + val, val & BIT(0), 200, 2000); + if (ret) + goto disable_power; + + writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL); + + ret =3D readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STAT= US, + val, val =3D=3D 0, 200, 2000); + if (ret) + goto disable_power; + + writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT, + core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); + writel(RESET_HIGH, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET); + writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET); + writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); + + reset_control_bulk_reset(clk_rst_tbl_size, core->resets); + + /* Disable MVP NoC clock */ + val =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + val |=3D NOC_HALT; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + + /* enable MVP NoC reset */ + val =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + val |=3D SW_RESET; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + + /* poll AON spare register bit0 to become zero with 50ms timeout */ + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_SPARE, + val, (val & BIT(0)) =3D=3D 0, 1000, 50000); + if (ret) + goto disable_power; + + /* enable bit(1) to avoid cvp noc xo reset */ + val =3D readl(core->reg_base + AON_WRAPPER_SPARE); + val |=3D BIT(1); + writel(val, core->reg_base + AON_WRAPPER_SPARE); + + reset_control_bulk_assert(xo_rst_tbl_size, core->controller_resets); + + /* De-assert MVP NoC reset */ + val =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + val &=3D ~SW_RESET; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + + usleep_range(80, 100); + + reset_control_bulk_deassert(xo_rst_tbl_size, core->controller_resets); + + /* reset AON spare register */ + writel(0, core->reg_base + AON_WRAPPER_SPARE); + + /* Enable MVP NoC clock */ + val =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + val &=3D ~NOC_HALT; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); + +disable_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + + return 0; +} + +static u64 iris_vpu3x_calculate_frequency(struct iris_inst *inst, size_t d= ata_size) +{ + struct platform_inst_caps *caps =3D inst->core->iris_platform_data->inst_= caps; + struct v4l2_format *inp_f =3D inst->fmt_src; + u32 height, width, mbs_per_second, mbpf; + u64 fw_cycles, fw_vpp_cycles; + u64 vsp_cycles, vpp_cycles; + u32 fps =3D DEFAULT_FPS; + + width =3D max(inp_f->fmt.pix_mp.width, inst->crop.width); + height =3D max(inp_f->fmt.pix_mp.height, inst->crop.height); + + mbpf =3D NUM_MBS_PER_FRAME(height, width); + mbs_per_second =3D mbpf * fps; + + fw_cycles =3D fps * caps->mb_cycles_fw; + fw_vpp_cycles =3D fps * caps->mb_cycles_fw_vpp; + + vpp_cycles =3D mult_frac(mbs_per_second, caps->mb_cycles_vpp, (u32)inst->= fw_caps[PIPE].value); + /* 21 / 20 is minimum overhead factor */ + vpp_cycles +=3D max(div_u64(vpp_cycles, 20), fw_vpp_cycles); + + /* 1.059 is multi-pipe overhead */ + if (inst->fw_caps[PIPE].value > 1) + vpp_cycles +=3D div_u64(vpp_cycles * 59, 1000); + + vsp_cycles =3D fps * data_size * 8; + vsp_cycles =3D div_u64(vsp_cycles, 2); + /* VSP FW overhead 1.05 */ + vsp_cycles =3D div_u64(vsp_cycles * 21, 20); + + if (inst->fw_caps[STAGE].value =3D=3D STAGE_1) + vsp_cycles =3D vsp_cycles * 3; + + return max3(vpp_cycles, vsp_cycles, fw_cycles); +} + +const struct vpu_ops iris_vpu3_ops =3D { + .power_off_hw =3D iris_vpu3_power_off_hardware, + .power_off_controller =3D iris_vpu_power_off_controller, + .calc_freq =3D iris_vpu3x_calculate_frequency, +}; + +const struct vpu_ops iris_vpu33_ops =3D { + .power_off_hw =3D iris_vpu33_power_off_hardware, + .power_off_controller =3D iris_vpu33_power_off_controller, + .calc_freq =3D iris_vpu3x_calculate_frequency, +}; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index f8965661c602f990d5a7057565f79df4112d097e..4af3cb0d44e00be498fc7ba648c= 68f1ef2cb0f20 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -10,6 +10,7 @@ struct iris_core; =20 extern const struct vpu_ops iris_vpu2_ops; extern const struct vpu_ops iris_vpu3_ops; +extern const struct vpu_ops iris_vpu33_ops; =20 struct vpu_ops { void (*power_off_hw)(struct iris_core *core); @@ -23,6 +24,8 @@ void iris_vpu_clear_interrupt(struct iris_core *core); int iris_vpu_watchdog(struct iris_core *core, u32 intr_status); int iris_vpu_prepare_pc(struct iris_core *core); int iris_vpu_power_on(struct iris_core *core); +void iris_vpu_power_off_controller_begin(struct iris_core *core); +int iris_vpu_power_off_controller_end(struct iris_core *core); int iris_vpu_power_off_controller(struct iris_core *core); void iris_vpu_power_off_hw(struct iris_core *core); void iris_vpu_power_off(struct iris_core *core); --=20 2.34.1 From nobody Mon Feb 9 04:07:43 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06D651FE452 for ; Mon, 7 Apr 2025 15:24:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744039469; cv=none; b=MOPIzs9BJNSssrWyiGRktl2GDd4uMvI2DF5okP61R4Uh6pWH8P0LMv2/gMyeAb+xcuK5ebqUPhS7mhcIetrmA+65AJt5+/mV9xSGubsRPM//V8Fx4UBKC4x+SBFaXvKMfuh31qRXE5Vvq1YnsWqIjp0n8ETPSUcm/Gjt/MhP3KE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744039469; c=relaxed/simple; bh=neXImAtQA6tzq28UA2f7Fc6YFrL/8512jm9dsPst4Uw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KMSiWvOMwzQeRt+Q0StS/pHS1oxaO9FvdB7iokmcnOJu7P3oBIEoaXVrBDJ+AkERtooLVAWbtYv+MJUVbHy/Lq6ReeAuKGvKs5oOinC1kMGaAYyjxNBgzhOa7Y2/Es8hbdZJrSKkMlHtTkIb4n5NWWeTfEia6+0RkkKcl7MEzR0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=NU9DG/Kj; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="NU9DG/Kj" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-4394a0c65fcso42055685e9.1 for ; Mon, 07 Apr 2025 08:24:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1744039464; x=1744644264; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GvVRJL05EetY3b5wXnazV4Utq3Bno8ucEIV3aAjgwZI=; b=NU9DG/KjEbAZWy4uKneBAfMFo0Yy9+eLmoe1IzOUvWUQ1Al4VIJ4G7CTsdg/lzZFhG KNxVLVzlzkNz3XPqAViTtXdQa8PUmtMNRR5R6t9G3vrXrBD3OmO+QCwqDymuX3PSjnmj MBmrCH/TGvf3wKW/zxCsKljm1AvMQeyhpigiok2UdztOxNzTr1F+dIpHzlxGeoS4HNlV VFyISx+CIOGk7cEB4WiBnYXwyTPSr4pqa/7xJSf5R/2LcH+iPn0OgZ8FvrVCgdcF3Lea izIYNshs2wrx12X0bBQudaAt7ITnBn7dWchyalQMRyOgDH7Llvpj2T3knWzRsCuj+q6W r3BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744039464; x=1744644264; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GvVRJL05EetY3b5wXnazV4Utq3Bno8ucEIV3aAjgwZI=; b=Oi8HISGDVAYsQMlhLr/8ZJnnu1dRW9KiuKwlT7RLAf8ASsjoVBTBEEUAN8LAv9xyXt BKqbamJBq61UFK7CR2Sfe+kI3SfTJ/gdpKzR1SwnD7UutY0iGkY7XEJkx2FMWddQxkDi JduIhPNS7fj/WXTs5yEAZKMT4OHQbVLzEozmutLeb1VsSQfhW3NZQVTcoUhWy+S73sFW vov+dnyZ6Qqv65BoNZyE0tsla4ZNpQYGciG1IxI2FEPruc89S5bVJPPwRzvyKyWm+Jow zAwHDOaB2vHbcUV1ggZ1IXHFvBr64cutdOMQsl55BUVh7YF9kqbY37rp0n+uBgrr9KL/ WdzA== X-Forwarded-Encrypted: i=1; AJvYcCXAOHh0hi/q9hrZURltWDra7ws7LPOj/LegmJMuB2nJPCZxdQHHiVMO0aqQ5o+/KHD/0+8I8Jg/2CF7FAc=@vger.kernel.org X-Gm-Message-State: AOJu0Yz+cC3deL23bZrX29U7sFaH6aXNtJBpHdNPl18kSg6oeCtAjJ8n qB1cB8Qe3u+7F2HN5+FVCUo7szK2/xBu4xE39WKlmHoEb5ClIAatddfUD5Jt3Aef7OzJvGykrpm s X-Gm-Gg: ASbGncupzXMmgrf7n5FaVueTJ+KTBpUwhvDvWYOxE0KWVvOkwy713sbM/oxpn6GoPwA bwPF56ssMRvD3UlPJvFpC4tqw6f/vnVAgJ3jvmY0fU+p0ugeardPDSdLBBZwqVUJZOZ3rbrfYTA X1fMxtneNG/GbnkCXMAw/iEo0HFx+JmEu3ZxiWSFE4LN7jLBsxoZ7tz/ZJ1TECQQsrFO1Ve+1Qy QRJKLeR7ogUv3sYbc8w04YVattGqQ9icQTbLBWFFtOkVbi90Cp6qn4V06Dq2c9kOebaEZ2vSptF P/xHEC4IENWOq65VOkSWH/4ah5QOnkFQ4xHGZU1pUcrQyaBEOR/Ncmi1knaZfirtcA== X-Google-Smtp-Source: AGHT+IHBRqMiDiPVAjeRnWAr5LUDeSmE9wHz0sfR5rKfiXLkQ3xumNNQLM66y4ktKIF4vGMuDePqHw== X-Received: by 2002:a05:6000:430c:b0:391:47d8:de2d with SMTP id ffacd0b85a97d-39cba93382fmr10973353f8f.23.1744039464251; Mon, 07 Apr 2025 08:24:24 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:3d9:2080:52eb:f6ff:feb3:451a]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c301b42besm12212001f8f.41.2025.04.07.08.24.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Apr 2025 08:24:23 -0700 (PDT) From: Neil Armstrong Date: Mon, 07 Apr 2025 17:24:17 +0200 Subject: [PATCH v3 5/5] media: platform: qcom/iris: add sm8650 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250407-topic-sm8x50-iris-v10-v3-5-63569f6d04aa@linaro.org> References: <20250407-topic-sm8x50-iris-v10-v3-0-63569f6d04aa@linaro.org> In-Reply-To: <20250407-topic-sm8x50-iris-v10-v3-0-63569f6d04aa@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5217; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=neXImAtQA6tzq28UA2f7Fc6YFrL/8512jm9dsPst4Uw=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBn8+4j0nULgROhyU7aboOye/k8H2jz5sPE6W1sl6I6 s+uzY5aJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ/PuIwAKCRB33NvayMhJ0VuyD/ 40kl4zHzWK5Xmkv75+p6h9FHxrRPpglQiiMrtp7UVlwXQ2uhLsV+aYatTw6HY1AY1Ei06uYIcfme7t Zg9fO262jpl9i1KLUVXt8Mkx/FuZlKLwRU/RCdFpVJOfqynGfOlDkOoKoyLM9K7R8jxvezN9NZOqES 5wm9T7PDdvULxzzDte08K+0u8o2HQjKA/fzZzoYjOX/o0WiXXqbQzhh/IIi+gFxxW3Mjt2V+bqmVRQ tSxlEpHs6LbLGIUar2gd58yqxrVWfJ7G8DMS0PsaHx22V0Cu8Kw/xiuQ4wmat3te11JBSKLJ4D8iXW 8zsoNanTyCG0wpBGmpZSmthsEpZMnBabpy6RVIPxDKJ1qROkVaWikduUyCfw5Cqj6+A06bO61YrhWn zLHD9ySNmVzxGUnOH12pTC27VRpcsSVQo5mhRaC6N/9M7SMENGlRvB7j5kzOAGCrDkX53TalNGZW+o YVLdilahUVTONrJLYlCuv5vt5NOkxOOTG7p+3dPWGbD+lykd9Z8L8lgMcQA3UMpb8PrGYnEKn0Y0yZ kvZ3PJ+htkS27SzwIrmmLVZq/Vv9/5ZGsNphXLIIEvab6APnl7JqY1j9/Q5wtQdILSd0Wns9k9rwvi gTJc3vweAqEZEKQ8aQsY/NOyWQ8Cjg+hg8JQNtBlfVJDxa+JOfy2qjSEeL6g== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add support for the SM8650 platform by re-using the SM8550 definitions and using the vpu33 ops. The SM8650/vpu33 requires more reset lines, but the H.284 decoder capabilities are identical. Signed-off-by: Neil Armstrong Tested-by: Bryan O'Donoghue # x1e Dell=20 --- .../platform/qcom/iris/iris_platform_common.h | 1 + .../platform/qcom/iris/iris_platform_sm8550.c | 64 ++++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 ++ 3 files changed, 69 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index fdd40fd80178c4c66b37e392d07a0a62f492f108..6bc3a7975b04d612f6c89206eae= 95dac678695fc 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -35,6 +35,7 @@ enum pipe_type { =20 extern struct iris_platform_data sm8250_data; extern struct iris_platform_data sm8550_data; +extern struct iris_platform_data sm8650_data; =20 enum platform_clk_type { IRIS_AXI_CLK, diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8550.c index 35d278996c430f2856d0fe59586930061a271c3e..d0f8fa960d53367023e41bc5807= ba3f8beae2efc 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8550.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.c @@ -144,6 +144,10 @@ static const struct icc_info sm8550_icc_table[] =3D { =20 static const char * const sm8550_clk_reset_table[] =3D { "bus" }; =20 +static const char * const sm8650_clk_reset_table[] =3D { "bus", "core" }; + +static const char * const sm8650_controller_reset_table[] =3D { "xo" }; + static const struct bw_info sm8550_bw_table_dec[] =3D { { ((4096 * 2160) / 256) * 60, 1608000 }, { ((4096 * 2160) / 256) * 30, 826000 }, @@ -264,3 +268,63 @@ struct iris_platform_data sm8550_data =3D { .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), }; + +/* + * Shares most of SM8550 data except: + * - vpu_ops to iris_vpu33_ops + * - clk_rst_tbl to sm8650_clk_reset_table + * - controller_rst_tbl to sm8650_controller_reset_table + * - fwname to "qcom/vpu/vpu33_p4.mbn" + */ +struct iris_platform_data sm8650_data =3D { + .get_instance =3D iris_hfi_gen2_get_instance, + .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, + .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, + .vpu_ops =3D &iris_vpu33_ops, + .set_preset_registers =3D iris_set_sm8550_preset_registers, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D sm8650_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8650_clk_reset_table), + .controller_rst_tbl =3D sm8650_controller_reset_table, + .controller_rst_tbl_size =3D ARRAY_SIZE(sm8650_controller_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D sm8550_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu33_p4.mbn", + .pas_id =3D IRIS_PAS_ID, + .inst_caps =3D &platform_inst_cap_sm8550, + .inst_fw_caps =3D inst_fw_cap_sm8550, + .inst_fw_caps_size =3D ARRAY_SIZE(inst_fw_cap_sm8550), + .tz_cp_config_data =3D &tz_cp_config_sm8550, + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .ubwc_config =3D &ubwc_config_sm8550, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D ((8192 * 4352) / 256) * 2, + .input_config_params =3D + sm8550_vdec_input_config_params, + .input_config_params_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_params), + .output_config_params =3D + sm8550_vdec_output_config_params, + .output_config_params_size =3D + ARRAY_SIZE(sm8550_vdec_output_config_params), + .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, + .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), + .dec_output_prop =3D sm8550_vdec_subscribe_output_properties, + .dec_output_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_output_propert= ies), + + .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), +}; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index 4f8bce6e2002bffee4c93dcaaf6e52bf4e40992e..7cd8650fbe9c09598670530103e= 3d5edf32953e7 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -345,6 +345,10 @@ static const struct of_device_id iris_dt_match[] =3D { .data =3D &sm8250_data, }, #endif + { + .compatible =3D "qcom,sm8650-iris", + .data =3D &sm8650_data, + }, { }, }; MODULE_DEVICE_TABLE(of, iris_dt_match); --=20 2.34.1