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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Enable QoS configuration for master ports with predefined values for priority and urgency forwarding. Signed-off-by: Neil Armstrong --- drivers/interconnect/qcom/sm8650.c | 327 +++++++++++++++++++++++++++++++++= ++++ 1 file changed, 327 insertions(+) diff --git a/drivers/interconnect/qcom/sm8650.c b/drivers/interconnect/qcom= /sm8650.c index 20ac5bc5e1fbafe74800ad6f22839bac006ca7db..f6911891503a7ed65be8bc37ed6= 00e87d4cfcc42 100644 --- a/drivers/interconnect/qcom/sm8650.c +++ b/drivers/interconnect/qcom/sm8650.c @@ -17,20 +17,45 @@ #include "icc-rpmh.h" #include "sm8650.h" =20 +static const struct regmap_config icc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .fast_io =3D true, +}; + +static struct qcom_icc_qosbox qhm_qspi_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qhm_qspi =3D { .name =3D "qhm_qspi", .id =3D SM8650_MASTER_QSPI_0, .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &qhm_qspi_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_A1NOC_SNOC }, }; =20 +static struct qcom_icc_qosbox qhm_qup1_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xd000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qhm_qup1 =3D { .name =3D "qhm_qup1", .id =3D SM8650_MASTER_QUP_1, .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &qhm_qup1_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_A1NOC_SNOC }, }; @@ -44,65 +69,128 @@ static struct qcom_icc_node qxm_qup02 =3D { .links =3D { SM8650_SLAVE_A1NOC_SNOC }, }; =20 +static struct qcom_icc_qosbox xm_sdc4_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xe000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node xm_sdc4 =3D { .name =3D "xm_sdc4", .id =3D SM8650_MASTER_SDCC_4, .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_sdc4_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_A1NOC_SNOC }, }; =20 +static struct qcom_icc_qosbox xm_ufs_mem_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xf000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node xm_ufs_mem =3D { .name =3D "xm_ufs_mem", .id =3D SM8650_MASTER_UFS_MEM, .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &xm_ufs_mem_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_A1NOC_SNOC }, }; =20 +static struct qcom_icc_qosbox xm_usb3_0_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x10000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node xm_usb3_0 =3D { .name =3D "xm_usb3_0", .id =3D SM8650_MASTER_USB3_0, .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_usb3_0_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_A1NOC_SNOC }, }; =20 +static struct qcom_icc_qosbox qhm_qdss_bam_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qhm_qdss_bam =3D { .name =3D "qhm_qdss_bam", .id =3D SM8650_MASTER_QDSS_BAM, .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &qhm_qdss_bam_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_A2NOC_SNOC }, }; =20 +static struct qcom_icc_qosbox qhm_qup2_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qhm_qup2 =3D { .name =3D "qhm_qup2", .id =3D SM8650_MASTER_QUP_2, .channels =3D 1, .buswidth =3D 4, + .qosbox =3D &qhm_qup2_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_A2NOC_SNOC }, }; =20 +static struct qcom_icc_qosbox qxm_crypto_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qxm_crypto =3D { .name =3D "qxm_crypto", .id =3D SM8650_MASTER_CRYPTO, .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qxm_crypto_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_A2NOC_SNOC }, }; =20 +static struct qcom_icc_qosbox qxm_ipa_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qxm_ipa =3D { .name =3D "qxm_ipa", .id =3D SM8650_MASTER_IPA, .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qxm_ipa_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_A2NOC_SNOC }, }; @@ -116,29 +204,56 @@ static struct qcom_icc_node qxm_sp =3D { .links =3D { SM8650_SLAVE_A2NOC_SNOC }, }; =20 +static struct qcom_icc_qosbox xm_qdss_etr_0_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x17000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node xm_qdss_etr_0 =3D { .name =3D "xm_qdss_etr_0", .id =3D SM8650_MASTER_QDSS_ETR, .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_qdss_etr_0_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_A2NOC_SNOC }, }; =20 +static struct qcom_icc_qosbox xm_qdss_etr_1_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x18000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node xm_qdss_etr_1 =3D { .name =3D "xm_qdss_etr_1", .id =3D SM8650_MASTER_QDSS_ETR_1, .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_qdss_etr_1_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_A2NOC_SNOC }, }; =20 +static struct qcom_icc_qosbox xm_sdc2_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x19000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node xm_sdc2 =3D { .name =3D "xm_sdc2", .id =3D SM8650_MASTER_SDCC_2, .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_sdc2_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_A2NOC_SNOC }, }; @@ -223,29 +338,56 @@ static struct qcom_icc_node qnm_gemnoc_pcie =3D { .links =3D { SM8650_SLAVE_PCIE_0, SM8650_SLAVE_PCIE_1 }, }; =20 +static struct qcom_icc_qosbox alm_gpu_tcu_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xbf000 }, + .prio =3D 1, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + static struct qcom_icc_node alm_gpu_tcu =3D { .name =3D "alm_gpu_tcu", .id =3D SM8650_MASTER_GPU_TCU, .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &alm_gpu_tcu_qos, .num_links =3D 2, .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, }; =20 +static struct qcom_icc_qosbox alm_sys_tcu_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xc1000 }, + .prio =3D 6, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + static struct qcom_icc_node alm_sys_tcu =3D { .name =3D "alm_sys_tcu", .id =3D SM8650_MASTER_SYS_TCU, .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &alm_sys_tcu_qos, .num_links =3D 2, .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, }; =20 +static struct qcom_icc_qosbox alm_ubwc_p_tcu_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xc5000 }, + .prio =3D 1, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + static struct qcom_icc_node alm_ubwc_p_tcu =3D { .name =3D "alm_ubwc_p_tcu", .id =3D SM8650_MASTER_UBWC_P_TCU, .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &alm_ubwc_p_tcu_qos, .num_links =3D 2, .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, }; @@ -260,20 +402,38 @@ static struct qcom_icc_node chm_apps =3D { SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, }; =20 +static struct qcom_icc_qosbox qnm_gpu_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x31000, 0x71000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, +}; + static struct qcom_icc_node qnm_gpu =3D { .name =3D "qnm_gpu", .id =3D SM8650_MASTER_GFX3D, .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &qnm_gpu_qos, .num_links =3D 2, .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, }; =20 +static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xb5000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qnm_lpass_gemnoc =3D { .name =3D "qnm_lpass_gemnoc", .id =3D SM8650_MASTER_LPASS_GEM_NOC, .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &qnm_lpass_gemnoc_qos, .num_links =3D 3, .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, @@ -289,67 +449,130 @@ static struct qcom_icc_node qnm_mdsp =3D { SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, }; =20 +static struct qcom_icc_qosbox qnm_mnoc_hf_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x33000, 0x73000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qnm_mnoc_hf =3D { .name =3D "qnm_mnoc_hf", .id =3D SM8650_MASTER_MNOC_HF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &qnm_mnoc_hf_qos, .num_links =3D 2, .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, }; =20 +static struct qcom_icc_qosbox qnm_mnoc_sf_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x35000, 0x75000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qnm_mnoc_sf =3D { .name =3D "qnm_mnoc_sf", .id =3D SM8650_MASTER_MNOC_SF_MEM_NOC, .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &qnm_mnoc_sf_qos, .num_links =3D 2, .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, }; =20 +static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x37000, 0x77000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, +}; + static struct qcom_icc_node qnm_nsp_gemnoc =3D { .name =3D "qnm_nsp_gemnoc", .id =3D SM8650_MASTER_COMPUTE_NOC, .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &qnm_nsp_gemnoc_qos, .num_links =3D 3, .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, }; =20 +static struct qcom_icc_qosbox qnm_pcie_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xb7000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qnm_pcie =3D { .name =3D "qnm_pcie", .id =3D SM8650_MASTER_ANOC_PCIE_GEM_NOC, .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &qnm_pcie_qos, .num_links =3D 2, .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC }, }; =20 +static struct qcom_icc_qosbox qnm_snoc_sf_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xbb000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qnm_snoc_sf =3D { .name =3D "qnm_snoc_sf", .id =3D SM8650_MASTER_SNOC_SF_MEM_NOC, .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &qnm_snoc_sf_qos, .num_links =3D 3, .links =3D { SM8650_SLAVE_GEM_NOC_CNOC, SM8650_SLAVE_LLCC, SM8650_SLAVE_MEM_NOC_PCIE_SNOC }, }; =20 +static struct qcom_icc_qosbox qnm_ubwc_p_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xc3000 }, + .prio =3D 1, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, +}; + static struct qcom_icc_node qnm_ubwc_p =3D { .name =3D "qnm_ubwc_p", .id =3D SM8650_MASTER_UBWC_P, .channels =3D 1, .buswidth =3D 32, + .qosbox =3D &qnm_ubwc_p_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_LLCC }, }; =20 +static struct qcom_icc_qosbox xm_gic_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xb9000 }, + .prio =3D 4, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + static struct qcom_icc_node xm_gic =3D { .name =3D "xm_gic", .id =3D SM8650_MASTER_GIC, .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_gic_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_LLCC }, }; @@ -390,38 +613,74 @@ static struct qcom_icc_node llcc_mc =3D { .links =3D { SM8650_SLAVE_EBI1 }, }; =20 +static struct qcom_icc_qosbox qnm_camnoc_hf_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x28000, 0x29000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qnm_camnoc_hf =3D { .name =3D "qnm_camnoc_hf", .id =3D SM8650_MASTER_CAMNOC_HF, .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &qnm_camnoc_hf_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_MNOC_HF_MEM_NOC }, }; =20 +static struct qcom_icc_qosbox qnm_camnoc_icp_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x2a000 }, + .prio =3D 4, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qnm_camnoc_icp =3D { .name =3D "qnm_camnoc_icp", .id =3D SM8650_MASTER_CAMNOC_ICP, .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qnm_camnoc_icp_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_MNOC_SF_MEM_NOC }, }; =20 +static struct qcom_icc_qosbox qnm_camnoc_sf_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x2b000, 0x2c000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qnm_camnoc_sf =3D { .name =3D "qnm_camnoc_sf", .id =3D SM8650_MASTER_CAMNOC_SF, .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &qnm_camnoc_sf_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_MNOC_SF_MEM_NOC }, }; =20 +static struct qcom_icc_qosbox qnm_mdp_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x2d000, 0x2e000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qnm_mdp =3D { .name =3D "qnm_mdp", .id =3D SM8650_MASTER_MDP, .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &qnm_mdp_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_MNOC_HF_MEM_NOC }, }; @@ -435,38 +694,74 @@ static struct qcom_icc_node qnm_vapss_hcp =3D { .links =3D { SM8650_SLAVE_MNOC_SF_MEM_NOC }, }; =20 +static struct qcom_icc_qosbox qnm_video_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x30000, 0x31000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qnm_video =3D { .name =3D "qnm_video", .id =3D SM8650_MASTER_VIDEO, .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &qnm_video_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_MNOC_SF_MEM_NOC }, }; =20 +static struct qcom_icc_qosbox qnm_video_cv_cpu_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x32000 }, + .prio =3D 4, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qnm_video_cv_cpu =3D { .name =3D "qnm_video_cv_cpu", .id =3D SM8650_MASTER_VIDEO_CV_PROC, .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qnm_video_cv_cpu_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_MNOC_SF_MEM_NOC }, }; =20 +static struct qcom_icc_qosbox qnm_video_cvp_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x33000, 0x34000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qnm_video_cvp =3D { .name =3D "qnm_video_cvp", .id =3D SM8650_MASTER_VIDEO_PROC, .channels =3D 2, .buswidth =3D 32, + .qosbox =3D &qnm_video_cvp_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_MNOC_SF_MEM_NOC }, }; =20 +static struct qcom_icc_qosbox qnm_video_v_cpu_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x35000 }, + .prio =3D 4, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node qnm_video_v_cpu =3D { .name =3D "qnm_video_v_cpu", .id =3D SM8650_MASTER_VIDEO_V_PROC, .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &qnm_video_v_cpu_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_MNOC_SF_MEM_NOC }, }; @@ -498,20 +793,38 @@ static struct qcom_icc_node qsm_pcie_anoc_cfg =3D { .links =3D { SM8650_SLAVE_SERVICE_PCIE_ANOC }, }; =20 +static struct qcom_icc_qosbox xm_pcie3_0_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio =3D 3, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node xm_pcie3_0 =3D { .name =3D "xm_pcie3_0", .id =3D SM8650_MASTER_PCIE_0, .channels =3D 1, .buswidth =3D 8, + .qosbox =3D &xm_pcie3_0_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_ANOC_PCIE_GEM_NOC }, }; =20 +static struct qcom_icc_qosbox xm_pcie3_1_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, +}; + static struct qcom_icc_node xm_pcie3_1 =3D { .name =3D "xm_pcie3_1", .id =3D SM8650_MASTER_PCIE_1, .channels =3D 1, .buswidth =3D 16, + .qosbox =3D &xm_pcie3_1_qos, .num_links =3D 1, .links =3D { SM8650_SLAVE_ANOC_PCIE_GEM_NOC }, }; @@ -1325,6 +1638,7 @@ static struct qcom_icc_node * const aggre1_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8650_aggre1_noc =3D { + .config =3D &icc_regmap_config, .nodes =3D aggre1_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), }; @@ -1346,6 +1660,7 @@ static struct qcom_icc_node * const aggre2_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8650_aggre2_noc =3D { + .config =3D &icc_regmap_config, .nodes =3D aggre2_noc_nodes, .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), .bcms =3D aggre2_noc_bcms, @@ -1368,6 +1683,7 @@ static struct qcom_icc_node * const clk_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8650_clk_virt =3D { + .config =3D &icc_regmap_config, .nodes =3D clk_virt_nodes, .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), .bcms =3D clk_virt_bcms, @@ -1429,6 +1745,7 @@ static struct qcom_icc_node * const config_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8650_config_noc =3D { + .config =3D &icc_regmap_config, .nodes =3D config_noc_nodes, .num_nodes =3D ARRAY_SIZE(config_noc_nodes), .bcms =3D config_noc_bcms, @@ -1456,6 +1773,7 @@ static struct qcom_icc_node * const cnoc_main_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sm8650_cnoc_main =3D { + .config =3D &icc_regmap_config, .nodes =3D cnoc_main_nodes, .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), .bcms =3D cnoc_main_bcms, @@ -1488,6 +1806,7 @@ static struct qcom_icc_node * const gem_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8650_gem_noc =3D { + .config =3D &icc_regmap_config, .nodes =3D gem_noc_nodes, .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), .bcms =3D gem_noc_bcms, @@ -1500,6 +1819,7 @@ static struct qcom_icc_node * const lpass_ag_noc_node= s[] =3D { }; =20 static const struct qcom_icc_desc sm8650_lpass_ag_noc =3D { + .config =3D &icc_regmap_config, .nodes =3D lpass_ag_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), }; @@ -1514,6 +1834,7 @@ static struct qcom_icc_node * const lpass_lpiaon_noc_= nodes[] =3D { }; =20 static const struct qcom_icc_desc sm8650_lpass_lpiaon_noc =3D { + .config =3D &icc_regmap_config, .nodes =3D lpass_lpiaon_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpiaon_noc_nodes), .bcms =3D lpass_lpiaon_noc_bcms, @@ -1526,6 +1847,7 @@ static struct qcom_icc_node * const lpass_lpicx_noc_n= odes[] =3D { }; =20 static const struct qcom_icc_desc sm8650_lpass_lpicx_noc =3D { + .config =3D &icc_regmap_config, .nodes =3D lpass_lpicx_noc_nodes, .num_nodes =3D ARRAY_SIZE(lpass_lpicx_noc_nodes), }; @@ -1541,6 +1863,7 @@ static struct qcom_icc_node * const mc_virt_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8650_mc_virt =3D { + .config =3D &icc_regmap_config, .nodes =3D mc_virt_nodes, .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), .bcms =3D mc_virt_bcms, @@ -1569,6 +1892,7 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8650_mmss_noc =3D { + .config =3D &icc_regmap_config, .nodes =3D mmss_noc_nodes, .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), .bcms =3D mmss_noc_bcms, @@ -1585,6 +1909,7 @@ static struct qcom_icc_node * const nsp_noc_nodes[] = =3D { }; =20 static const struct qcom_icc_desc sm8650_nsp_noc =3D { + .config =3D &icc_regmap_config, .nodes =3D nsp_noc_nodes, .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), .bcms =3D nsp_noc_bcms, @@ -1604,6 +1929,7 @@ static struct qcom_icc_node * const pcie_anoc_nodes[]= =3D { }; =20 static const struct qcom_icc_desc sm8650_pcie_anoc =3D { + .config =3D &icc_regmap_config, .nodes =3D pcie_anoc_nodes, .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), .bcms =3D pcie_anoc_bcms, @@ -1623,6 +1949,7 @@ static struct qcom_icc_node * const system_noc_nodes[= ] =3D { }; =20 static const struct qcom_icc_desc sm8650_system_noc =3D { + .config =3D &icc_regmap_config, .nodes =3D system_noc_nodes, .num_nodes =3D ARRAY_SIZE(system_noc_nodes), .bcms =3D system_noc_bcms, --- base-commit: 2bdde620f7f2bff2ff1cb7dc166859eaa0c78a7c change-id: 20250407-topic-sm8650-upstream-icc-qos-ebc5bee4896d Best regards, --=20 Neil Armstrong