From nobody Fri Dec 19 18:41:44 2025 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31980224B07; Mon, 7 Apr 2025 04:46:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744001200; cv=none; b=CNbbz32I1Wb/MMvhMf1eY+3SGcpSiPpg5qUYa57HujYoyKtYpwTN780yivpwmbGc6Is2bPAMjiWcA7AJzfrEYg4jeTbBt/MAZ2Dr6I0knYxWFMWohKfMdRKMYS/xcJ3qJ6Kf2Pk+G9bb7A7DMUYGN/teLAipB0yrZK0dwSyfZtk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1744001200; c=relaxed/simple; bh=EBSRx3c6U11weHNs7rjc5+muXlHyhv1nGdUlu9ALZYY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oyoOFSxmPl+Y0uH6zl3qp9tWqBC/Wi61ag9/dRhTVP/rLy3TfV5wIdR5YkRzsYGknVm8ThVcO+FqaDQEwnzJoPaHrB34+Xy362nnnpVW4vrJwmOaCtM/IlCSCFae44Oh6wZLctfGwJB32+b8nJAZtYmPZi28ueYe153x7Y1Fmgg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=N2ODXEZa; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="N2ODXEZa" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-224100e9a5cso38507745ad.2; Sun, 06 Apr 2025 21:46:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1744001197; x=1744605997; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Zud0rDyPmRtSFEeCjx+6zO9A4fHC48w3npIiibg9sIk=; b=N2ODXEZaCABihEHinswzX26PK+vpLxOg9GSDj/gu77qFGolrhor0sbSC1pEVasq536 Ks+qerGHo2Ij9Hr5xpcUzTNS6ahV1jlp8nLoV9dr7DdxOY9/Ek06+sTby6LW39TlPbcz D5QvezHTlaH3vJq1eZg86EcWBgF6NBOr7sGXIMOav38hLvbdaev0/AjFA8pusM3bn6Es 3sviCr5BuIVjBICpn/9rZeOoRhQiCbA1n87pHk2KzKFE4PzKcUn8fa02P2htRLsQucnn K1Xu6ggpl81vaOrSN+ZZWQaYZNOEQNnRGGBZNCxnfkqNdLD+F0jKB4alUpRAynKdB7ih 36Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1744001197; x=1744605997; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zud0rDyPmRtSFEeCjx+6zO9A4fHC48w3npIiibg9sIk=; b=JXx0VMVX4Sh857CrAXbMruoyhJgWVmkRfqQDI9EUVKoRnhBQjCpjUk5mqrCVa8WOSl fFe4pp/pToXbJLlTG+FsSEslSLNRW2fPFRobq5LC7xdY4Hxy8SWVMTqDlh3bCdh1F6dK hqYfikuh7WLT1GUQlCU/hSkItlOp/mKwFS7Pnfgg4XqYvEMnY4MWXT5AEDDdbyS8XH5m mR1/xQ8u2JrQ+0TSk0vSL2ePw2TZi0ZmGqD7PohtcJnIrC7kTC9DUQOAkPIhqehvKe7x pyV8aeIKnj8Qn9ok29Op/3/cQ9ck3wI37Hcasnb9c+kpPLyS7oJiojL63jdP9mnLg8Pc ja1g== X-Forwarded-Encrypted: i=1; AJvYcCVRnLX9p/9jEXSM7vlK4v4Pa/DoESXmVnXKGVqP97HmEd1mRatEObaWCnkr/ElHAtggdlOpye3FKig4@vger.kernel.org, AJvYcCVv2nMCKCSmysOYUA7qj4B39L8nYdrBLr//Si0q72kGY3Hz2KYIHzj0xYmRwQo+c1OhyUMOi/rvInoK/DJu+xXMvw==@vger.kernel.org, AJvYcCXKqYZHEH486BtdfTUqCgOQU7+7tnJOHSWRucSdkZwso6lgHwItJpQWpZEHoorFj4IIjTO2gAQPJ5r9M0+4@vger.kernel.org X-Gm-Message-State: AOJu0Yw1mMJs+drblGlGTNfFPAlFzh/6f5zjSlYOu0Nw6Tf8DVrEGowO qdIPak0g51+wLILnHXNpiuksJRI7MxAdFylgjcMTWXkQsVe/lPbS X-Gm-Gg: ASbGncumPryefSkxIweKYUR9rmIvbAIMXL3n8V4URSFdoPBeW6JDswipi8wpePhGtws TAoQw9K1Ot2r4NNLGs/ECvw+myHsM8f0UGgkxC0H26i36vNJ9wYb1qO90xIBnseGBsbQ6cx/HEn 9L5CrkF+R6C99Lyy69n8lDUKeqvJwF941rxKaIxC1SsNseQ+ccXM75DWyrxSy4H1d/vWK6MKKLa +aDVIpsgLkCNspn8Tr9w0LuOK3N0uwxpsy6FCBK+Q6A+u0uBIMHmnytFTk+wTexgI2+90d7b2Wc fHCUereHHXUZ2+l0FwcIlbXhB31VXJmVCiGMGy8j9TLpwJY= X-Google-Smtp-Source: AGHT+IGrce1mBrQ75bMWOKr5pnkTISyTTooIdkYs/K+rg66FCC1sePPVuxATydtj0PbZcFRSINu9cw== X-Received: by 2002:a17:902:ce0e:b0:223:44c5:4eb8 with SMTP id d9443c01a7336-22a8a8ced6cmr167560365ad.32.1744001197471; Sun, 06 Apr 2025 21:46:37 -0700 (PDT) Received: from [127.0.1.1] ([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id 98e67ed59e1d1-305983b9954sm7765810a91.32.2025.04.06.21.46.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Apr 2025 21:46:37 -0700 (PDT) From: Nick Chan Date: Mon, 07 Apr 2025 12:45:19 +0800 Subject: [PATCH v6 10/21] drivers/perf: apple_m1: Add A9/A9X support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250407-apple-cpmu-v6-10-ae8c2f225c1f@gmail.com> References: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> In-Reply-To: <20250407-apple-cpmu-v6-0-ae8c2f225c1f@gmail.com> To: Will Deacon , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Sven Peter , Janne Grunau , Alyssa Rosenzweig , Neal Gompa Cc: Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Nick Chan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6996; i=towinchenmi@gmail.com; h=from:subject:message-id; bh=EBSRx3c6U11weHNs7rjc5+muXlHyhv1nGdUlu9ALZYY=; b=owEBbQKS/ZANAwAIAQHKCLemxQgkAcsmYgBn81iHbvjGMv3E3nVhfdRC0ToUvKj3c6SLPsemX afF5JH1SGqJAjMEAAEIAB0WIQRLUnh4XJes95w8aIMBygi3psUIJAUCZ/NYhwAKCRABygi3psUI JM/JEACOplQrm5dKEd+SLJzEidNxKrwxlo5QKNgbDImicP3w2i9ctY9mLFtesfWYOCJWMzFw9OD BKuHHgLPZUZH5AgZyuHLote7YUOaX0Xu+y9i7cfMCZMOztyXSqBI4fYNi6sUjC7/qCxjT4wsKRa psG5ckXa/T/nf7e56rSCxrf1XdxDB0R8DfqZi1zGfKLX1KYYTfkS64nen4J0l8SLnyjHXynsmpK uxROeaETXMBInXEZ2GxK5kJFdz2RLRW1wcVnd737qETyfxn4nUfNl9VhTySlph5qka3YNeRDtaX UX7wzk8k/5FnjNAmOjHqQDEiiCUnaAQXu85XbyMY/vrghhLIszLomwGguXXgcju0basD5X4fZB6 Rw4kePdV5des3fp2uyQ1hqE6ghRotXq7H08aTLoqgECnsmTvyfTE8dL+d/3BJDfnRhEOEJmEvOt 40r2L+M1KK4iMsN6CxCn7RmGtPiaLjw+i63NgczBhaL/+fplDADcrK0W5ZfxPP6iQICtgntcX4w yeKbNgm7XMhp9uWMluoQI5GIMqNnl4sAPg7VqYRsRTRK1yC8+XpNk9Nrfmxnd3pHi7Qrj973Lmd EW7DQTS8z8TSAvvL7hqHCEXSGZpcx1VSN6twn7IC2nPMmFi78aOihzezy6Fi5v4eimjIF1+GGy9 729tYfM0oxI0RgQ== X-Developer-Key: i=towinchenmi@gmail.com; a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Add support for CPU PMU found in the Apple A9 and A9X SoCs. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 121 ++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 121 insertions(+) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 5739a85f3ae07c52f4ce91c4eda3e4bcdf91015d..0f59a22812a424ecd442e731a5c= 6b5be828be77c 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -289,6 +289,109 @@ static const u16 a8_pmu_event_affinity[A8_PMU_PERFCTR= _LAST + 1] =3D { [A8_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, }; =20 + +enum a9_pmu_events { + A9_PMU_PERFCTR_UNKNOWN_1 =3D 0x1, + A9_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, + A9_PMU_PERFCTR_L2_TLB_MISS_INSTRUCTION =3D 0xa, + A9_PMU_PERFCTR_L2_TLB_MISS_DATA =3D 0xb, + A9_PMU_PERFCTR_L2C_AGENT_LD =3D 0x1a, + A9_PMU_PERFCTR_L2C_AGENT_LD_MISS =3D 0x1b, + A9_PMU_PERFCTR_L2C_AGENT_ST =3D 0x1c, + A9_PMU_PERFCTR_L2C_AGENT_ST_MISS =3D 0x1d, + A9_PMU_PERFCTR_SCHEDULE_UOP =3D 0x52, + A9_PMU_PERFCTR_MAP_REWIND =3D 0x75, + A9_PMU_PERFCTR_MAP_STALL =3D 0x76, + A9_PMU_PERFCTR_MAP_INT_UOP =3D 0x7c, + A9_PMU_PERFCTR_MAP_LDST_UOP =3D 0x7d, + A9_PMU_PERFCTR_MAP_SIMD_UOP =3D 0x7e, + A9_PMU_PERFCTR_FLUSH_RESTART_OTHER_NONSPEC =3D 0x84, + A9_PMU_PERFCTR_INST_ALL =3D 0x8c, + A9_PMU_PERFCTR_INST_BRANCH =3D 0x8d, + A9_PMU_PERFCTR_INST_BRANCH_CALL =3D 0x8e, + A9_PMU_PERFCTR_INST_BRANCH_RET =3D 0x8f, + A9_PMU_PERFCTR_INST_BRANCH_TAKEN =3D 0x90, + A9_PMU_PERFCTR_INST_BRANCH_INDIR =3D 0x93, + A9_PMU_PERFCTR_INST_BRANCH_COND =3D 0x94, + A9_PMU_PERFCTR_INST_INT_LD =3D 0x95, + A9_PMU_PERFCTR_INST_INT_ST =3D 0x96, + A9_PMU_PERFCTR_INST_INT_ALU =3D 0x97, + A9_PMU_PERFCTR_INST_SIMD_LD =3D 0x98, + A9_PMU_PERFCTR_INST_SIMD_ST =3D 0x99, + A9_PMU_PERFCTR_INST_SIMD_ALU =3D 0x9a, + A9_PMU_PERFCTR_INST_LDST =3D 0x9b, + A9_PMU_PERFCTR_INST_BARRIER =3D 0x9c, + A9_PMU_PERFCTR_UNKNOWN_9f =3D 0x9f, + A9_PMU_PERFCTR_L1D_TLB_ACCESS =3D 0xa0, + A9_PMU_PERFCTR_L1D_TLB_MISS =3D 0xa1, + A9_PMU_PERFCTR_L1D_CACHE_MISS_ST =3D 0xa2, + A9_PMU_PERFCTR_L1D_CACHE_MISS_LD =3D 0xa3, + A9_PMU_PERFCTR_LD_UNIT_UOP =3D 0xa6, + A9_PMU_PERFCTR_ST_UNIT_UOP =3D 0xa7, + A9_PMU_PERFCTR_L1D_CACHE_WRITEBACK =3D 0xa8, + A9_PMU_PERFCTR_LDST_X64_UOP =3D 0xb1, + A9_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_SUCC =3D 0xb3, + A9_PMU_PERFCTR_ATOMIC_OR_EXCLUSIVE_FAIL =3D 0xb4, + A9_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC =3D 0xbf, + A9_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC =3D 0xc0, + A9_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC =3D 0xc1, + A9_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC =3D 0xc4, + A9_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC =3D 0xc5, + A9_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC =3D 0xc6, + A9_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC =3D 0xc8, + A9_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC =3D 0xca, + A9_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC =3D 0xcb, + A9_PMU_PERFCTR_FED_IC_MISS_DEMAND =3D 0xd3, + A9_PMU_PERFCTR_L1I_TLB_MISS_DEMAND =3D 0xd4, + A9_PMU_PERFCTR_MAP_DISPATCH_BUBBLE =3D 0xd6, + A9_PMU_PERFCTR_FETCH_RESTART =3D 0xde, + A9_PMU_PERFCTR_ST_NT_UOP =3D 0xe5, + A9_PMU_PERFCTR_LD_NT_UOP =3D 0xe6, + A9_PMU_PERFCTR_UNKNOWN_f6 =3D 0xf6, + A9_PMU_PERFCTR_UNKNOWN_f7 =3D 0xf7, + A9_PMU_PERFCTR_LAST =3D M1_PMU_CFG_EVENT, + + /* + * From this point onwards, these are not actual HW events, + * but attributes that get stored in hw->config_base. + */ + A9_PMU_CFG_COUNT_USER =3D BIT(8), + A9_PMU_CFG_COUNT_KERNEL =3D BIT(9), +}; + +static const u16 a9_pmu_event_affinity[A9_PMU_PERFCTR_LAST + 1] =3D { + [0 ... A9_PMU_PERFCTR_LAST] =3D ANY_BUT_0_1, + [A9_PMU_PERFCTR_UNKNOWN_1] =3D BIT(7), + [A9_PMU_PERFCTR_CORE_ACTIVE_CYCLE] =3D ANY_BUT_0_1 | BIT(0), + [A9_PMU_PERFCTR_INST_ALL] =3D BIT(7) | BIT(1), + [A9_PMU_PERFCTR_INST_BRANCH] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_CALL] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_RET] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_TAKEN] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_INDIR] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BRANCH_COND] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_LD] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_ST] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_INT_ALU] =3D BIT(7), + [A9_PMU_PERFCTR_INST_SIMD_LD] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_SIMD_ST] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_SIMD_ALU] =3D BIT(7), + [A9_PMU_PERFCTR_INST_LDST] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_INST_BARRIER] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_UNKNOWN_9f] =3D BIT(7), + [A9_PMU_PERFCTR_L1D_CACHE_MISS_LD_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_L1D_CACHE_MISS_ST_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_L1D_TLB_MISS_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_ST_MEMORY_ORDER_VIOLATION_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_COND_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_RET_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_CALL_INDIR_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_BRANCH_MISPRED_NONSPEC] =3D ONLY_5_6_7, + [A9_PMU_PERFCTR_UNKNOWN_f6] =3D ONLY_3_5_7, + [A9_PMU_PERFCTR_UNKNOWN_f7] =3D ONLY_3_5_7, +}; + enum m1_pmu_events { M1_PMU_PERFCTR_RETIRE_UOP =3D 0x1, M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE =3D 0x2, @@ -797,6 +900,12 @@ static int a8_pmu_get_event_idx(struct pmu_hw_events *= cpuc, return apple_pmu_get_event_idx(cpuc, event, a8_pmu_event_affinity); } =20 +static int a9_pmu_get_event_idx(struct pmu_hw_events *cpuc, + struct perf_event *event) +{ + return apple_pmu_get_event_idx(cpuc, event, a9_pmu_event_affinity); +} + static int m1_pmu_get_event_idx(struct pmu_hw_events *cpuc, struct perf_event *event) { @@ -986,6 +1095,17 @@ static int a8_pmu_typhoon_init(struct arm_pmu *cpu_pm= u) return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); } =20 +static int a9_pmu_twister_init(struct arm_pmu *cpu_pmu) +{ + cpu_pmu->name =3D "apple_twister_pmu"; + cpu_pmu->get_event_idx =3D a9_pmu_get_event_idx; + cpu_pmu->map_event =3D m1_pmu_map_event; + cpu_pmu->reset =3D a7_pmu_reset; + cpu_pmu->start =3D a7_pmu_start; + cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; + return apple_pmu_init(cpu_pmu, A7_PMU_NR_COUNTERS); +} + static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) { cpu_pmu->name =3D "apple_icestorm_pmu"; @@ -1035,6 +1155,7 @@ static const struct of_device_id m1_pmu_of_device_ids= [] =3D { { .compatible =3D "apple,blizzard-pmu", .data =3D m2_pmu_blizzard_init, }, { .compatible =3D "apple,icestorm-pmu", .data =3D m1_pmu_ice_init, }, { .compatible =3D "apple,firestorm-pmu", .data =3D m1_pmu_fire_init, }, + { .compatible =3D "apple,twister-pmu", .data =3D a9_pmu_twister_init, }, { .compatible =3D "apple,typhoon-pmu", .data =3D a8_pmu_typhoon_init, }, { .compatible =3D "apple,cyclone-pmu", .data =3D a7_pmu_cyclone_init, }, { }, --=20 2.49.0