From nobody Mon Feb 9 18:59:49 2026 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC87E2563; Sat, 5 Apr 2025 00:15:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743812135; cv=none; b=KCZAwiZc2KrdAlGMPGZpozKruA98UjQSRihdh1v6iYWwbvrdAXEYffDZjXzLQYCTN5oMusDpSTk5M/jWBvmlQRa9mpcykCyO9uLhL8DZSbXPLwoTNvGxZj+kUwlYc2APTJtt3JeDXO0f33YatrJQEsGFymgomPTcEihjUMDtGp8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743812135; c=relaxed/simple; bh=RA58xna5TnZMfeTU05n1vEVfCAtcv3caCmUSOinMX3o=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sGgL51ok7hGmYJ2baTQ+uHuYMvLhmiU+WIwU4QohnItyLAcH9zrSkLuxiOllXs0yUU1cjAPik+jW59nuBCLUzLOoykgPxrWjdKcCMfPHaTSlYqFA4AxT+pXr/B2chQUnU20qmo8kC4LFddheAVkkNgY70kproYGMSQlqjOBLSUw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=a8Tq3iDq; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="a8Tq3iDq" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 5350FJfI3922118 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 4 Apr 2025 19:15:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1743812119; bh=tG9+DniP+4kMZwsZQdG8VwGsMqG8IuNWjITKP0tXflI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=a8Tq3iDqY0dybTRUjI+f0ISJxP7/EDyGotuBqyNkom+8gnlzGrtM7JKUH4Hvk6CES vd6BhXapzCPJThOD5T2a/6L5n1u/+J1iNi94D/YqrFZVl7YaCRb12XUdm333VnQQq0 yhH4izgjZeHckawDACCqgz+SiDk78eomVZu/cYJY= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 5350FJCM021248 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 4 Apr 2025 19:15:19 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 4 Apr 2025 19:15:18 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 4 Apr 2025 19:15:18 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 5350FI5f065952; Fri, 4 Apr 2025 19:15:18 -0500 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Hari Nagalla , Beleswar Padhi , Andrew Davis , Markus Schneider-Pargmann Subject: [PATCH v6 06/11] arm64: dts: ti: k3-am62a7-sk: Enable IPC with remote processors Date: Fri, 4 Apr 2025 19:15:13 -0500 Message-ID: <20250405001518.1315273-7-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250405001518.1315273-1-jm@ti.com> References: <20250405001518.1315273-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Devarsh Thakkar For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 96 +++++++++++++++++++++++-- 1 file changed, 90 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index 1c9d95696c839..7d817b447c1d0 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -52,6 +52,42 @@ linux,cma { linux,cma-default; }; =20 + c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@99900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99900000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c900000 0x00 0xf00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg =3D <0x00 0x9e780000 0x00 0x80000>; alignment =3D <0x1000>; @@ -63,12 +99,6 @@ secure_ddr: optee@9e800000 { alignment =3D <0x1000>; no-map; }; - - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9c900000 0x00 0x01e00000>; - no-map; - }; }; =20 opp-table { @@ -741,3 +771,57 @@ dpi1_out: endpoint { }; }; }; + +&mailbox0_cluster0 { + status =3D "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + status =3D "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0>, <&mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&c7x_0 { + mboxes =3D <&mailbox0_cluster1>, <&mbox_c7x_0>; + memory-region =3D <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + status =3D "okay"; +}; --=20 2.49.0