From nobody Sun Feb 8 08:48:44 2026 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBC3A182BD; Sat, 5 Apr 2025 00:15:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743812134; cv=none; b=gwy58GeeFArltkqj/JRYXzb4URws3qTqFIXLjDJHXLzHerXHWG5R7EVJYluYuvYdjAqOJ8Siy0ZRn7y8qj4AMtk0HKAwmPnayBuFExT/RIQY3qZzUG13gQ8/5DPfGjPr5yV/Pa4gV5uWNiH3qFL7piFWudTLbJHxMJ2CFm/6UhE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743812134; c=relaxed/simple; bh=676EeJdGm3Q/CL3ppATqn5FS/L/FgHuEr+5zetRU4mU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aZPZVdi0LUUkGQdmkny0c6/XC1cxfTZRinI0z91GL7R4YEo2KZglyMU3jdGzFEMUjjsEalr4QcdVq74AiV0DJonBnDUbibvo0Zz/GqZEM0L2Qjh6NdhRx+KQgmkWi3+6Y8BSFWBvzQrFvMcWSDe/HwVbSeyT2MQlMnsTMYlqIh8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=YANhNrHV; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="YANhNrHV" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 5350FI7Y3922102 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 4 Apr 2025 19:15:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1743812118; bh=KfuHzB09gQzDVN1YPTwSbJ0e9xT70zByEt80tSecGcE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=YANhNrHVHj4DJUR7MXUR0rke7qm5LsA6BzZAjWKxPX7z6b6wh67URXubJBSNCsNkV aimEk9dMig4rUhaa5MmG/7BxgkVAfWoC5GJfFdkcgo4IaOQH1tHVznvUZHJ8LrXQcy uyabcLZXBbnIIMFEw3tWgYWdQfqcr7iHorHvPob4= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 5350FIdD038155 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 4 Apr 2025 19:15:18 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 4 Apr 2025 19:15:18 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 4 Apr 2025 19:15:18 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 5350FI5a065952; Fri, 4 Apr 2025 19:15:18 -0500 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Hari Nagalla , Beleswar Padhi , Andrew Davis , Markus Schneider-Pargmann Subject: [PATCH v6 01/11] arm64: dts: ti: k3-am62: Add ATCM and BTCM cbass ranges Date: Fri, 4 Apr 2025 19:15:08 -0500 Message-ID: <20250405001518.1315273-2-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250405001518.1315273-1-jm@ti.com> References: <20250405001518.1315273-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add cbass ranges for ATCM and BTCM on am62x device, without these, remoteproc driver fails to probe and attach to the DM r5 core and IPC communication is broken. Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am62.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k= 3-am62.dtsi index bfb55ca113239..59f6dff552ed4 100644 --- a/arch/arm64/boot/dts/ti/k3-am62.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi @@ -86,7 +86,9 @@ cbass_main: bus@f0000 { /* Wakeup Domain Range */ <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, - <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ =20 cbass_mcu: bus@4000000 { bootph-all; @@ -103,7 +105,9 @@ cbass_wakeup: bus@b00000 { #size-cells =3D <2>; ranges =3D <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Wind= ow */ - <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; + <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, + <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/ + <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/ }; }; =20 --=20 2.49.0 From nobody Sun Feb 8 08:48:44 2026 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 490C918027; Sat, 5 Apr 2025 00:15:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743812134; cv=none; b=q8WMc7Fm17bdy/wVi510E+dLe+feRyxZWKt6TdOfhaJFlIu9pKx5xjWqeDd9x3hcFmH5vLOYtXMo6a4lF8fxM6kjmHMWfdnqgJKrOHyn7n+hxr/NZVAdxazKKMYetp3f5WN537BOy4P0hSrXsDYAao1uuYWdUhF6oqjnQLDSn7M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743812134; c=relaxed/simple; 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Fri, 4 Apr 2025 19:15:18 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 5350FI5b065952; Fri, 4 Apr 2025 19:15:18 -0500 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Hari Nagalla , Beleswar Padhi , Andrew Davis , Markus Schneider-Pargmann Subject: [PATCH v6 02/11] arm64: dts: ti: k3-am62-wakeup: Add wakeup R5F node Date: Fri, 4 Apr 2025 19:15:09 -0500 Message-ID: <20250405001518.1315273-3-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250405001518.1315273-1-jm@ti.com> References: <20250405001518.1315273-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla AM62 SoC devices have a single core R5F processor in wakeup domain. The R5F processor in wakeup domain is used as a device manager for the SoC. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Acked-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/d= ts/ti/k3-am62-wakeup.dtsi index 9b8a1f85aa15c..6549b7efa6561 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -106,6 +106,31 @@ wkup_rti0: watchdog@2b000000 { status =3D "reserved"; }; =20 + wkup_r5fss0: r5fss@78000000 { + compatible =3D "ti,am62-r5fss"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x78000000 0x00 0x78000000 0x8000>, + <0x78100000 0x00 0x78100000 0x8000>; + power-domains =3D <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + wkup_r5fss0_core0: r5f@78000000 { + compatible =3D "ti,am62-r5f"; + reg =3D <0x78000000 0x00008000>, + <0x78100000 0x00008000>; + reg-names =3D "atcm", "btcm"; + resets =3D <&k3_reset 121 1>; + firmware-name =3D "am62-wkup-r5f0_0-fw"; + ti,atcm-enable =3D <1>; + ti,btcm-enable =3D <1>; + ti,loczrama =3D <1>; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <121>; + ti,sci-proc-ids =3D <0x01 0xff>; + }; + }; + wkup_vtm0: temperature-sensor@b00000 { compatible =3D "ti,j7200-vtm"; reg =3D <0x00 0xb00000 0x00 0x400>, --=20 2.49.0 From nobody Sun Feb 8 08:48:44 2026 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E322171A7; Sat, 5 Apr 2025 00:15:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743812133; cv=none; b=J/Z+FjSJtEzciQ2eR5U2OqkTcsBTIwPTNZaWhfpI5xQxC7kjYXVXUOLovKx+CeT5DS2UsO26AynZHxzoQenacFUfqY1dcSAUSFkAe2F8e5gSHFa9Phv0+6ub4WDKm7hZNdwGGHpDSViXCA+pJW9xLoV3p9uXO9laa3YolIhajX8= ARC-Message-Signature: i=1; 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Fri, 4 Apr 2025 19:15:18 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 5350FI5c065952; Fri, 4 Apr 2025 19:15:18 -0500 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Hari Nagalla , Beleswar Padhi , Andrew Davis , Markus Schneider-Pargmann Subject: [PATCH v6 03/11] arm64: dts: ti: k3-am62a-mcu: Add R5F remote proc node Date: Fri, 4 Apr 2025 19:15:10 -0500 Message-ID: <20250405001518.1315273-4-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250405001518.1315273-1-jm@ti.com> References: <20250405001518.1315273-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla AM62A SoCs have a single R5F core in the MCU voltage domain. Add the R5FSS node with the child node for core0 in MCU voltage domain .dtsi file. Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Acked-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts= /ti/k3-am62a-mcu.dtsi index 9ed9d703ff24d..ee961ced7208f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -174,4 +174,29 @@ mcu_mcan1: can@4e18000 { bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; status =3D "disabled"; }; + + mcu_r5fss0: r5fss@79000000 { + compatible =3D "ti,am62-r5fss"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x79000000 0x00 0x79000000 0x8000>, + <0x79020000 0x00 0x79020000 0x8000>; + power-domains =3D <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + mcu_r5fss0_core0: r5f@79000000 { + compatible =3D "ti,am62-r5f"; + reg =3D <0x79000000 0x00008000>, + <0x79020000 0x00008000>; + reg-names =3D "atcm", "btcm"; + resets =3D <&k3_reset 9 1>; + firmware-name =3D "am62a-mcu-r5f0_0-fw"; + ti,atcm-enable =3D <0>; + ti,btcm-enable =3D <1>; + ti,loczrama =3D <0>; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <9>; + ti,sci-proc-ids =3D <0x03 0xff>; + }; + }; }; --=20 2.49.0 From nobody Sun Feb 8 08:48:44 2026 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 994D742AA1; Sat, 5 Apr 2025 00:15:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743812137; cv=none; b=kWpqwfI9LfeUCP/XwVF9JPnDDxWdXgLfr/Do0Ng9/YsOiMzpRUe3UnJSB5Ocm3F27IOBXACxbeSTEJjzxeE7gcD5hrOLtQVBlOQJn4mtNK8L1vi7gERmHdpRYRyPM9mx6QCl5ONaWOtgOvYGPyfVuy8DNC98YqfO2Z2gR4d0828= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743812137; c=relaxed/simple; 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Fri, 4 Apr 2025 19:15:18 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 5350FI5d065952; Fri, 4 Apr 2025 19:15:18 -0500 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Hari Nagalla , Beleswar Padhi , Andrew Davis , Markus Schneider-Pargmann Subject: [PATCH v6 04/11] arm64: dts: ti: k3-am62a-wakeup: Add R5F device node Date: Fri, 4 Apr 2025 19:15:11 -0500 Message-ID: <20250405001518.1315273-5-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250405001518.1315273-1-jm@ti.com> References: <20250405001518.1315273-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Devarsh Thakkar AM62A SoCs have a single R5F core in wakeup domain. This core is also used as a device manager for the SoC. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Acked-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 25 +++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/= dts/ti/k3-am62a-wakeup.dtsi index b2c8f53517438..259ae6ebbfb5a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -103,6 +103,31 @@ wkup_rti0: watchdog@2b000000 { status =3D "reserved"; }; =20 + wkup_r5fss0: r5fss@78000000 { + compatible =3D "ti,am62-r5fss"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x78000000 0x00 0x78000000 0x8000>, + <0x78100000 0x00 0x78100000 0x8000>; + power-domains =3D <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + wkup_r5fss0_core0: r5f@78000000 { + compatible =3D "ti,am62-r5f"; + reg =3D <0x78000000 0x00008000>, + <0x78100000 0x00008000>; + reg-names =3D "atcm", "btcm"; + resets =3D <&k3_reset 121 1>; + firmware-name =3D "am62a-wkup-r5f0_0-fw"; + ti,atcm-enable =3D <1>; + ti,btcm-enable =3D <1>; + ti,loczrama =3D <1>; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <121>; + ti,sci-proc-ids =3D <0x01 0xff>; + }; + }; + wkup_vtm0: temperature-sensor@b00000 { compatible =3D "ti,j7200-vtm"; reg =3D <0x00 0xb00000 0x00 0x400>, --=20 2.49.0 From nobody Sun Feb 8 08:48:44 2026 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5E4E14AD3F; Sat, 5 Apr 2025 00:15:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743812139; cv=none; b=uxOSEMWIjI+A6kRfxtMIIgYGE5TBf0jwXGiEWco5o/HJ530S92Fd1CV99Dg7jTVfskPTRg+hmQoca5cueeJLtMzHjUFXFO71f9/7O6OtrTx2+BsrrTjlg4O0tmgA4tkAU0iSFofr2YkaB5aqgRZDumdVaGDufxDvlasrLeq06KA= ARC-Message-Signature: i=1; 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Fri, 4 Apr 2025 19:15:18 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 5350FI5e065952; Fri, 4 Apr 2025 19:15:18 -0500 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Hari Nagalla , Beleswar Padhi , Andrew Davis , Markus Schneider-Pargmann Subject: [PATCH v6 05/11] arm64: dts: ti: k3-am62a-main: Add C7xv device node Date: Fri, 4 Apr 2025 19:15:12 -0500 Message-ID: <20250405001518.1315273-6-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250405001518.1315273-1-jm@ti.com> References: <20250405001518.1315273-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Jai Luthra AM62A SoCs have a C7xv DSP subsystem with Analytics engine capability. This subsystem is intended for deep learning purposes. Define the device node for C7xv DSP. Signed-off-by: Jai Luthra Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Acked-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62a-main.dtsi index a1daba7b1fad5..d296e9e179738 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -1123,6 +1123,18 @@ vpu: video-codec@30210000 { power-domains =3D <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; }; =20 + c7x_0: dsp@7e000000 { + compatible =3D "ti,am62a-c7xv-dsp"; + reg =3D <0x00 0x7e000000 0x00 0x00100000>; + reg-names =3D "l2sram"; + resets =3D <&k3_reset 208 1>; + firmware-name =3D "am62a-c71_0-fw"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <208>; + ti,sci-proc-ids =3D <0x04 0xff>; + status =3D "disabled"; + }; + e5010: jpeg-encoder@fd20000 { compatible =3D "ti,am62a-jpeg-enc", "img,e5010-jpeg-enc"; reg =3D <0x00 0xfd20000 0x00 0x100>, --=20 2.49.0 From nobody Sun Feb 8 08:48:44 2026 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC87E2563; 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charset="utf-8" From: Devarsh Thakkar For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 96 +++++++++++++++++++++++-- 1 file changed, 90 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index 1c9d95696c839..7d817b447c1d0 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -52,6 +52,42 @@ linux,cma { linux,cma-default; }; =20 + c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@99900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99900000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c900000 0x00 0xf00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg =3D <0x00 0x9e780000 0x00 0x80000>; alignment =3D <0x1000>; @@ -63,12 +99,6 @@ secure_ddr: optee@9e800000 { alignment =3D <0x1000>; no-map; }; - - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9c900000 0x00 0x01e00000>; - no-map; - }; }; =20 opp-table { @@ -741,3 +771,57 @@ dpi1_out: endpoint { }; }; }; + +&mailbox0_cluster0 { + status =3D "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx =3D <0 0 0>; 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charset="utf-8" From: Devarsh Thakkar For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 50 ++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index d29f524600af0..05760507da4ed 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -49,6 +49,30 @@ reserved-memory { #size-cells =3D <2>; ranges; =20 + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000= { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c900000 0x00 0xf00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg =3D <0x00 0x9e780000 0x00 0x80000>; no-map; @@ -58,12 +82,6 @@ secure_ddr: optee@9e800000 { reg =3D <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ no-map; }; - - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9c900000 0x00 0x01e00000>; - no-map; - }; }; =20 vmain_pd: regulator-0 { @@ -640,6 +658,26 @@ mbox_mcu_r5_0: mbox-mcu-r5-0 { }; }; =20 +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + &main_uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart0_pins_default>; --=20 2.49.0 From nobody Sun Feb 8 08:48:44 2026 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2C2C43151; Sat, 5 Apr 2025 00:15:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743812137; cv=none; b=aaUmeyogOhjPHeGV81U0upWFJhBYnBlXlyNrluV0iV/8DB7nCaxjmvEUsR0uoHI4Cw5zGFle0m4Yh1uwV7TfN6bRpgdkTarrYsFhZpRfw4mlbTv1scFHtTp4xUso8XR33Z8lVxd3+68unYwbCBVa4m9zZiIs0Aa7VFlKSJmvZIk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743812137; c=relaxed/simple; bh=gxhvWVX3Zj86stirawTqBVBj3XfzXj9UoNgw5dseHGY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Fri, 4 Apr 2025 19:15:18 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 5350FI5h065952; Fri, 4 Apr 2025 19:15:18 -0500 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Hari Nagalla , Beleswar Padhi , Andrew Davis , Markus Schneider-Pargmann Subject: [PATCH v6 08/11] arm64: dts: ti: k3-am62x-sk-common: Enable IPC with remote processors Date: Fri, 4 Apr 2025 19:15:15 -0500 Message-ID: <20250405001518.1315273-9-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250405001518.1315273-1-jm@ti.com> References: <20250405001518.1315273-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 34 ++++++++++++++++--- 1 file changed, 29 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am62x-sk-common.dtsi index d52cb2a5a589a..364b2ba6af958 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -70,6 +70,18 @@ mcu_m4fss_memory_region: m4f-memory@9cc00000 { no-map; }; =20 + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9da00000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg =3D <0x00 0x9e780000 0x00 0x80000>; alignment =3D <0x1000>; @@ -82,11 +94,6 @@ secure_ddr: optee@9e800000 { no-map; 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charset="utf-8" From: Hari Nagalla C7x DSP uses main_timer2, so mark it as reserved in linux DT. Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index 7d817b447c1d0..8d7645bb90337 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -682,6 +682,11 @@ &main_uart1 { status =3D "reserved"; }; =20 +/* main_timer2 is used by C7x DSP */ +&main_timer2 { + status =3D "reserved"; +}; + &usbss0 { status =3D "okay"; ti,vbus-divider; --=20 2.49.0 From nobody Sun Feb 8 08:48:44 2026 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 025C62FB2; Sat, 5 Apr 2025 00:15:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743812135; cv=none; b=fBSzWho6tD1v8kC5V54r0FNxMPJl47pZo27vcRsFPFusAunTbxqC2t1MJ5TUlUOifWClha2FEApaW0pM0E9E8Mp2IgYqSO0Tmg3jcD8llk8mICvadJhiMjGxIWUfv0Z2FcR+R8ZiBprHtNNno4OSORscZek1n42Y5yxefo0+KIo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743812135; c=relaxed/simple; bh=uFR/fqFEyryfV8WtLTk6FtyGkz+FUGyA2syaYBYehAg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZIvPCQAOH1TB+ue5X80VuBl/+/Q4kpuZ/q1NCDuDx7Aj6kLWyr7avgMM+UEdJ5tPX2Bw4+Z8yev9I0eNRxLkKbcc6jLsiZEzzHzC41eJNB1e1V8B1QPLV8X27R9Gxm94NnxeXfZZS+JOMgsiNFg3mzYW0m1naEB8fxebrDrj4UU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Yn7lu6MB; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Yn7lu6MB" Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 5350FJC54072977 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 4 Apr 2025 19:15:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1743812119; bh=OTq4UdWHJFuAiM+oo3eenuRmPm/h270vOixLYg4RaqU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Yn7lu6MB1NQ0tJUs8fT8GatJUGtD1LVGJtDoU9YDQoTDiWRuCltM+4pajt9vTZpKx bGk8m/ZECY46EL7fnVy4O7fqodHRKc0zQDwmKlHIbXvT5UFsNa6wukhsJ/y5Ogc5mN c5IJSXl249i1Fg9okbZqbBapS9i90qaph0IzX1z0= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 5350FJU1038172 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 4 Apr 2025 19:15:19 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 4 Apr 2025 19:15:19 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 4 Apr 2025 19:15:18 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 5350FI5j065952; Fri, 4 Apr 2025 19:15:18 -0500 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Hari Nagalla , Beleswar Padhi , Andrew Davis , Markus Schneider-Pargmann Subject: [PATCH v6 10/11] arm64: dts: ti: k3-am62a7-sk: Reserve main_rti4 for C7x DSP Date: Fri, 4 Apr 2025 19:15:17 -0500 Message-ID: <20250405001518.1315273-11-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250405001518.1315273-1-jm@ti.com> References: <20250405001518.1315273-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla The main rti4 watchdog timer is used by the C7x DSP, so reserve the timer in the linux device tree. Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index 8d7645bb90337..032f1f18d184e 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -830,3 +830,8 @@ &c7x_0 { <&c7x_0_memory_region>; status =3D "okay"; }; + +/* main_rti4 is used by C7x DSP */ +&main_rti4 { + status =3D "reserved"; +}; --=20 2.49.0 From nobody Sun Feb 8 08:48:44 2026 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBED517A2E5; Sat, 5 Apr 2025 00:15:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743812141; cv=none; b=aB899e6wbjI08Z+tEq3QX07ixCSZuo6MNkwC+XHaQTYwXPPWs5jsEuAwIaxsAFGOud0NA54FKnEsF1Ts4FUexxln6JBClOXxwmkEVkEbl3Qo/k4PD+jcjUNthlIFGEw2OSX1C3Oaf1awcvJiamdcimjVNjUFAOlNQjUEa7jl5wA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743812141; c=relaxed/simple; bh=/gDqjyJoVjgQ+S4Kg1uFXudcEbZNcFups73llq8NASE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=eIhv5yOPgFIL4fABONvRBBngLG5WVqf4MRtw1oFgLrM+dufw9iuUZ6jGByQna5cibS1e6pKFZz7KgzNGPm4AtZM1zm6whq5IZo6BKT26xqG07ejXN7/+9sUat2k7actWoMPB9rtb7yhHQ5ODz7HxM5SDEvANGA4miNzyeuXWTZI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=xOAgztZe; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xOAgztZe" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 5350FJS8464798 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 4 Apr 2025 19:15:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1743812119; bh=+kbMmR2tIQt85OejEztUOpNk2QJKMnsU0zN6RrSPaRc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xOAgztZekWbAPxN6egfSA7+BCXEasNCMnAP0BknLn3wKS36bdLZI2gAhi7mMsh0o0 el2VX+ZeIHnhuZUJn6dPtX2fBpjsKMcGJCkirKSKdDDcGuB/3yBf5RVbFmBT3tDlEw 9Nm4BVwtjru49xoCt9sjM0FxjuCAniT2Ql/rRpKI= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 5350FJsV092676 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 4 Apr 2025 19:15:19 -0500 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 4 Apr 2025 19:15:19 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 4 Apr 2025 19:15:19 -0500 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 5350FI5k065952; Fri, 4 Apr 2025 19:15:19 -0500 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Hari Nagalla , Beleswar Padhi , Andrew Davis , Markus Schneider-Pargmann Subject: [PATCH v6 11/11] arm64: dts: ti: k3-am64: Reserve timers used by MCU FW Date: Fri, 4 Apr 2025 19:15:18 -0500 Message-ID: <20250405001518.1315273-12-jm@ti.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250405001518.1315273-1-jm@ti.com> References: <20250405001518.1315273-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla AM64x device has 4 R5F cores in the main domain. TI MCU firmware uses main domain timers as tick timers in these firmwares. Hence keep them as reserved in the Linux device tree. Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 17 +++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 17 +++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index f8ec40523254b..68bd6b806f8f0 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -796,6 +796,23 @@ &mcu_m4fss { status =3D "okay"; }; =20 +/* main_timers 8-11 are used by TI MCU FW */ +&main_timer8 { + status =3D "reserved"; +}; + +&main_timer9 { + status =3D "reserved"; +}; + +&main_timer10 { + status =3D "reserved"; +}; + +&main_timer11 { + status =3D "reserved"; +}; + &serdes_ln_ctrl { idle-states =3D ; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index 33e421ec18abb..07fbdf2400d23 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -710,6 +710,23 @@ &mcu_m4fss { status =3D "okay"; }; =20 +/* main_timers 8-11 are used by TI MCU FW */ +&main_timer8 { + status =3D "reserved"; +}; + +&main_timer9 { + status =3D "reserved"; +}; + +&main_timer10 { + status =3D "reserved"; +}; + +&main_timer11 { + status =3D "reserved"; +}; + &ecap0 { status =3D "okay"; /* PWM is available on Pin 1 of header J3 */ --=20 2.49.0