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Fixes: 411b44ba80ab ("svm: Implements update_pi_irte hook to setup posted i= nterrupt") Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 901d8d2dc169..a961e6e67050 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -820,7 +820,7 @@ static int svm_ir_list_add(struct vcpu_svm *svm, struct= amd_iommu_pi_data *pi) * Allocating new amd_iommu_pi_data, which will get * add to the per-vcpu ir_list. */ - ir =3D kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL_ACCOUNT); + ir =3D kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_ATOMIC | __GFP_ACCOUN= T); if (!ir) { ret =3D -ENOMEM; goto out; --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A7E521E096 for ; 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Fri, 04 Apr 2025 12:39:50 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:17 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-3-seanjc@google.com> Subject: [PATCH 02/67] KVM: x86: Reset IRTE to host control if *new* route isn't postable From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Restore an IRTE back to host control (remapped or posted MSI mode) if the *new* GSI route prevents posting the IRQ directly to a vCPU, regardless of the GSI routing type. Updating the IRTE if and only if the new GSI is an MSI results in KVM leaving an IRTE posting to a vCPU. The dangling IRTE can result in interrupts being incorrectly delivered to the guest, and in the worst case scenario can result in use-after-free, e.g. if the VM is torn down, but the underlying host IRQ isn't freed. Fixes: efc644048ecd ("KVM: x86: Update IRTE for posted-interrupts") Fixes: 411b44ba80ab ("svm: Implements update_pi_irte hook to setup posted i= nterrupt") Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 61 ++++++++++++++++++---------------- arch/x86/kvm/vmx/posted_intr.c | 28 ++++++---------- 2 files changed, 43 insertions(+), 46 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index a961e6e67050..ef08356fdb1c 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -896,6 +896,7 @@ int avic_pi_update_irte(struct kvm *kvm, unsigned int h= ost_irq, { struct kvm_kernel_irq_routing_entry *e; struct kvm_irq_routing_table *irq_rt; + bool enable_remapped_mode =3D true; int idx, ret =3D 0; =20 if (!kvm_arch_has_assigned_device(kvm) || !kvm_arch_has_irq_bypass()) @@ -932,6 +933,8 @@ int avic_pi_update_irte(struct kvm *kvm, unsigned int h= ost_irq, kvm_vcpu_apicv_active(&svm->vcpu)) { struct amd_iommu_pi_data pi; =20 + enable_remapped_mode =3D false; + /* Try to enable guest_mode in IRTE */ pi.base =3D __sme_set(page_to_phys(svm->avic_backing_page) & AVIC_HPA_MASK); @@ -950,33 +953,6 @@ int avic_pi_update_irte(struct kvm *kvm, unsigned int = host_irq, */ if (!ret && pi.is_guest_mode) svm_ir_list_add(svm, &pi); - } else { - /* Use legacy mode in IRTE */ - struct amd_iommu_pi_data pi; - - /** - * Here, pi is used to: - * - Tell IOMMU to use legacy mode for this interrupt. - * - Retrieve ga_tag of prior interrupt remapping data. - */ - pi.prev_ga_tag =3D 0; - pi.is_guest_mode =3D false; - ret =3D irq_set_vcpu_affinity(host_irq, &pi); - - /** - * Check if the posted interrupt was previously - * setup with the guest_mode by checking if the ga_tag - * was cached. If so, we need to clean up the per-vcpu - * ir_list. - */ - if (!ret && pi.prev_ga_tag) { - int id =3D AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag); - struct kvm_vcpu *vcpu; - - vcpu =3D kvm_get_vcpu_by_id(kvm, id); - if (vcpu) - svm_ir_list_del(to_svm(vcpu), &pi); - } } =20 if (!ret && svm) { @@ -991,7 +967,36 @@ int avic_pi_update_irte(struct kvm *kvm, unsigned int = host_irq, } } =20 - ret =3D 0; + if (enable_remapped_mode) { + /* Use legacy mode in IRTE */ + struct amd_iommu_pi_data pi; + + /** + * Here, pi is used to: + * - Tell IOMMU to use legacy mode for this interrupt. + * - Retrieve ga_tag of prior interrupt remapping data. + */ + pi.prev_ga_tag =3D 0; + pi.is_guest_mode =3D false; + ret =3D irq_set_vcpu_affinity(host_irq, &pi); + + /** + * Check if the posted interrupt was previously + * setup with the guest_mode by checking if the ga_tag + * was cached. If so, we need to clean up the per-vcpu + * ir_list. + */ + if (!ret && pi.prev_ga_tag) { + int id =3D AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag); + struct kvm_vcpu *vcpu; + + vcpu =3D kvm_get_vcpu_by_id(kvm, id); + if (vcpu) + svm_ir_list_del(to_svm(vcpu), &pi); + } + } else { + ret =3D 0; + } out: srcu_read_unlock(&kvm->irq_srcu, idx); return ret; diff --git a/arch/x86/kvm/vmx/posted_intr.c b/arch/x86/kvm/vmx/posted_intr.c index 16121d29dfd9..78ba3d638fe8 100644 --- a/arch/x86/kvm/vmx/posted_intr.c +++ b/arch/x86/kvm/vmx/posted_intr.c @@ -273,6 +273,7 @@ int vmx_pi_update_irte(struct kvm *kvm, unsigned int ho= st_irq, { struct kvm_kernel_irq_routing_entry *e; struct kvm_irq_routing_table *irq_rt; + bool enable_remapped_mode =3D true; struct kvm_lapic_irq irq; struct kvm_vcpu *vcpu; struct vcpu_data vcpu_info; @@ -311,21 +312,8 @@ int vmx_pi_update_irte(struct kvm *kvm, unsigned int h= ost_irq, =20 kvm_set_msi_irq(kvm, e, &irq); if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || - !kvm_irq_is_postable(&irq)) { - /* - * Make sure the IRTE is in remapped mode if - * we don't handle it in posted mode. - */ - ret =3D irq_set_vcpu_affinity(host_irq, NULL); - if (ret < 0) { - printk(KERN_INFO - "failed to back to remapped mode, irq: %u\n", - host_irq); - goto out; - } - + !kvm_irq_is_postable(&irq)) continue; - } =20 vcpu_info.pi_desc_addr =3D __pa(vcpu_to_pi_desc(vcpu)); vcpu_info.vector =3D irq.vector; @@ -333,11 +321,12 @@ int vmx_pi_update_irte(struct kvm *kvm, unsigned int = host_irq, trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi, vcpu_info.vector, vcpu_info.pi_desc_addr, set); =20 - if (set) - ret =3D irq_set_vcpu_affinity(host_irq, &vcpu_info); - else - ret =3D irq_set_vcpu_affinity(host_irq, NULL); + if (!set) + continue; =20 + enable_remapped_mode =3D false; + + ret =3D irq_set_vcpu_affinity(host_irq, &vcpu_info); if (ret < 0) { printk(KERN_INFO "%s: failed to update PI IRTE\n", __func__); @@ -345,6 +334,9 @@ int vmx_pi_update_irte(struct kvm *kvm, unsigned int ho= st_irq, } } =20 + if (enable_remapped_mode) + ret =3D irq_set_vcpu_affinity(host_irq, NULL); + ret =3D 0; out: srcu_read_unlock(&kvm->irq_srcu, idx); --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF172221540 for ; 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Fri, 04 Apr 2025 12:39:52 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:18 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-4-seanjc@google.com> Subject: [PATCH 03/67] KVM: x86: Explicitly treat routing entry type changes as changes From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Explicitly treat type differences as GSI routing changes, as comparing MSI data between two entries could get a false negative, e.g. if userspace changed the type but left the type-specific data as-is. Fixes: 515a0c79e796 ("kvm: irqfd: avoid update unmodified entries of the ro= uting") Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/x86.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 9211344b20ae..f94f1217a087 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -13615,7 +13615,8 @@ int kvm_arch_update_irqfd_routing(struct kvm *kvm, = unsigned int host_irq, bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old, struct kvm_kernel_irq_routing_entry *new) { - if (new->type !=3D KVM_IRQ_ROUTING_MSI) + if (old->type !=3D KVM_IRQ_ROUTING_MSI || + new->type !=3D KVM_IRQ_ROUTING_MSI) return true; =20 return !!memcmp(&old->msi, &new->msi, sizeof(new->msi)); --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD21B221544 for ; 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Fri, 04 Apr 2025 12:39:54 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:19 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-5-seanjc@google.com> Subject: [PATCH 04/67] KVM: x86: Take irqfds.lock when adding/deleting IRQ bypass producer From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Take irqfds.lock when adding/deleting an IRQ bypass producer to ensure irqfd->producer isn't modified while kvm_irq_routing_update() is running. The only lock held when a producer is added/removed is irqbypass's mutex. Fixes: 872768800652 ("KVM: x86: select IRQ_BYPASS_MANAGER") Cc: stable@vger.kernel.org Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/x86.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index f94f1217a087..dcc173852dc5 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -13569,15 +13569,22 @@ int kvm_arch_irq_bypass_add_producer(struct irq_b= ypass_consumer *cons, { struct kvm_kernel_irqfd *irqfd =3D container_of(cons, struct kvm_kernel_irqfd, consumer); + struct kvm *kvm =3D irqfd->kvm; int ret; =20 - irqfd->producer =3D prod; kvm_arch_start_assignment(irqfd->kvm); + + spin_lock_irq(&kvm->irqfds.lock); + irqfd->producer =3D prod; + ret =3D kvm_x86_call(pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 1); if (ret) kvm_arch_end_assignment(irqfd->kvm); =20 + spin_unlock_irq(&kvm->irqfds.lock); + + return ret; } =20 @@ -13587,9 +13594,9 @@ void kvm_arch_irq_bypass_del_producer(struct irq_by= pass_consumer *cons, int ret; struct kvm_kernel_irqfd *irqfd =3D container_of(cons, struct kvm_kernel_irqfd, consumer); + struct kvm *kvm =3D irqfd->kvm; =20 WARN_ON(irqfd->producer !=3D prod); - irqfd->producer =3D NULL; =20 /* * When producer of consumer is unregistered, we change back to @@ -13597,12 +13604,18 @@ void kvm_arch_irq_bypass_del_producer(struct irq_= bypass_consumer *cons, * when the irq is masked/disabled or the consumer side (KVM * int this case doesn't want to receive the interrupts. */ + spin_lock_irq(&kvm->irqfds.lock); + irqfd->producer =3D NULL; + ret =3D kvm_x86_call(pi_update_irte)(irqfd->kvm, prod->irq, irqfd->gsi, 0); if (ret) printk(KERN_INFO "irq bypass consumer (token %p) unregistration" " fails: %d\n", irqfd->consumer.token, ret); =20 + spin_unlock_irq(&kvm->irqfds.lock); + + kvm_arch_end_assignment(irqfd->kvm); } =20 --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5030D22173E for ; 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Fri, 04 Apr 2025 12:39:55 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:20 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-6-seanjc@google.com> Subject: [PATCH 05/67] iommu/amd: Return an error if vCPU affinity is set for non-vCPU IRTE From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Return -EINVAL instead of success if amd_ir_set_vcpu_affinity() is invoked without use_vapic; lying to KVM about whether or not the IRTE was configured to post IRQs is all kinds of bad. Fixes: d98de49a53e4 ("iommu/amd: Enable vAPIC interrupt remapping mode by d= efault") Signed-off-by: Sean Christopherson Reviewed-by: Vasant Hegde Tested-by: Sairaj Kodilkar --- drivers/iommu/amd/iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index cd5116d8c3b2..b3a01b7757ee 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3850,7 +3850,7 @@ static int amd_ir_set_vcpu_affinity(struct irq_data *= data, void *vcpu_info) * we should not modify the IRTE */ if (!dev_data || !dev_data->use_vapic) - return 0; + return -EINVAL; =20 ir_data->cfg =3D irqd_cfg(data); pi_data->ir_data =3D ir_data; --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13030221F02 for ; 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Fri, 04 Apr 2025 12:39:57 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:21 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-7-seanjc@google.com> Subject: [PATCH 06/67] iommu/amd: WARN if KVM attempts to set vCPU affinity without posted intrrupts From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" WARN if KVM attempts to set vCPU affinity when posted interrupts aren't enabled, as KVM shouldn't try to enable posting when they're unsupported, and the IOMMU driver darn well should only advertise posting support when AMD_IOMMU_GUEST_IR_VAPIC() is true. Note, KVM consumes is_guest_mode only on success. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- drivers/iommu/amd/iommu.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index b3a01b7757ee..4f69a37cf143 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3852,19 +3852,12 @@ static int amd_ir_set_vcpu_affinity(struct irq_data= *data, void *vcpu_info) if (!dev_data || !dev_data->use_vapic) return -EINVAL; =20 + if (WARN_ON_ONCE(!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))) + return -EINVAL; + ir_data->cfg =3D irqd_cfg(data); pi_data->ir_data =3D ir_data; =20 - /* Note: - * SVM tries to set up for VAPIC mode, but we are in - * legacy mode. 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charset="utf-8" Now that the AMD IOMMU doesn't signal success incorrectly, WARN if KVM attempts to track an AMD IRTE entry without metadata. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index ef08356fdb1c..1708ea55125a 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -796,12 +796,15 @@ static int svm_ir_list_add(struct vcpu_svm *svm, stru= ct amd_iommu_pi_data *pi) struct amd_svm_iommu_ir *ir; u64 entry; =20 + if (WARN_ON_ONCE(!pi->ir_data)) + return -EINVAL; + /** * In some cases, the existing irte is updated and re-set, * so we need to check here if it's already been * added * to the ir_list. */ - if (pi->ir_data && (pi->prev_ga_tag !=3D 0)) { + if (pi->prev_ga_tag) { struct kvm *kvm =3D svm->vcpu.kvm; u32 vcpu_id =3D AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag); struct kvm_vcpu *prev_vcpu =3D kvm_get_vcpu_by_id(kvm, vcpu_id); --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66D7C2222CE for ; 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Fri, 04 Apr 2025 12:40:00 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:23 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-9-seanjc@google.com> Subject: [PATCH 08/67] KVM: x86: Pass new routing entries and irqfd when updating IRTEs From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When updating IRTEs in response to a GSI routing or IRQ bypass change, pass the new/current routing information along with the associated irqfd. This will allow KVM x86 to harden, simplify, and deduplicate its code. Since adding/removing a bypass producer is now conveniently protected with irqfds.lock, i.e. can't run concurrently with kvm_irq_routing_update(), use the routing information cached in the irqfd instead of looking up the information in the current GSI routing tables. Opportunistically convert an existing printk() to pr_info() and put its string onto a single line (old code that strictly adhered to 80 chars). Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/include/asm/kvm_host.h | 6 ++++-- arch/x86/kvm/svm/avic.c | 18 +++++++---------- arch/x86/kvm/svm/svm.h | 5 +++-- arch/x86/kvm/vmx/posted_intr.c | 19 ++++++++--------- arch/x86/kvm/vmx/posted_intr.h | 8 ++++++-- arch/x86/kvm/x86.c | 36 ++++++++++++++++++--------------- include/linux/kvm_host.h | 7 +++++-- virt/kvm/eventfd.c | 11 +++++----- 8 files changed, 58 insertions(+), 52 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 6e8be274c089..54f3cf73329b 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -294,6 +294,7 @@ enum x86_intercept_stage; */ #define KVM_APIC_PV_EOI_PENDING 1 =20 +struct kvm_kernel_irqfd; struct kvm_kernel_irq_routing_entry; =20 /* @@ -1828,8 +1829,9 @@ struct kvm_x86_ops { void (*vcpu_blocking)(struct kvm_vcpu *vcpu); void (*vcpu_unblocking)(struct kvm_vcpu *vcpu); =20 - int (*pi_update_irte)(struct kvm *kvm, unsigned int host_irq, - uint32_t guest_irq, bool set); + int (*pi_update_irte)(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, + unsigned int host_irq, uint32_t guest_irq, + struct kvm_kernel_irq_routing_entry *new); void (*pi_start_assignment)(struct kvm *kvm); void (*apicv_pre_state_restore)(struct kvm_vcpu *vcpu); void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 1708ea55125a..04dfd898ea8d 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -18,6 +18,7 @@ #include #include #include +#include =20 #include =20 @@ -885,21 +886,14 @@ get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_i= rq_routing_entry *e, return 0; } =20 -/* - * avic_pi_update_irte - set IRTE for Posted-Interrupts - * - * @kvm: kvm - * @host_irq: host irq of the interrupt - * @guest_irq: gsi of the interrupt - * @set: set or unset PI - * returns 0 on success, < 0 on failure - */ -int avic_pi_update_irte(struct kvm *kvm, unsigned int host_irq, - uint32_t guest_irq, bool set) +int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, + unsigned int host_irq, uint32_t guest_irq, + struct kvm_kernel_irq_routing_entry *new) { struct kvm_kernel_irq_routing_entry *e; struct kvm_irq_routing_table *irq_rt; bool enable_remapped_mode =3D true; + bool set =3D !!new; int idx, ret =3D 0; =20 if (!kvm_arch_has_assigned_device(kvm) || !kvm_arch_has_irq_bypass()) @@ -925,6 +919,8 @@ int avic_pi_update_irte(struct kvm *kvm, unsigned int h= ost_irq, if (e->type !=3D KVM_IRQ_ROUTING_MSI) continue; =20 + WARN_ON_ONCE(new && memcmp(e, new, sizeof(*new))); + /** * Here, we setup with legacy mode in the following cases: * 1. When cannot target interrupt to a specific vcpu. diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index d4490eaed55d..294d5594c724 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -731,8 +731,9 @@ void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu); void avic_vcpu_put(struct kvm_vcpu *vcpu); void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu); void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu); -int avic_pi_update_irte(struct kvm *kvm, unsigned int host_irq, - uint32_t guest_irq, bool set); +int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, + unsigned int host_irq, uint32_t guest_irq, + struct kvm_kernel_irq_routing_entry *new); void avic_vcpu_blocking(struct kvm_vcpu *vcpu); void avic_vcpu_unblocking(struct kvm_vcpu *vcpu); void avic_ring_doorbell(struct kvm_vcpu *vcpu); diff --git a/arch/x86/kvm/vmx/posted_intr.c b/arch/x86/kvm/vmx/posted_intr.c index 78ba3d638fe8..1b6b655a2b8a 100644 --- a/arch/x86/kvm/vmx/posted_intr.c +++ b/arch/x86/kvm/vmx/posted_intr.c @@ -2,6 +2,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt =20 #include +#include =20 #include #include @@ -259,17 +260,9 @@ void vmx_pi_start_assignment(struct kvm *kvm) kvm_make_all_cpus_request(kvm, KVM_REQ_UNBLOCK); } =20 -/* - * vmx_pi_update_irte - set IRTE for Posted-Interrupts - * - * @kvm: kvm - * @host_irq: host irq of the interrupt - * @guest_irq: gsi of the interrupt - * @set: set or unset PI - * returns 0 on success, < 0 on failure - */ -int vmx_pi_update_irte(struct kvm *kvm, unsigned int host_irq, - uint32_t guest_irq, bool set) +int vmx_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, + unsigned int host_irq, uint32_t guest_irq, + struct kvm_kernel_irq_routing_entry *new) { struct kvm_kernel_irq_routing_entry *e; struct kvm_irq_routing_table *irq_rt; @@ -277,6 +270,7 @@ int vmx_pi_update_irte(struct kvm *kvm, unsigned int ho= st_irq, struct kvm_lapic_irq irq; struct kvm_vcpu *vcpu; struct vcpu_data vcpu_info; + bool set =3D !!new; int idx, ret =3D 0; =20 if (!vmx_can_use_vtd_pi(kvm)) @@ -294,6 +288,9 @@ int vmx_pi_update_irte(struct kvm *kvm, unsigned int ho= st_irq, hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { if (e->type !=3D KVM_IRQ_ROUTING_MSI) continue; + + WARN_ON_ONCE(new && memcmp(e, new, sizeof(*new))); + /* * VT-d PI cannot support posting multicast/broadcast * interrupts to a vCPU, we still use interrupt remapping diff --git a/arch/x86/kvm/vmx/posted_intr.h b/arch/x86/kvm/vmx/posted_intr.h index ad9116a99bcc..a586d6aaf862 100644 --- a/arch/x86/kvm/vmx/posted_intr.h +++ b/arch/x86/kvm/vmx/posted_intr.h @@ -3,6 +3,9 @@ #define __KVM_X86_VMX_POSTED_INTR_H =20 #include +#include +#include + #include =20 void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu); @@ -10,8 +13,9 @@ void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu); void pi_wakeup_handler(void); void __init pi_init_cpu(int cpu); bool pi_has_pending_interrupt(struct kvm_vcpu *vcpu); -int vmx_pi_update_irte(struct kvm *kvm, unsigned int host_irq, - uint32_t guest_irq, bool set); +int vmx_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, + unsigned int host_irq, uint32_t guest_irq, + struct kvm_kernel_irq_routing_entry *new); void vmx_pi_start_assignment(struct kvm *kvm); =20 static inline int pi_find_highest_vector(struct pi_desc *pi_desc) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index dcc173852dc5..23376fcd928c 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -13570,31 +13570,31 @@ int kvm_arch_irq_bypass_add_producer(struct irq_b= ypass_consumer *cons, struct kvm_kernel_irqfd *irqfd =3D container_of(cons, struct kvm_kernel_irqfd, consumer); struct kvm *kvm =3D irqfd->kvm; - int ret; + int ret =3D 0; =20 kvm_arch_start_assignment(irqfd->kvm); =20 spin_lock_irq(&kvm->irqfds.lock); irqfd->producer =3D prod; =20 - ret =3D kvm_x86_call(pi_update_irte)(irqfd->kvm, - prod->irq, irqfd->gsi, 1); - if (ret) - kvm_arch_end_assignment(irqfd->kvm); - + if (irqfd->irq_entry.type =3D=3D KVM_IRQ_ROUTING_MSI) { + ret =3D kvm_x86_call(pi_update_irte)(irqfd, irqfd->kvm, prod->irq, + irqfd->gsi, &irqfd->irq_entry); + if (ret) + kvm_arch_end_assignment(irqfd->kvm); + } spin_unlock_irq(&kvm->irqfds.lock); =20 - return ret; } =20 void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons, struct irq_bypass_producer *prod) { - int ret; struct kvm_kernel_irqfd *irqfd =3D container_of(cons, struct kvm_kernel_irqfd, consumer); struct kvm *kvm =3D irqfd->kvm; + int ret; =20 WARN_ON(irqfd->producer !=3D prod); =20 @@ -13607,11 +13607,13 @@ void kvm_arch_irq_bypass_del_producer(struct irq_= bypass_consumer *cons, spin_lock_irq(&kvm->irqfds.lock); irqfd->producer =3D NULL; =20 - ret =3D kvm_x86_call(pi_update_irte)(irqfd->kvm, - prod->irq, irqfd->gsi, 0); - if (ret) - printk(KERN_INFO "irq bypass consumer (token %p) unregistration" - " fails: %d\n", irqfd->consumer.token, ret); + if (irqfd->irq_entry.type =3D=3D KVM_IRQ_ROUTING_MSI) { + ret =3D kvm_x86_call(pi_update_irte)(irqfd, irqfd->kvm, prod->irq, + irqfd->gsi, NULL); + if (ret) + pr_info("irq bypass consumer (token %p) unregistration fails: %d\n", + irqfd->consumer.token, ret); + } =20 spin_unlock_irq(&kvm->irqfds.lock); =20 @@ -13619,10 +13621,12 @@ void kvm_arch_irq_bypass_del_producer(struct irq_= bypass_consumer *cons, kvm_arch_end_assignment(irqfd->kvm); } =20 -int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, - uint32_t guest_irq, bool set) +int kvm_arch_update_irqfd_routing(struct kvm_kernel_irqfd *irqfd, + struct kvm_kernel_irq_routing_entry *old, + struct kvm_kernel_irq_routing_entry *new) { - return kvm_x86_call(pi_update_irte)(kvm, host_irq, guest_irq, set); + return kvm_x86_call(pi_update_irte)(irqfd, irqfd->kvm, irqfd->producer->i= rq, + irqfd->gsi, new); } =20 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old, diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index 5438a1b446a6..2d9f3aeb766a 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -2383,6 +2383,8 @@ struct kvm_vcpu *kvm_get_running_vcpu(void); struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void); =20 #ifdef CONFIG_HAVE_KVM_IRQ_BYPASS +struct kvm_kernel_irqfd; + bool kvm_arch_has_irq_bypass(void); int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *, struct irq_bypass_producer *); @@ -2390,8 +2392,9 @@ void kvm_arch_irq_bypass_del_producer(struct irq_bypa= ss_consumer *, struct irq_bypass_producer *); void kvm_arch_irq_bypass_stop(struct irq_bypass_consumer *); void kvm_arch_irq_bypass_start(struct irq_bypass_consumer *); -int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq, - uint32_t guest_irq, bool set); +int kvm_arch_update_irqfd_routing(struct kvm_kernel_irqfd *irqfd, + struct kvm_kernel_irq_routing_entry *old, + struct kvm_kernel_irq_routing_entry *new); bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *, struct kvm_kernel_irq_routing_entry *); #endif /* CONFIG_HAVE_KVM_IRQ_BYPASS */ diff --git a/virt/kvm/eventfd.c b/virt/kvm/eventfd.c index 249ba5b72e9b..ad71e3e4d1c3 100644 --- a/virt/kvm/eventfd.c +++ b/virt/kvm/eventfd.c @@ -285,9 +285,9 @@ void __attribute__((weak)) kvm_arch_irq_bypass_start( { } =20 -int __attribute__((weak)) kvm_arch_update_irqfd_routing( - struct kvm *kvm, unsigned int host_irq, - uint32_t guest_irq, bool set) +int __weak kvm_arch_update_irqfd_routing(struct kvm_kernel_irqfd *irqfd, + struct kvm_kernel_irq_routing_entry *old, + struct kvm_kernel_irq_routing_entry *new) { return 0; } @@ -619,9 +619,8 @@ void kvm_irq_routing_update(struct kvm *kvm) #ifdef CONFIG_HAVE_KVM_IRQ_BYPASS if (irqfd->producer && kvm_arch_irqfd_route_changed(&old, &irqfd->irq_entry)) { - int ret =3D kvm_arch_update_irqfd_routing( - irqfd->kvm, irqfd->producer->irq, - irqfd->gsi, 1); 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charset="utf-8" Track the IRTEs that are posting to an SVM vCPU via the associated irqfd structure and GSI routing instead of dynamically allocating a separate data structure. In addition to eliminating an atomic allocation, this will allow hoisting much of the IRTE update logic to common x86. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 49 ++++++++++++++++----------------------- include/linux/kvm_irqfd.h | 3 +++ 2 files changed, 23 insertions(+), 29 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 04dfd898ea8d..967618ba743a 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -774,27 +774,30 @@ static int avic_set_pi_irte_mode(struct kvm_vcpu *vcp= u, bool activate) return ret; } =20 -static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data= *pi) +static void svm_ir_list_del(struct vcpu_svm *svm, + struct kvm_kernel_irqfd *irqfd, + struct amd_iommu_pi_data *pi) { unsigned long flags; - struct amd_svm_iommu_ir *cur; + struct kvm_kernel_irqfd *cur; =20 spin_lock_irqsave(&svm->ir_list_lock, flags); - list_for_each_entry(cur, &svm->ir_list, node) { - if (cur->data !=3D pi->ir_data) + list_for_each_entry(cur, &svm->ir_list, vcpu_list) { + if (cur->irq_bypass_data !=3D pi->ir_data) continue; - list_del(&cur->node); - kfree(cur); + if (WARN_ON_ONCE(cur !=3D irqfd)) + continue; + list_del(&irqfd->vcpu_list); break; } spin_unlock_irqrestore(&svm->ir_list_lock, flags); } =20 -static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data = *pi) +static int svm_ir_list_add(struct vcpu_svm *svm, + struct kvm_kernel_irqfd *irqfd, + struct amd_iommu_pi_data *pi) { - int ret =3D 0; unsigned long flags; - struct amd_svm_iommu_ir *ir; u64 entry; =20 if (WARN_ON_ONCE(!pi->ir_data)) @@ -811,25 +814,14 @@ static int svm_ir_list_add(struct vcpu_svm *svm, stru= ct amd_iommu_pi_data *pi) struct kvm_vcpu *prev_vcpu =3D kvm_get_vcpu_by_id(kvm, vcpu_id); struct vcpu_svm *prev_svm; =20 - if (!prev_vcpu) { - ret =3D -EINVAL; - goto out; - } + if (!prev_vcpu) + return -EINVAL; =20 prev_svm =3D to_svm(prev_vcpu); - svm_ir_list_del(prev_svm, pi); + svm_ir_list_del(prev_svm, irqfd, pi); } =20 - /** - * Allocating new amd_iommu_pi_data, which will get - * add to the per-vcpu ir_list. - */ - ir =3D kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_ATOMIC | __GFP_ACCOUN= T); - if (!ir) { - ret =3D -ENOMEM; - goto out; - } - ir->data =3D pi->ir_data; + irqfd->irq_bypass_data =3D pi->ir_data; =20 spin_lock_irqsave(&svm->ir_list_lock, flags); =20 @@ -844,10 +836,9 @@ static int svm_ir_list_add(struct vcpu_svm *svm, struc= t amd_iommu_pi_data *pi) amd_iommu_update_ga(entry & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK, true, pi->ir_data); =20 - list_add(&ir->node, &svm->ir_list); + list_add(&irqfd->vcpu_list, &svm->ir_list); spin_unlock_irqrestore(&svm->ir_list_lock, flags); -out: - return ret; + return 0; } =20 /* @@ -951,7 +942,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, * scheduling information in IOMMU irte. */ if (!ret && pi.is_guest_mode) - svm_ir_list_add(svm, &pi); + svm_ir_list_add(svm, irqfd, &pi); } =20 if (!ret && svm) { @@ -991,7 +982,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, =20 vcpu =3D kvm_get_vcpu_by_id(kvm, id); if (vcpu) - svm_ir_list_del(to_svm(vcpu), &pi); + svm_ir_list_del(to_svm(vcpu), irqfd, &pi); } } else { ret =3D 0; diff --git a/include/linux/kvm_irqfd.h b/include/linux/kvm_irqfd.h index 8ad43692e3bb..6510a48e62aa 100644 --- a/include/linux/kvm_irqfd.h +++ b/include/linux/kvm_irqfd.h @@ -59,6 +59,9 @@ struct kvm_kernel_irqfd { struct work_struct shutdown; struct irq_bypass_consumer consumer; struct irq_bypass_producer *producer; + + struct list_head vcpu_list; + void *irq_bypass_data; }; =20 #endif /* __LINUX_KVM_IRQFD_H */ --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0D5622259C for ; Fri, 4 Apr 2025 19:40:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743795606; cv=none; b=fIDhLN1Ci+IM/ILbGg5hXxIDb51A5vDs2iCgvJUNsx3kgn4C05WAZpmbV8Ijp4w9epyExtJzAqLv0rLrEt1DT9KzlhyhaHnYtXfkfdsfh3/VOA23JEc9NlIrY5Vmo58BEbOwM/cdtycsdTamwgl/JjzzvebIRZYIBBz15yQ76bY= ARC-Message-Signature: i=1; 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charset="utf-8" Delete the previous per-vCPU IRTE link prior to modifying the IRTE. If forcing the IRTE back to remapped mode fails, the IRQ is already broken; keeping stale metadata won't change that, and the IOMMU should be sufficiently paranoid to sanitize the IRTE when the IRQ is freed and reallocated. This will allow hoisting the vCPU tracking to common x86, which in turn will allow most of the IRTE update code to be deduplicated. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 61 +++++++++------------------------------ include/linux/kvm_irqfd.h | 1 + 2 files changed, 15 insertions(+), 47 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 967618ba743a..02b6f0007436 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -81,6 +81,7 @@ bool x2avic_enabled; struct amd_svm_iommu_ir { struct list_head node; /* Used by SVM for per-vcpu ir_list */ void *data; /* Storing pointer to struct amd_ir_data */ + struct vcpu_svm *svm; }; =20 static void avic_activate_vmcb(struct vcpu_svm *svm) @@ -774,23 +775,19 @@ static int avic_set_pi_irte_mode(struct kvm_vcpu *vcp= u, bool activate) return ret; } =20 -static void svm_ir_list_del(struct vcpu_svm *svm, - struct kvm_kernel_irqfd *irqfd, - struct amd_iommu_pi_data *pi) +static void svm_ir_list_del(struct kvm_kernel_irqfd *irqfd) { + struct kvm_vcpu *vcpu =3D irqfd->irq_bypass_vcpu; unsigned long flags; - struct kvm_kernel_irqfd *cur; =20 - spin_lock_irqsave(&svm->ir_list_lock, flags); - list_for_each_entry(cur, &svm->ir_list, vcpu_list) { - if (cur->irq_bypass_data !=3D pi->ir_data) - continue; - if (WARN_ON_ONCE(cur !=3D irqfd)) - continue; - list_del(&irqfd->vcpu_list); - break; - } - spin_unlock_irqrestore(&svm->ir_list_lock, flags); + if (!vcpu) + return; + + spin_lock_irqsave(&to_svm(vcpu)->ir_list_lock, flags); + list_del(&irqfd->vcpu_list); + spin_unlock_irqrestore(&to_svm(vcpu)->ir_list_lock, flags); + + irqfd->irq_bypass_vcpu =3D NULL; } =20 static int svm_ir_list_add(struct vcpu_svm *svm, @@ -803,24 +800,7 @@ static int svm_ir_list_add(struct vcpu_svm *svm, if (WARN_ON_ONCE(!pi->ir_data)) return -EINVAL; =20 - /** - * In some cases, the existing irte is updated and re-set, - * so we need to check here if it's already been * added - * to the ir_list. - */ - if (pi->prev_ga_tag) { - struct kvm *kvm =3D svm->vcpu.kvm; - u32 vcpu_id =3D AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag); - struct kvm_vcpu *prev_vcpu =3D kvm_get_vcpu_by_id(kvm, vcpu_id); - struct vcpu_svm *prev_svm; - - if (!prev_vcpu) - return -EINVAL; - - prev_svm =3D to_svm(prev_vcpu); - svm_ir_list_del(prev_svm, irqfd, pi); - } - + irqfd->irq_bypass_vcpu =3D &svm->vcpu; irqfd->irq_bypass_data =3D pi->ir_data; =20 spin_lock_irqsave(&svm->ir_list_lock, flags); @@ -912,6 +892,8 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, =20 WARN_ON_ONCE(new && memcmp(e, new, sizeof(*new))); =20 + svm_ir_list_del(irqfd); + /** * Here, we setup with legacy mode in the following cases: * 1. When cannot target interrupt to a specific vcpu. @@ -969,21 +951,6 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd= , struct kvm *kvm, pi.prev_ga_tag =3D 0; pi.is_guest_mode =3D false; ret =3D irq_set_vcpu_affinity(host_irq, &pi); - - /** - * Check if the posted interrupt was previously - * setup with the guest_mode by checking if the ga_tag - * was cached. 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Fri, 04 Apr 2025 12:40:05 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:26 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-12-seanjc@google.com> Subject: [PATCH 11/67] KVM: SVM: Delete IRTE link from previous vCPU irrespective of new routing From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Delete the IRTE link from the previous vCPU irrespective of the new routing state. This is a glorified nop (only the ordering changes), as both the "posting" and "remapped" mode paths pre-delete the link. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 02b6f0007436..e9ded2488a0b 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -870,6 +870,12 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd= , struct kvm *kvm, if (!kvm_arch_has_assigned_device(kvm) || !kvm_arch_has_irq_bypass()) return 0; =20 + /* + * If the IRQ was affined to a different vCPU, remove the IRTE metadata + * from the *previous* vCPU's list. + */ + svm_ir_list_del(irqfd); + pr_debug("SVM: %s: host_irq=3D%#x, guest_irq=3D%#x, set=3D%#x\n", __func__, host_irq, guest_irq, set); =20 @@ -892,8 +898,6 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, =20 WARN_ON_ONCE(new && memcmp(e, new, sizeof(*new))); =20 - svm_ir_list_del(irqfd); - /** * Here, we setup with legacy mode in the following cases: * 1. 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AJvYcCXYsPfH8x/bSC/aAp1jKiarLumHf+YuKxOtTvWqO3WtOTtqPOZvX1K/Y5wuoLzrzuiBik6m1VVMCe7OreQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yw6JzSNJe1pQmNoMXb0JPUnsMQwS+UOIcumbpiWvRsHkd8zu27h ignP9ZshllTzm8HxZ9LJcnika8quwnBWqAZ7ULVj7NF/UtRRE/l6MyHd5Fa1HazxQUhfuH0MjhL KPQ== X-Google-Smtp-Source: AGHT+IH1FWkdivy4S+bLPUdZ+zOkMlZOgSIPe0C8D80kAIF34VnktZoafbX6YO039dybyFyARTj7CbbGk/k= X-Received: from pfxa1.prod.google.com ([2002:a05:6a00:1d01:b0:730:90b2:dab]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a20:561a:b0:1f5:9330:2a18 with SMTP id adf61e73a8af0-2010801c42emr4738241637.23.1743795607614; Fri, 04 Apr 2025 12:40:07 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:27 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-13-seanjc@google.com> Subject: [PATCH 12/67] KVM: SVM: Drop pointless masking of default APIC base when setting V_APIC_BAR From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Drop VMCB_AVIC_APIC_BAR_MASK, it's just a regurgitation of the maximum theoretical 4KiB-aligned physical address, i.e. is not novel in any way, and its only usage is to mask the default APIC base, which is 4KiB aligned and (obviously) a legal physical address. No functional change intended. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/include/asm/svm.h | 2 -- arch/x86/kvm/svm/avic.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 9b7fa99ae951..9d3f17732ab4 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -254,8 +254,6 @@ struct __attribute__ ((__packed__)) vmcb_control_area { =20 #define AVIC_DOORBELL_PHYSICAL_ID_MASK GENMASK_ULL(11, 0) =20 -#define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL - #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index e9ded2488a0b..69bf82fc7890 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -253,7 +253,7 @@ void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *= vmcb) vmcb->control.avic_backing_page =3D bpa & AVIC_HPA_MASK; vmcb->control.avic_logical_id =3D lpa & AVIC_HPA_MASK; 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charset="utf-8" Drop AVIC_HPA_MASK and all its users, the mask is just the 4KiB-aligned maximum theoretical physical address for x86-64 CPUs, as x86-64 is currently defined (going beyond PA52 would require an entirely new paging mode, which would arguably create a new, different architecture). All usage in KVM masks the result of page_to_phys(), which on x86-64 is guaranteed to be 4KiB aligned and a legal physical address; if either of those requirements doesn't hold true, KVM has far bigger problems. Drop masking the avic_backing_page with AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK for all the same reasons, but keep the macro even though it's unused in functional code. It's a distinct architectural define, and having the definition in software helps visualize the layout of an entry. And to be hyper-paranoid about MAXPA going beyond 52, add a compile-time assert to ensure the kernel's maximum supported physical address stays in bounds. The unnecessary masking in avic_init_vmcb() also incorrectly assumes that SME's C-bit resides between bits 51:11; that holds true for current CPUs, but isn't required by AMD's architecture: In some implementations, the bit used may be a physical address bit Key word being "may". Opportunistically use the GENMASK_ULL() version for AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK, which is far more readable than a set of repeating Fs. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/include/asm/svm.h | 4 +--- arch/x86/kvm/svm/avic.c | 18 ++++++++++-------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 9d3f17732ab4..8b07939ef3b9 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -247,7 +247,7 @@ struct __attribute__ ((__packed__)) vmcb_control_area { #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) =20 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK GENMASK_ULL(11, 0) -#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12) +#define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK GENMASK_ULL(51, 12) #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63) #define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK (0xFFULL) @@ -282,8 +282,6 @@ enum avic_ipi_failure_cause { static_assert((AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) =3D=3D= AVIC_MAX_PHYSICAL_ID); static_assert((X2AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) =3D= =3D X2AVIC_MAX_PHYSICAL_ID); =20 -#define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF) - #define SVM_SEV_FEAT_SNP_ACTIVE BIT(0) #define SVM_SEV_FEAT_RESTRICTED_INJECTION BIT(3) #define SVM_SEV_FEAT_ALTERNATE_INJECTION BIT(4) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 69bf82fc7890..f04010f66595 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -250,9 +250,9 @@ void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *= vmcb) phys_addr_t lpa =3D __sme_set(page_to_phys(kvm_svm->avic_logical_id_table= _page)); phys_addr_t ppa =3D __sme_set(page_to_phys(kvm_svm->avic_physical_id_tabl= e_page)); =20 - vmcb->control.avic_backing_page =3D bpa & AVIC_HPA_MASK; - vmcb->control.avic_logical_id =3D lpa & AVIC_HPA_MASK; - vmcb->control.avic_physical_id =3D ppa & AVIC_HPA_MASK; + vmcb->control.avic_backing_page =3D bpa; + vmcb->control.avic_logical_id =3D lpa; + vmcb->control.avic_physical_id =3D ppa; vmcb->control.avic_vapic_bar =3D APIC_DEFAULT_PHYS_BASE; =20 if (kvm_apicv_activated(svm->vcpu.kvm)) @@ -310,9 +310,12 @@ static int avic_init_backing_page(struct kvm_vcpu *vcp= u) if (!entry) return -EINVAL; =20 - new_entry =3D __sme_set((page_to_phys(svm->avic_backing_page) & - AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) | - AVIC_PHYSICAL_ID_ENTRY_VALID_MASK); + /* Note, fls64() returns the bit position, +1. */ + BUILD_BUG_ON(__PHYSICAL_MASK_SHIFT > + fls64(AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK)); + + new_entry =3D __sme_set(page_to_phys(svm->avic_backing_page)) | + AVIC_PHYSICAL_ID_ENTRY_VALID_MASK; WRITE_ONCE(*entry, new_entry); =20 svm->avic_physical_id_cache =3D entry; @@ -912,8 +915,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, enable_remapped_mode =3D false; =20 /* Try to enable guest_mode in IRTE */ - pi.base =3D __sme_set(page_to_phys(svm->avic_backing_page) & - AVIC_HPA_MASK); + pi.base =3D __sme_set(page_to_phys(svm->avic_backing_page)); pi.ga_tag =3D AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id, svm->vcpu.vcpu_id); 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AJvYcCW9h8TevHEs+rEaLZzGqRbv7E720vW8Z3uRbV1/9GY+AACdRqO7vcAhVEWcxXR0fv/HZMjHs3VtT93KauA=@vger.kernel.org X-Gm-Message-State: AOJu0Yx9rCubVeDokOfXFo5mP5b2d7UiCQIriOX+GgXli0YLm2+vXC3E +leqgyBDyrCcU8AgfOIORKsV0D/3b9ZusqP/kVxPB6hpGw3E38p1HgQjbSm7sJufrfS9O6vgtIT pbQ== X-Google-Smtp-Source: AGHT+IE27zbdMk+l2PrFIwUw1sH9cB4J4cN7CaOyjTIEfbMCPGg6FI6XQmyQTP9lTfdwAAei1fZlh+dM+/8= X-Received: from pfbjc3.prod.google.com ([2002:a05:6a00:6c83:b0:736:4313:e6bc]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:aa7:888c:0:b0:739:4a93:a5df with SMTP id d2e1a72fcca58-73b6aa6c7c8mr897212b3a.12.1743795611081; Fri, 04 Apr 2025 12:40:11 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:29 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-15-seanjc@google.com> Subject: [PATCH 14/67] KVM: SVM: Add helper to deduplicate code for getting AVIC backing page From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a helper to get the physical address of the AVIC backing page, both to deduplicate code and to prepare for getting the address directly from apic->regs, at which point it won't be all that obvious that the address in question is what SVM calls the AVIC backing page. No functional change intended. Reviewed-by: Maxim Levitsky Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index f04010f66595..a1f4a08d35f5 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -243,14 +243,18 @@ int avic_vm_init(struct kvm *kvm) return err; } =20 +static phys_addr_t avic_get_backing_page_address(struct vcpu_svm *svm) +{ + return __sme_set(page_to_phys(svm->avic_backing_page)); +} + void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *vmcb) { struct kvm_svm *kvm_svm =3D to_kvm_svm(svm->vcpu.kvm); - phys_addr_t bpa =3D __sme_set(page_to_phys(svm->avic_backing_page)); phys_addr_t lpa =3D __sme_set(page_to_phys(kvm_svm->avic_logical_id_table= _page)); phys_addr_t ppa =3D __sme_set(page_to_phys(kvm_svm->avic_physical_id_tabl= e_page)); =20 - vmcb->control.avic_backing_page =3D bpa; + vmcb->control.avic_backing_page =3D avic_get_backing_page_address(svm); vmcb->control.avic_logical_id =3D lpa; vmcb->control.avic_physical_id =3D ppa; vmcb->control.avic_vapic_bar =3D APIC_DEFAULT_PHYS_BASE; @@ -314,7 +318,7 @@ static int avic_init_backing_page(struct kvm_vcpu *vcpu) BUILD_BUG_ON(__PHYSICAL_MASK_SHIFT > fls64(AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK)); =20 - new_entry =3D __sme_set(page_to_phys(svm->avic_backing_page)) | + new_entry =3D avic_get_backing_page_address(svm) | AVIC_PHYSICAL_ID_ENTRY_VALID_MASK; WRITE_ONCE(*entry, new_entry); =20 @@ -854,7 +858,7 @@ get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq= _routing_entry *e, pr_debug("SVM: %s: use GA mode for irq %u\n", __func__, irq.vector); *svm =3D to_svm(vcpu); - vcpu_info->pi_desc_addr =3D __sme_set(page_to_phys((*svm)->avic_backing_p= age)); + vcpu_info->pi_desc_addr =3D avic_get_backing_page_address(*svm); vcpu_info->vector =3D irq.vector; =20 return 0; @@ -915,7 +919,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, enable_remapped_mode =3D false; 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charset="utf-8" Drop vcpu_svm's avic_backing_page pointer and instead grab the physical address of KVM's vAPIC page directly from the source. Getting a physical address from a kernel virtual address is not an expensive operation, and getting the physical address from a struct page is *more* expensive for CONFIG_SPARSEMEM=3Dy kernels. Regardless, none of the paths that consume the address are hot paths, i.e. shaving cycles is not a priority. Eliminating the "cache" means KVM doesn't have to worry about the cache being invalid, which will simplify a future fix when dealing with vCPU IDs that are too big. WARN if KVM attempts to allocate a vCPU's AVIC backing page without an in-kernel local APIC. avic_init_vcpu() bails early if the APIC is not in-kernel, and KVM disallows enabling an in-kernel APIC after vCPUs have been created, i.e. it should be impossible to reach avic_init_backing_page() without the vAPIC being allocated. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 6 ++---- arch/x86/kvm/svm/svm.h | 1 - 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index a1f4a08d35f5..c8ba2ce4cfd8 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -245,7 +245,7 @@ int avic_vm_init(struct kvm *kvm) =20 static phys_addr_t avic_get_backing_page_address(struct vcpu_svm *svm) { - return __sme_set(page_to_phys(svm->avic_backing_page)); + return __sme_set(__pa(svm->vcpu.arch.apic->regs)); } =20 void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *vmcb) @@ -290,7 +290,7 @@ static int avic_init_backing_page(struct kvm_vcpu *vcpu) (id > X2AVIC_MAX_PHYSICAL_ID)) return -EINVAL; =20 - if (!vcpu->arch.apic->regs) + if (WARN_ON_ONCE(!vcpu->arch.apic->regs)) return -EINVAL; =20 if (kvm_apicv_activated(vcpu->kvm)) { @@ -307,8 +307,6 @@ static int avic_init_backing_page(struct kvm_vcpu *vcpu) return ret; } =20 - svm->avic_backing_page =3D virt_to_page(vcpu->arch.apic->regs); - /* Setting AVIC backing page address in the phy APIC ID table */ entry =3D avic_get_physical_id_entry(vcpu, id); if (!entry) diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 294d5594c724..1cc4e145577c 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -301,7 +301,6 @@ struct vcpu_svm { =20 u32 ldr_reg; u32 dfr_reg; - struct page *avic_backing_page; u64 *avic_physical_id_cache; =20 /* --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 439522253FB for ; Fri, 4 Apr 2025 19:40:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Fri, 04 Apr 2025 12:40:14 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:31 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-17-seanjc@google.com> Subject: [PATCH 16/67] KVM: SVM: Inhibit AVIC if ID is too big instead of rejecting vCPU creation From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Inhibit AVIC with a new "ID too big" flag if userspace creates a vCPU with an ID that is too big, but otherwise allow vCPU creation to succeed. Rejecting KVM_CREATE_VCPU with EINVAL violates KVM's ABI as KVM advertises that the max vCPU ID is 4095, but disallows creating vCPUs with IDs bigger than 254 (AVIC) or 511 (x2AVIC). Alternatively, KVM could advertise an accurate value depending on which AVIC mode is in use, but that wouldn't really solve the underlying problem, e.g. would be a breaking change if KVM were to ever try and enable AVIC or x2AVIC by default. Cc: Maxim Levitsky Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/include/asm/kvm_host.h | 9 ++++++++- arch/x86/kvm/svm/avic.c | 16 ++++++++++++++-- arch/x86/kvm/svm/svm.h | 3 ++- 3 files changed, 24 insertions(+), 4 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 54f3cf73329b..0583d8a9c8d4 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1304,6 +1304,12 @@ enum kvm_apicv_inhibit { */ APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED, =20 + /* + * AVIC is disabled because the vCPU's APIC ID is beyond the max + * supported by AVIC/x2AVIC, i.e. the vCPU is unaddressable. + */ + APICV_INHIBIT_REASON_PHYSICAL_ID_TOO_BIG, + NR_APICV_INHIBIT_REASONS, }; =20 @@ -1322,7 +1328,8 @@ enum kvm_apicv_inhibit { __APICV_INHIBIT_REASON(IRQWIN), \ __APICV_INHIBIT_REASON(PIT_REINJ), \ __APICV_INHIBIT_REASON(SEV), \ - __APICV_INHIBIT_REASON(LOGICAL_ID_ALIASED) + __APICV_INHIBIT_REASON(LOGICAL_ID_ALIASED), \ + __APICV_INHIBIT_REASON(PHYSICAL_ID_TOO_BIG) =20 struct kvm_arch { unsigned long n_used_mmu_pages; diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index c8ba2ce4cfd8..ba8dfc8a12f4 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -286,9 +286,21 @@ static int avic_init_backing_page(struct kvm_vcpu *vcp= u) int id =3D vcpu->vcpu_id; struct vcpu_svm *svm =3D to_svm(vcpu); =20 + /* + * Inhibit AVIC if the vCPU ID is bigger than what is supported by AVIC + * hardware. Do so immediately, i.e. don't defer the update via a + * request, as avic_vcpu_load() expects to be called if and only if the + * vCPU has fully initialized AVIC. Immediately clear apicv_active, + * as avic_vcpu_load() assumes avic_physical_id_cache is valid, i.e. + * waiting until KVM_REQ_APICV_UPDATE is processed on the first KVM_RUN + * will result in an NULL pointer deference when loading the vCPU. + */ if ((!x2avic_enabled && id > AVIC_MAX_PHYSICAL_ID) || - (id > X2AVIC_MAX_PHYSICAL_ID)) - return -EINVAL; + (id > X2AVIC_MAX_PHYSICAL_ID)) { + kvm_set_apicv_inhibit(vcpu->kvm, APICV_INHIBIT_REASON_PHYSICAL_ID_TOO_BI= G); + vcpu->arch.apic->apicv_active =3D false; + return 0; + } =20 if (WARN_ON_ONCE(!vcpu->arch.apic->regs)) return -EINVAL; diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 1cc4e145577c..7af28802ebee 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -715,7 +715,8 @@ extern struct kvm_x86_nested_ops svm_nested_ops; BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED) | \ BIT(APICV_INHIBIT_REASON_APIC_ID_MODIFIED) | \ BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED) | \ - BIT(APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED) \ + BIT(APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED) | \ + BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_TOO_BIG) \ ) =20 bool avic_hardware_setup(void); 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charset="utf-8" Drop avic_get_physical_id_entry()'s compatibility check on the incoming ID, as its sole caller, avic_init_backing_page(), performs the exact same check. Drop avic_get_physical_id_entry() entirely as the only remaining functionality is getting the address of the Physical ID table, and accessing the array without an immediate bounds check is kludgy. Opportunistically add a compile-time assertion to ensure the vcpu_id can't result in a bounds overflow, e.g. if KVM (really) messed up a maximum physical ID #define, as well as run-time assertions so that a NULL pointer dereference is morphed into a safer WARN(). No functional change intended. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 47 +++++++++++++++++------------------------ 1 file changed, 19 insertions(+), 28 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index ba8dfc8a12f4..344541e418c3 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -265,35 +265,19 @@ void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb= *vmcb) avic_deactivate_vmcb(svm); } =20 -static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu, - unsigned int index) -{ - u64 *avic_physical_id_table; - struct kvm_svm *kvm_svm =3D to_kvm_svm(vcpu->kvm); - - if ((!x2avic_enabled && index > AVIC_MAX_PHYSICAL_ID) || - (index > X2AVIC_MAX_PHYSICAL_ID)) - return NULL; - - avic_physical_id_table =3D page_address(kvm_svm->avic_physical_id_table_p= age); - - return &avic_physical_id_table[index]; -} - static int avic_init_backing_page(struct kvm_vcpu *vcpu) { - u64 *entry, new_entry; - int id =3D vcpu->vcpu_id; + struct kvm_svm *kvm_svm =3D to_kvm_svm(vcpu->kvm); struct vcpu_svm *svm =3D to_svm(vcpu); + u32 id =3D vcpu->vcpu_id; + u64 *table, new_entry; =20 /* * Inhibit AVIC if the vCPU ID is bigger than what is supported by AVIC - * hardware. Do so immediately, i.e. don't defer the update via a - * request, as avic_vcpu_load() expects to be called if and only if the - * vCPU has fully initialized AVIC. Immediately clear apicv_active, - * as avic_vcpu_load() assumes avic_physical_id_cache is valid, i.e. - * waiting until KVM_REQ_APICV_UPDATE is processed on the first KVM_RUN - * will result in an NULL pointer deference when loading the vCPU. + * hardware. Immediately clear apicv_active, i.e. don't wait until the + * KVM_REQ_APICV_UPDATE request is processed on the first KVM_RUN, as + * avic_vcpu_load() expects to be called if and only if the vCPU has + * fully initialized AVIC. */ if ((!x2avic_enabled && id > AVIC_MAX_PHYSICAL_ID) || (id > X2AVIC_MAX_PHYSICAL_ID)) { @@ -302,6 +286,9 @@ static int avic_init_backing_page(struct kvm_vcpu *vcpu) return 0; } =20 + BUILD_BUG_ON((AVIC_MAX_PHYSICAL_ID + 1) * sizeof(*table) > PAGE_SIZE || + (X2AVIC_MAX_PHYSICAL_ID + 1) * sizeof(*table) > PAGE_SIZE); + if (WARN_ON_ONCE(!vcpu->arch.apic->regs)) return -EINVAL; =20 @@ -320,9 +307,7 @@ static int avic_init_backing_page(struct kvm_vcpu *vcpu) } =20 /* Setting AVIC backing page address in the phy APIC ID table */ - entry =3D avic_get_physical_id_entry(vcpu, id); - if (!entry) - return -EINVAL; + table =3D page_address(kvm_svm->avic_physical_id_table_page); =20 /* Note, fls64() returns the bit position, +1. */ BUILD_BUG_ON(__PHYSICAL_MASK_SHIFT > @@ -330,9 +315,9 @@ static int avic_init_backing_page(struct kvm_vcpu *vcpu) =20 new_entry =3D avic_get_backing_page_address(svm) | AVIC_PHYSICAL_ID_ENTRY_VALID_MASK; - WRITE_ONCE(*entry, new_entry); + WRITE_ONCE(table[id], new_entry); =20 - svm->avic_physical_id_cache =3D entry; + svm->avic_physical_id_cache =3D &table[id]; =20 return 0; } @@ -1018,6 +1003,9 @@ void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) if (WARN_ON(h_physical_id & ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK= )) return; =20 + if (WARN_ON_ONCE(!svm->avic_physical_id_cache)) + return; + /* * No need to update anything if the vCPU is blocking, i.e. if the vCPU * is being scheduled in after being preempted. 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charset="utf-8" Allocate and track AVIC's logical and physical tables as u32 and u64 pointers respectively, as managing the pages as "struct page" pointers adds an almost absurd amount of boilerplate and complexity. E.g. with page_address() out of the way, svm->avic_physical_id_cache becomes completely superfluous, and will be removed in a future cleanup. No functional change intended. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 49 ++++++++++++++--------------------------- arch/x86/kvm/svm/svm.h | 4 ++-- 2 files changed, 18 insertions(+), 35 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 344541e418c3..ae6d2c00397f 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -181,10 +181,8 @@ void avic_vm_destroy(struct kvm *kvm) if (!enable_apicv) return; =20 - if (kvm_svm->avic_logical_id_table_page) - __free_page(kvm_svm->avic_logical_id_table_page); - if (kvm_svm->avic_physical_id_table_page) - __free_page(kvm_svm->avic_physical_id_table_page); + free_page((unsigned long)kvm_svm->avic_logical_id_table); + free_page((unsigned long)kvm_svm->avic_physical_id_table); =20 spin_lock_irqsave(&svm_vm_data_hash_lock, flags); hash_del(&kvm_svm->hnode); @@ -197,27 +195,19 @@ int avic_vm_init(struct kvm *kvm) int err =3D -ENOMEM; struct kvm_svm *kvm_svm =3D to_kvm_svm(kvm); struct kvm_svm *k2; - struct page *p_page; - struct page *l_page; u32 vm_id; =20 if (!enable_apicv) return 0; =20 - /* Allocating physical APIC ID table (4KB) */ - p_page =3D alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); - if (!p_page) + kvm_svm->avic_physical_id_table =3D (void *)get_zeroed_page(GFP_KERNEL_AC= COUNT); + if (!kvm_svm->avic_physical_id_table) goto free_avic; =20 - kvm_svm->avic_physical_id_table_page =3D p_page; - - /* Allocating logical APIC ID table (4KB) */ - l_page =3D alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); - if (!l_page) + kvm_svm->avic_logical_id_table =3D (void *)get_zeroed_page(GFP_KERNEL_ACC= OUNT); + if (!kvm_svm->avic_logical_id_table) goto free_avic; =20 - kvm_svm->avic_logical_id_table_page =3D l_page; - spin_lock_irqsave(&svm_vm_data_hash_lock, flags); again: vm_id =3D next_vm_id =3D (next_vm_id + 1) & AVIC_VM_ID_MASK; @@ -251,12 +241,10 @@ static phys_addr_t avic_get_backing_page_address(stru= ct vcpu_svm *svm) void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *vmcb) { struct kvm_svm *kvm_svm =3D to_kvm_svm(svm->vcpu.kvm); - phys_addr_t lpa =3D __sme_set(page_to_phys(kvm_svm->avic_logical_id_table= _page)); - phys_addr_t ppa =3D __sme_set(page_to_phys(kvm_svm->avic_physical_id_tabl= e_page)); =20 vmcb->control.avic_backing_page =3D avic_get_backing_page_address(svm); - vmcb->control.avic_logical_id =3D lpa; - vmcb->control.avic_physical_id =3D ppa; + vmcb->control.avic_logical_id =3D __sme_set(__pa(kvm_svm->avic_logical_id= _table)); + vmcb->control.avic_physical_id =3D __sme_set(__pa(kvm_svm->avic_physical_= id_table)); vmcb->control.avic_vapic_bar =3D APIC_DEFAULT_PHYS_BASE; =20 if (kvm_apicv_activated(svm->vcpu.kvm)) @@ -270,7 +258,7 @@ static int avic_init_backing_page(struct kvm_vcpu *vcpu) struct kvm_svm *kvm_svm =3D to_kvm_svm(vcpu->kvm); struct vcpu_svm *svm =3D to_svm(vcpu); u32 id =3D vcpu->vcpu_id; - u64 *table, new_entry; + u64 new_entry; =20 /* * Inhibit AVIC if the vCPU ID is bigger than what is supported by AVIC @@ -286,8 +274,8 @@ static int avic_init_backing_page(struct kvm_vcpu *vcpu) return 0; } =20 - BUILD_BUG_ON((AVIC_MAX_PHYSICAL_ID + 1) * sizeof(*table) > PAGE_SIZE || - (X2AVIC_MAX_PHYSICAL_ID + 1) * sizeof(*table) > PAGE_SIZE); + BUILD_BUG_ON((AVIC_MAX_PHYSICAL_ID + 1) * sizeof(new_entry) > PAGE_SIZE || + (X2AVIC_MAX_PHYSICAL_ID + 1) * sizeof(new_entry) > PAGE_SIZE); =20 if (WARN_ON_ONCE(!vcpu->arch.apic->regs)) return -EINVAL; @@ -306,18 +294,16 @@ static int avic_init_backing_page(struct kvm_vcpu *vc= pu) return ret; } =20 - /* Setting AVIC backing page address in the phy APIC ID table */ - table =3D page_address(kvm_svm->avic_physical_id_table_page); - /* Note, fls64() returns the bit position, +1. */ BUILD_BUG_ON(__PHYSICAL_MASK_SHIFT > fls64(AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK)); =20 + /* Setting AVIC backing page address in the phy APIC ID table */ new_entry =3D avic_get_backing_page_address(svm) | AVIC_PHYSICAL_ID_ENTRY_VALID_MASK; - WRITE_ONCE(table[id], new_entry); + WRITE_ONCE(kvm_svm->avic_physical_id_table[id], new_entry); =20 - svm->avic_physical_id_cache =3D &table[id]; + svm->avic_physical_id_cache =3D &kvm_svm->avic_physical_id_table[id]; =20 return 0; } @@ -451,7 +437,7 @@ static int avic_kick_target_vcpus_fast(struct kvm *kvm,= struct kvm_lapic *source if (apic_x2apic_mode(source)) avic_logical_id_table =3D NULL; else - avic_logical_id_table =3D page_address(kvm_svm->avic_logical_id_table_p= age); + avic_logical_id_table =3D kvm_svm->avic_logical_id_table; =20 /* * AVIC is inhibited if vCPUs aren't mapped 1:1 with logical @@ -553,7 +539,6 @@ unsigned long avic_vcpu_get_apicv_inhibit_reasons(struc= t kvm_vcpu *vcpu) static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool= flat) { struct kvm_svm *kvm_svm =3D to_kvm_svm(vcpu->kvm); - u32 *logical_apic_id_table; u32 cluster, index; =20 ldr =3D GET_APIC_LOGICAL_ID(ldr); @@ -574,9 +559,7 @@ static u32 *avic_get_logical_id_entry(struct kvm_vcpu *= vcpu, u32 ldr, bool flat) return NULL; index +=3D (cluster << 2); =20 - logical_apic_id_table =3D (u32 *) page_address(kvm_svm->avic_logical_id_t= able_page); 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Fri, 04 Apr 2025 12:40:19 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:34 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-20-seanjc@google.com> Subject: [PATCH 19/67] KVM: SVM: Drop superfluous "cache" of AVIC Physical ID entry pointer From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Drop the vCPU's pointer to its AVIC Physical ID entry, and simply index the table directly. Caching a pointer address is completely unnecessary for performance, and while the field technically caches the result of the pointer calculation, it's all too easy to misinterpret the name and think that the field somehow caches the _data_ in the table. No functional change intended. Suggested-by: Maxim Levitsky Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 27 +++++++++++++++------------ arch/x86/kvm/svm/svm.h | 1 - 2 files changed, 15 insertions(+), 13 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index ae6d2c00397f..c4e6c97b736f 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -303,8 +303,6 @@ static int avic_init_backing_page(struct kvm_vcpu *vcpu) AVIC_PHYSICAL_ID_ENTRY_VALID_MASK; WRITE_ONCE(kvm_svm->avic_physical_id_table[id], new_entry); =20 - svm->avic_physical_id_cache =3D &kvm_svm->avic_physical_id_table[id]; - return 0; } =20 @@ -779,13 +777,16 @@ static int svm_ir_list_add(struct vcpu_svm *svm, struct kvm_kernel_irqfd *irqfd, struct amd_iommu_pi_data *pi) { + struct kvm_vcpu *vcpu =3D &svm->vcpu; + struct kvm *kvm =3D vcpu->kvm; + struct kvm_svm *kvm_svm =3D to_kvm_svm(kvm); unsigned long flags; u64 entry; =20 if (WARN_ON_ONCE(!pi->ir_data)) return -EINVAL; =20 - irqfd->irq_bypass_vcpu =3D &svm->vcpu; + irqfd->irq_bypass_vcpu =3D vcpu; irqfd->irq_bypass_data =3D pi->ir_data; =20 spin_lock_irqsave(&svm->ir_list_lock, flags); @@ -796,7 +797,7 @@ static int svm_ir_list_add(struct vcpu_svm *svm, * will update the pCPU info when the vCPU awkened and/or scheduled in. * See also avic_vcpu_load(). */ - entry =3D READ_ONCE(*(svm->avic_physical_id_cache)); + entry =3D READ_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id]); if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) amd_iommu_update_ga(entry & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK, true, pi->ir_data); @@ -976,17 +977,18 @@ avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu= , int cpu, bool r) =20 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) { - u64 entry; + struct kvm_svm *kvm_svm =3D to_kvm_svm(vcpu->kvm); int h_physical_id =3D kvm_cpu_get_apicid(cpu); struct vcpu_svm *svm =3D to_svm(vcpu); unsigned long flags; + u64 entry; =20 lockdep_assert_preemption_disabled(); =20 if (WARN_ON(h_physical_id & ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK= )) return; =20 - if (WARN_ON_ONCE(!svm->avic_physical_id_cache)) + if (WARN_ON_ONCE(vcpu->vcpu_id * sizeof(entry) >=3D PAGE_SIZE)) return; =20 /* @@ -1008,14 +1010,14 @@ void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) */ spin_lock_irqsave(&svm->ir_list_lock, flags); =20 - entry =3D READ_ONCE(*(svm->avic_physical_id_cache)); + entry =3D READ_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id]); WARN_ON_ONCE(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); =20 entry &=3D ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; entry |=3D (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK); entry |=3D AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; =20 - WRITE_ONCE(*(svm->avic_physical_id_cache), entry); + WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry); avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, true); =20 spin_unlock_irqrestore(&svm->ir_list_lock, flags); @@ -1023,13 +1025,14 @@ void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) =20 void avic_vcpu_put(struct kvm_vcpu *vcpu) { - u64 entry; + struct kvm_svm *kvm_svm =3D to_kvm_svm(vcpu->kvm); struct vcpu_svm *svm =3D to_svm(vcpu); unsigned long flags; + u64 entry; =20 lockdep_assert_preemption_disabled(); =20 - if (WARN_ON_ONCE(!svm->avic_physical_id_cache)) + if (WARN_ON_ONCE(vcpu->vcpu_id * sizeof(entry) >=3D PAGE_SIZE)) return; =20 /* @@ -1039,7 +1042,7 @@ void avic_vcpu_put(struct kvm_vcpu *vcpu) * can't be scheduled out and thus avic_vcpu_{put,load}() can't run * recursively. */ - entry =3D READ_ONCE(*(svm->avic_physical_id_cache)); + entry =3D READ_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id]); =20 /* Nothing to do if IsRunning =3D=3D '0' due to vCPU blocking. */ if (!(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)) @@ -1058,7 +1061,7 @@ void avic_vcpu_put(struct kvm_vcpu *vcpu) avic_update_iommu_vcpu_affinity(vcpu, -1, 0); =20 entry &=3D ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; - WRITE_ONCE(*(svm->avic_physical_id_cache), entry); + WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry); =20 spin_unlock_irqrestore(&svm->ir_list_lock, flags); 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charset="utf-8" Move enable_ipiv to common x86 so that it can be reused by SVM to control IPI virtualization when AVIC is enabled. SVM doesn't actually provide a way to truly disable IPI virtualization, but KVM can get close enough by skipping the necessary table programming. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/vmx/capabilities.h | 1 - arch/x86/kvm/vmx/vmx.c | 2 -- arch/x86/kvm/x86.c | 3 +++ 4 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 0583d8a9c8d4..85f45fc5156d 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1932,6 +1932,7 @@ struct kvm_arch_async_pf { extern u32 __read_mostly kvm_nr_uret_msrs; extern bool __read_mostly allow_smaller_maxphyaddr; extern bool __read_mostly enable_apicv; +extern bool __read_mostly enable_ipiv; extern bool __read_mostly enable_device_posted_irqs; extern struct kvm_x86_ops kvm_x86_ops; =20 diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilitie= s.h index cb6588238f46..5316c27f6099 100644 --- a/arch/x86/kvm/vmx/capabilities.h +++ b/arch/x86/kvm/vmx/capabilities.h @@ -15,7 +15,6 @@ extern bool __read_mostly enable_ept; extern bool __read_mostly enable_unrestricted_guest; extern bool __read_mostly enable_ept_ad_bits; extern bool __read_mostly enable_pml; -extern bool __read_mostly enable_ipiv; extern int __read_mostly pt_mode; =20 #define PT_MODE_SYSTEM 0 diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c index ac7f1df612e8..56b68db345a7 100644 --- a/arch/x86/kvm/vmx/vmx.c +++ b/arch/x86/kvm/vmx/vmx.c @@ -111,8 +111,6 @@ static bool __read_mostly fasteoi =3D 1; module_param(fasteoi, bool, 0444); =20 module_param(enable_apicv, bool, 0444); - -bool __read_mostly enable_ipiv =3D true; module_param(enable_ipiv, bool, 0444); =20 module_param(enable_device_posted_irqs, bool, 0444); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 23376fcd928c..52d8d0635603 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -227,6 +227,9 @@ EXPORT_SYMBOL_GPL(allow_smaller_maxphyaddr); bool __read_mostly enable_apicv =3D true; EXPORT_SYMBOL_GPL(enable_apicv); =20 +bool __read_mostly enable_ipiv =3D true; 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AJvYcCUqKGKJdhWoPJB9wdjbMaLd34tlNNENhJYeQzaZw0P2lauvpYbLKuPiiVRmtnpF81nbYuHpAfzR3T3VgWo=@vger.kernel.org X-Gm-Message-State: AOJu0Yy/8/hVNAcDTwFuEeszCdJYgxTVB4GDTzOpEvzTzug73jqxwCaT oWTfzIOi9G1wtAsn9g2SFldMeuUwtFdKCjIZAQQE8fx7RvlS4OtwS2eoZhH93t9gB4Q8S3L7FVg llQ== X-Google-Smtp-Source: AGHT+IE/kINVfoZrJ4qY9CHehtr/vzhchg2tVy6B+yeCOOea3l97XGuuqzOWftR5UeAUcXh68E3v1s4JzR8= X-Received: from pfbbe17.prod.google.com ([2002:a05:6a00:1f11:b0:730:9951:c9ea]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a17:90b:5387:b0:2fa:3b6b:3370 with SMTP id 98e67ed59e1d1-3057a68c61amr11505416a91.16.1743795623377; Fri, 04 Apr 2025 12:40:23 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:36 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-22-seanjc@google.com> Subject: [PATCH 21/67] KVM: SVM: Add enable_ipiv param, never set IsRunning if disabled From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Maxim Levitsky Let userspace "disable" IPI virtualization for AVIC via the enable_ipiv module param, by never setting IsRunning. SVM doesn't provide a way to disable IPI virtualization in hardware, but by ensuring CPUs never see IsRunning=3D1, every IPI in the guest (except for self-IPIs) will generate a VM-Exit. To avoid setting the real IsRunning bit, while still allowing KVM to use each vCPU's entry to update GA log entries, simply maintain a shadow of the entry, without propagating IsRunning updates to the real table when IPI virtualization is disabled. Providing a way to effectively disable IPI virtualization will allow KVM to safely enable AVIC on hardware that is susceptible to erratum #1235, which causes hardware to sometimes fail to detect that the IsRunning bit has been cleared by software. Note, the table _must_ be fully populated, as broadcast IPIs skip invalid entries, i.e. won't generate VM-Exit if every entry is invalid, and so simply pointing the VMCB at a common dummy table won't work. Alternatively, KVM could allocate a shadow of the entire table, but that'd be a waste of 4KiB since the per-vCPU entry doesn't actually consume an additional 8 bytes of memory (vCPU structures are large enough that they are backed by order-N pages). Signed-off-by: Maxim Levitsky [sean: keep "entry" variables, reuse enable_ipiv, split from erratum] Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 32 ++++++++++++++++++++++++++------ arch/x86/kvm/svm/svm.c | 2 ++ arch/x86/kvm/svm/svm.h | 9 +++++++++ 3 files changed, 37 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index c4e6c97b736f..eea362cd415d 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -301,6 +301,13 @@ static int avic_init_backing_page(struct kvm_vcpu *vcp= u) /* Setting AVIC backing page address in the phy APIC ID table */ new_entry =3D avic_get_backing_page_address(svm) | AVIC_PHYSICAL_ID_ENTRY_VALID_MASK; + svm->avic_physical_id_entry =3D new_entry; + + /* + * Initialize the real table, as vCPUs must have a valid entry in order + * for broadcast IPIs to function correctly (broadcast IPIs ignore + * invalid entries, i.e. aren't guaranteed to generate a VM-Exit). + */ WRITE_ONCE(kvm_svm->avic_physical_id_table[id], new_entry); =20 return 0; @@ -778,8 +785,6 @@ static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi) { struct kvm_vcpu *vcpu =3D &svm->vcpu; - struct kvm *kvm =3D vcpu->kvm; - struct kvm_svm *kvm_svm =3D to_kvm_svm(kvm); unsigned long flags; u64 entry; =20 @@ -797,7 +802,7 @@ static int svm_ir_list_add(struct vcpu_svm *svm, * will update the pCPU info when the vCPU awkened and/or scheduled in. * See also avic_vcpu_load(). */ - entry =3D READ_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id]); + entry =3D svm->avic_physical_id_entry; if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) amd_iommu_update_ga(entry & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK, true, pi->ir_data); @@ -1010,14 +1015,26 @@ void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) */ spin_lock_irqsave(&svm->ir_list_lock, flags); =20 - entry =3D READ_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id]); + entry =3D svm->avic_physical_id_entry; WARN_ON_ONCE(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); =20 entry &=3D ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; entry |=3D (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK); entry |=3D AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; =20 + svm->avic_physical_id_entry =3D entry; + + /* + * If IPI virtualization is disabled, clear IsRunning when updating the + * actual Physical ID table, so that the CPU never sees IsRunning=3D1. + * Keep the APIC ID up-to-date in the entry to minimize the chances of + * things going sideways if hardware peeks at the ID. + */ + if (!enable_ipiv) + entry &=3D ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; + WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry); + avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, true); =20 spin_unlock_irqrestore(&svm->ir_list_lock, flags); @@ -1042,7 +1059,7 @@ void avic_vcpu_put(struct kvm_vcpu *vcpu) * can't be scheduled out and thus avic_vcpu_{put,load}() can't run * recursively. */ - entry =3D READ_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id]); + entry =3D svm->avic_physical_id_entry; =20 /* Nothing to do if IsRunning =3D=3D '0' due to vCPU blocking. */ if (!(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)) @@ -1061,7 +1078,10 @@ void avic_vcpu_put(struct kvm_vcpu *vcpu) avic_update_iommu_vcpu_affinity(vcpu, -1, 0); =20 entry &=3D ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; - WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry); + svm->avic_physical_id_entry =3D entry; + + if (enable_ipiv) + WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry); =20 spin_unlock_irqrestore(&svm->ir_list_lock, flags); =20 diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index def76e63562d..43c4933d7da6 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -230,6 +230,7 @@ module_param(tsc_scaling, int, 0444); */ static bool avic; module_param(avic, bool, 0444); +module_param(enable_ipiv, bool, 0444); =20 module_param(enable_device_posted_irqs, bool, 0444); =20 @@ -5440,6 +5441,7 @@ static __init int svm_hardware_setup(void) enable_apicv =3D avic =3D avic && avic_hardware_setup(); =20 if (!enable_apicv) { + enable_ipiv =3D false; svm_x86_ops.vcpu_blocking =3D NULL; svm_x86_ops.vcpu_unblocking =3D NULL; svm_x86_ops.vcpu_get_apicv_inhibit_reasons =3D NULL; diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index e223e57f7def..6ad0aa86f78d 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -302,6 +302,15 @@ struct vcpu_svm { u32 ldr_reg; u32 dfr_reg; =20 + /* + * This is essentially a shadow of the vCPU's actual entry in the + * Physical ID table that is programmed into the VMCB, i.e. that is + * seen by the CPU. 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charset="utf-8" From: Maxim Levitsky Disable IPI virtualization on AMD Family 17h CPUs (Zen2 and Zen1), as hardware doesn't reliably detect changes to the 'IsRunning' bit during ICR write emulation, and might fail to VM-Exit on the sending vCPU, if IsRunning was recently cleared. The absence of the VM-Exit leads to KVM not waking (or triggering nested VM-Exit) of the target vCPU(s) of the IPI, which can lead to hung vCPUs, unbounded delays in L2 execution, etc. To workaround the erratum, simply disable IPI virtualization, which prevents KVM from setting IsRunning and thus eliminates the race where hardware sees a stale IsRunning=3D1. As a result, all ICR writes (except when "Self" shorthand is used) will VM-Exit and therefore be correctly emulated by KVM. Disabling IPI virtualization does carry a performance penalty, but benchmarkng shows that enabling AVIC without IPI virtualization is still much better than not using AVIC at all, because AVIC still accelerates posted interrupts and the receiving end of the IPIs. Note, when virtualizaing Self-IPIs, the CPU skips reading the physical ID table and updates the vIRR directly (because the vCPU is by definition actively running), i.e. Self-IPI isn't susceptible to the erratum *and* is still accelerated by hardware. Signed-off-by: Maxim Levitsky [sean: rebase, massage changelog, disallow user override] Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index eea362cd415d..aba3f9d2ad02 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -1199,6 +1199,14 @@ bool avic_hardware_setup(void) if (x2avic_enabled) pr_info("x2AVIC enabled\n"); =20 + /* + * Disable IPI virtualization for AMD Family 17h CPUs (Zen1 and Zen2) + * due to erratum 1235, which results in missed GA log events and thus + * missed wake events for blocking vCPUs due to the CPU failing to see + * a software update to clear IsRunning. + */ + enable_ipiv =3D enable_ipiv && boot_cpu_data.x86 !=3D 0x17; + amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); =20 return true; --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89C71229B3C for ; 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Fri, 04 Apr 2025 12:40:26 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:38 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-24-seanjc@google.com> Subject: [PATCH 23/67] KVM: VMX: Suppress PI notifications whenever the vCPU is put From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Suppress posted interrupt notifications (set PID.SN=3D1) whenever the vCPU is put, i.e. unloaded, not just when the vCPU is preempted, as KVM doesn't do anything in response to a notification IRQ that arrives in the host, nor does KVM rely on the Outstanding Notification (PID.ON) flag when the vCPU is unloaded. And, the cost of scanning the PIR to manually set PID.ON when loading the vCPU is quite small, especially relative to the cost of loading (and unloading) a vCPU. On the flip side, leaving SN clear means a notification for the vCPU will result in a spurious IRQ for the pCPU, even if vCPU task is scheduled out, running in userspace, etc. Even worse, if the pCPU is running a different vCPU, the spurious IRQ could trigger posted interrupt processing for the wrong vCPU, which is technically a violation of the architecture, as setting bits in PIR aren't supposed to be propagated to the vIRR until a notification IRQ is received. The saving grace of the current behavior is that hardware sends notification interrupts if and only if PID.ON=3D0, i.e. only the first posted interrupt for a vCPU will trigger a spurious IRQ (for each window where the vCPU is unloaded). Ideally, KVM would suppress notifications before enabling IRQs in the VM-Exit, but KVM relies on PID.ON as an indicator that there is a posted interrupt pending in PIR, e.g. in vmx_sync_pir_to_irr(), and sadly there is no way to ask hardware to set PID.ON, but not generate an interrupt. That could be solved by using pi_has_pending_interrupt() instead of checking only PID.ON, but it's not at all clear that would be a performance win, as KVM would end up scanning the entire PIR whenever an interrupt isn't pending. And long term, the spurious IRQ window, i.e. where a vCPU is loaded with IRQs enabled, can effectively be made smaller for hot paths by moving performance critical VM-Exit handlers into the fastpath, i.e. by never enabling IRQs for hot path VM-Exits. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/vmx/posted_intr.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/arch/x86/kvm/vmx/posted_intr.c b/arch/x86/kvm/vmx/posted_intr.c index 1b6b655a2b8a..00818ca30ee0 100644 --- a/arch/x86/kvm/vmx/posted_intr.c +++ b/arch/x86/kvm/vmx/posted_intr.c @@ -70,13 +70,10 @@ void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) /* * If the vCPU wasn't on the wakeup list and wasn't migrated, then the * full update can be skipped as neither the vector nor the destination - * needs to be changed. + * needs to be changed. Clear SN even if there is no assigned device, + * again for simplicity. */ if (pi_desc->nv !=3D POSTED_INTR_WAKEUP_VECTOR && vcpu->cpu =3D=3D cpu) { - /* - * Clear SN if it was set due to being preempted. Again, do - * this even if there is no assigned device for simplicity. - */ if (pi_test_and_clear_sn(pi_desc)) goto after_clear_sn; return; @@ -200,15 +197,22 @@ void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) if (!vmx_needs_pi_wakeup(vcpu)) return; =20 - if (kvm_vcpu_is_blocking(vcpu) && !vmx_interrupt_blocked(vcpu)) + /* + * If the vCPU is blocking with IRQs enabled and ISN'T being preempted, + * enable the wakeup handler so that notification IRQ wakes the vCPU as + * expected. There is no need to enable the wakeup handler if the vCPU + * is preempted between setting its wait state and manually scheduling + * out, as the task is still runnable, i.e. doesn't need a wake event + * from KVM to be scheduled in. + * + * If the wakeup handler isn't being enabled, Suppress Notifications as + * the cost of propagating PIR.IRR to PID.ON is negligible compared to + * the cost of a spurious IRQ, and vCPU put/load is a slow path. + */ + if (!vcpu->preempted && kvm_vcpu_is_blocking(vcpu) && + !vmx_interrupt_blocked(vcpu)) pi_enable_wakeup_handler(vcpu); - - /* - * Set SN when the vCPU is preempted. Note, the vCPU can both be seen - * as blocking and preempted, e.g. if it's preempted between setting - * its wait state and manually scheduling out. - */ - if (vcpu->preempted) + else pi_set_sn(pi_desc); } =20 --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C0E922A4EB for ; Fri, 4 Apr 2025 19:40:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743795630; cv=none; b=o0OGdplkmNjF9aiL+3i66QJpJSkjvKUzsHhVWFb9A359AsAsnuHniuKfVb8lPdg5Ime9zdb2hXzmDC2e225nGJROTr+2Mt70Nj4h0JFB/YneaQ8/+GLCv0AKNN95UwKf4D2Ro7uKi0zKp2Z0K//qUgx4n4gJCbKI9pbiBR9arEQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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charset="utf-8" Add a comment to explain why KVM clears IsRunning when putting a vCPU, even though leaving IsRunning=3D1 would be ok from a functional perspective. Per Maxim's experiments, a misbehaving VM could spam the AVIC doorbell so fast as to induce a 50%+ loss in performance. Link: https://lore.kernel.org/all/8d7e0d0391df4efc7cb28557297eb2ec9904f1e5.= camel@redhat.com Cc: Maxim Levitsky Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index aba3f9d2ad02..60e6e82fe41f 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -1133,19 +1133,24 @@ void avic_vcpu_blocking(struct kvm_vcpu *vcpu) if (!kvm_vcpu_apicv_active(vcpu)) return; =20 - /* - * Unload the AVIC when the vCPU is about to block, _before_ - * the vCPU actually blocks. - * - * Any IRQs that arrive before IsRunning=3D0 will not cause an - * incomplete IPI vmexit on the source, therefore vIRR will also - * be checked by kvm_vcpu_check_block() before blocking. The - * memory barrier implicit in set_current_state orders writing - * IsRunning=3D0 before reading the vIRR. The processor needs a - * matching memory barrier on interrupt delivery between writing - * IRR and reading IsRunning; the lack of this barrier might be - * the cause of errata #1235). - */ + /* + * Unload the AVIC when the vCPU is about to block, _before_ the vCPU + * actually blocks. + * + * Note, any IRQs that arrive before IsRunning=3D0 will not cause an + * incomplete IPI vmexit on the source; kvm_vcpu_check_block() handles + * this by checking vIRR one last time before blocking. The memory + * barrier implicit in set_current_state orders writing IsRunning=3D0 + * before reading the vIRR. The processor needs a matching memory + * barrier on interrupt delivery between writing IRR and reading + * IsRunning; the lack of this barrier might be the cause of errata #1235= ). + * + * Clear IsRunning=3D0 even if guest IRQs are disabled, i.e. even if KVM + * doesn't need to detect events for scheduling purposes. The doorbell + * used to signal running vCPUs cannot be blocked, i.e. will perturb the + * CPU and cause noisy neighbor problems if the VM is sending interrupts + * to the vCPU while it's scheduled out. + */ avic_vcpu_put(vcpu); } =20 --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D1C522155F for ; Fri, 4 Apr 2025 19:40:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743795632; cv=none; b=Citjo8mFUjDrCl1RjkkBxJld8TRGd0olZkCpwK7wNX9ralmZ/10KHAKpnnpfnSkDq9ajIWGr+9aADhF9d8lE0WH1CVe1hZExYWflXSCBDyZtiv5L9ShGSnfK3eWXbQ7nJKAm7KJAewavTT3Jdc/BoYuzNRezMLpn15zspe/YrpU= ARC-Message-Signature: i=1; a=rsa-sha256; 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charset="utf-8" Use vcpu_data.pi_desc_addr instead of amd_iommu_pi_data.base to get the GA root pointer. KVM is the only source of amd_iommu_pi_data.base, and KVM's one and only path for writing amd_iommu_pi_data.base computes the exact same value for vcpu_data.pi_desc_addr and amd_iommu_pi_data.base, and fills amd_iommu_pi_data.base if and only if vcpu_data.pi_desc_addr is valid, i.e. amd_iommu_pi_data.base is fully redundant. Cc: Maxim Levitsky Reviewed-by: Joao Martins Signed-off-by: Sean Christopherson Reviewed-by: Vasant Hegde Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 7 +++++-- drivers/iommu/amd/iommu.c | 2 +- include/linux/amd-iommu.h | 1 - 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 60e6e82fe41f..9024b9fbca53 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -902,8 +902,11 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd= , struct kvm *kvm, =20 enable_remapped_mode =3D false; =20 - /* Try to enable guest_mode in IRTE */ - pi.base =3D avic_get_backing_page_address(svm); + /* + * Try to enable guest_mode in IRTE. Note, the address + * of the vCPU's AVIC backing page is passed to the + * IOMMU via vcpu_info->pi_desc_addr. + */ pi.ga_tag =3D AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id, svm->vcpu.vcpu_id); pi.is_guest_mode =3D true; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 4f69a37cf143..635774642b89 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3860,7 +3860,7 @@ static int amd_ir_set_vcpu_affinity(struct irq_data *= data, void *vcpu_info) =20 pi_data->prev_ga_tag =3D ir_data->cached_ga_tag; if (pi_data->is_guest_mode) { - ir_data->ga_root_ptr =3D (pi_data->base >> 12); + ir_data->ga_root_ptr =3D (vcpu_pi_info->pi_desc_addr >> 12); ir_data->ga_vector =3D vcpu_pi_info->vector; ir_data->ga_tag =3D pi_data->ga_tag; ret =3D amd_iommu_activate_guest_mode(ir_data); diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h index 062fbd4c9b77..4f433ef39188 100644 --- a/include/linux/amd-iommu.h +++ b/include/linux/amd-iommu.h @@ -20,7 +20,6 @@ struct amd_iommu; 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charset="utf-8" Delete the amd_ir_data.prev_ga_tag field now that all usage is superfluous. Signed-off-by: Sean Christopherson Reviewed-by: Vasant Hegde Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 2 -- drivers/iommu/amd/amd_iommu_types.h | 1 - drivers/iommu/amd/iommu.c | 10 ---------- include/linux/amd-iommu.h | 1 - 4 files changed, 14 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 9024b9fbca53..7f0f6a9cd2e8 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -943,9 +943,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, /** * Here, pi is used to: * - Tell IOMMU to use legacy mode for this interrupt. - * - Retrieve ga_tag of prior interrupt remapping data. */ - pi.prev_ga_tag =3D 0; pi.is_guest_mode =3D false; ret =3D irq_set_vcpu_affinity(host_irq, &pi); } else { diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 23caea22f8dc..319a1b650b3b 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -1060,7 +1060,6 @@ struct irq_2_irte { }; =20 struct amd_ir_data { - u32 cached_ga_tag; struct amd_iommu *iommu; struct irq_2_irte irq_2_irte; struct msi_msg msi_entry; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 635774642b89..3c40bc9980b7 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3858,23 +3858,13 @@ static int amd_ir_set_vcpu_affinity(struct irq_data= *data, void *vcpu_info) ir_data->cfg =3D irqd_cfg(data); pi_data->ir_data =3D ir_data; =20 - pi_data->prev_ga_tag =3D ir_data->cached_ga_tag; if (pi_data->is_guest_mode) { ir_data->ga_root_ptr =3D (vcpu_pi_info->pi_desc_addr >> 12); ir_data->ga_vector =3D vcpu_pi_info->vector; ir_data->ga_tag =3D pi_data->ga_tag; ret =3D amd_iommu_activate_guest_mode(ir_data); - if (!ret) - ir_data->cached_ga_tag =3D pi_data->ga_tag; } else { ret =3D amd_iommu_deactivate_guest_mode(ir_data); - - /* - * This communicates the ga_tag back to the caller - * so that it can do all the necessary clean up. - */ - if (!ret) - ir_data->cached_ga_tag =3D 0; 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charset="utf-8" Pass NULL to amd_ir_set_vcpu_affinity() to communicate "don't post to a vCPU" now that there's no need to communicate information back to KVM about the previous vCPU (KVM does its own tracking). Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 15 +++------------ drivers/iommu/amd/iommu.c | 10 +++++++--- 2 files changed, 10 insertions(+), 15 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 7f0f6a9cd2e8..9c789c288314 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -936,19 +936,10 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqf= d, struct kvm *kvm, } } =20 - if (enable_remapped_mode) { - /* Use legacy mode in IRTE */ - struct amd_iommu_pi_data pi; - - /** - * Here, pi is used to: - * - Tell IOMMU to use legacy mode for this interrupt. - */ - pi.is_guest_mode =3D false; - ret =3D irq_set_vcpu_affinity(host_irq, &pi); - } else { + if (enable_remapped_mode) + ret =3D irq_set_vcpu_affinity(host_irq, NULL); + else ret =3D 0; - } out: srcu_read_unlock(&kvm->irq_srcu, idx); return ret; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 3c40bc9980b7..08c4fa31da5d 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3835,7 +3835,6 @@ static int amd_ir_set_vcpu_affinity(struct irq_data *= data, void *vcpu_info) { int ret; struct amd_iommu_pi_data *pi_data =3D vcpu_info; - struct vcpu_data *vcpu_pi_info =3D pi_data->vcpu_data; struct amd_ir_data *ir_data =3D data->chip_data; struct irq_2_irte *irte_info =3D &ir_data->irq_2_irte; struct iommu_dev_data *dev_data; @@ -3856,9 +3855,14 @@ static int amd_ir_set_vcpu_affinity(struct irq_data = *data, void *vcpu_info) return -EINVAL; =20 ir_data->cfg =3D irqd_cfg(data); - pi_data->ir_data =3D ir_data; =20 - if (pi_data->is_guest_mode) { + if (pi_data) { + struct vcpu_data *vcpu_pi_info =3D pi_data->vcpu_data; + + pi_data->ir_data =3D ir_data; + + WARN_ON_ONCE(!pi_data->is_guest_mode); + ir_data->ga_root_ptr =3D (vcpu_pi_info->pi_desc_addr >> 12); ir_data->ga_vector =3D vcpu_pi_info->vector; ir_data->ga_tag =3D pi_data->ga_tag; --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 25F7922B8BF for ; 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Fri, 04 Apr 2025 12:40:35 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:43 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-29-seanjc@google.com> Subject: [PATCH 28/67] KVM: SVM: Get vCPU info for IRTE using new routing entry From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Explicitly get the vCPU information for a GSI routing entry from the new (or current) entry provided by common KVM. This is subtly a nop, as KVM allows at most one MSI per GSI, i.e. the for-loop can only ever process one entry, and that entry is the new/current entry. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 9c789c288314..eb6017b01c5f 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -855,7 +855,6 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e; struct kvm_irq_routing_table *irq_rt; bool enable_remapped_mode =3D true; - bool set =3D !!new; int idx, ret =3D 0; =20 if (!kvm_arch_has_assigned_device(kvm) || !kvm_arch_has_irq_bypass()) @@ -868,7 +867,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, svm_ir_list_del(irqfd); =20 pr_debug("SVM: %s: host_irq=3D%#x, guest_irq=3D%#x, set=3D%#x\n", - __func__, host_irq, guest_irq, set); + __func__, host_irq, guest_irq, !!new); =20 idx =3D srcu_read_lock(&kvm->irq_srcu); irq_rt =3D srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); @@ -896,7 +895,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, * 3. APIC virtualization is disabled for the vcpu. * 4. IRQ has incompatible delivery mode (SMI, INIT, etc) */ - if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set && + if (new && !get_pi_vcpu_info(kvm, new, &vcpu_info, &svm) && kvm_vcpu_apicv_active(&svm->vcpu)) { struct amd_iommu_pi_data pi; =20 @@ -927,7 +926,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, if (!ret && svm) { trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id, e->gsi, vcpu_info.vector, - vcpu_info.pi_desc_addr, set); + vcpu_info.pi_desc_addr, !!new); } =20 if (ret < 0) { --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 818F022C339 for ; Fri, 4 Apr 2025 19:40:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.201 ARC-Seal: i=1; a=rsa-sha256; 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Fri, 04 Apr 2025 12:40:37 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:44 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-30-seanjc@google.com> Subject: [PATCH 29/67] KVM: SVM: Stop walking list of routing table entries when updating IRTE From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that KVM SVM simply uses the provided routing entry, stop walking the routing table to find that entry. KVM, via setup_routing_entry() and sanity checked by kvm_get_msi_route(), disallows having a GSI configured to trigger multiple MSIs. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 106 ++++++++++++++++------------------------ 1 file changed, 43 insertions(+), 63 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index eb6017b01c5f..685a7b01194b 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -852,10 +852,10 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqf= d, struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, struct kvm_kernel_irq_routing_entry *new) { - struct kvm_kernel_irq_routing_entry *e; - struct kvm_irq_routing_table *irq_rt; bool enable_remapped_mode =3D true; - int idx, ret =3D 0; + struct vcpu_data vcpu_info; + struct vcpu_svm *svm =3D NULL; + int ret =3D 0; =20 if (!kvm_arch_has_assigned_device(kvm) || !kvm_arch_has_irq_bypass()) return 0; @@ -869,70 +869,51 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqf= d, struct kvm *kvm, pr_debug("SVM: %s: host_irq=3D%#x, guest_irq=3D%#x, set=3D%#x\n", __func__, host_irq, guest_irq, !!new); =20 - idx =3D srcu_read_lock(&kvm->irq_srcu); - irq_rt =3D srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); + /** + * Here, we setup with legacy mode in the following cases: + * 1. When cannot target interrupt to a specific vcpu. + * 2. Unsetting posted interrupt. + * 3. APIC virtualization is disabled for the vcpu. + * 4. IRQ has incompatible delivery mode (SMI, INIT, etc) + */ + if (new && new->type =3D=3D KVM_IRQ_ROUTING_MSI && + !get_pi_vcpu_info(kvm, new, &vcpu_info, &svm) && + kvm_vcpu_apicv_active(&svm->vcpu)) { + struct amd_iommu_pi_data pi; =20 - if (guest_irq >=3D irq_rt->nr_rt_entries || - hlist_empty(&irq_rt->map[guest_irq])) { - pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", - guest_irq, irq_rt->nr_rt_entries); - goto out; - } + enable_remapped_mode =3D false; =20 - hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { - struct vcpu_data vcpu_info; - struct vcpu_svm *svm =3D NULL; - - if (e->type !=3D KVM_IRQ_ROUTING_MSI) - continue; - - WARN_ON_ONCE(new && memcmp(e, new, sizeof(*new))); + /* + * Try to enable guest_mode in IRTE. Note, the address + * of the vCPU's AVIC backing page is passed to the + * IOMMU via vcpu_info->pi_desc_addr. + */ + pi.ga_tag =3D AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id, + svm->vcpu.vcpu_id); + pi.is_guest_mode =3D true; + pi.vcpu_data =3D &vcpu_info; + ret =3D irq_set_vcpu_affinity(host_irq, &pi); =20 /** - * Here, we setup with legacy mode in the following cases: - * 1. When cannot target interrupt to a specific vcpu. - * 2. Unsetting posted interrupt. - * 3. APIC virtualization is disabled for the vcpu. - * 4. IRQ has incompatible delivery mode (SMI, INIT, etc) + * Here, we successfully setting up vcpu affinity in + * IOMMU guest mode. Now, we need to store the posted + * interrupt information in a per-vcpu ir_list so that + * we can reference to them directly when we update vcpu + * scheduling information in IOMMU irte. */ - if (new && !get_pi_vcpu_info(kvm, new, &vcpu_info, &svm) && - kvm_vcpu_apicv_active(&svm->vcpu)) { - struct amd_iommu_pi_data pi; - - enable_remapped_mode =3D false; - - /* - * Try to enable guest_mode in IRTE. Note, the address - * of the vCPU's AVIC backing page is passed to the - * IOMMU via vcpu_info->pi_desc_addr. - */ - pi.ga_tag =3D AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id, - svm->vcpu.vcpu_id); - pi.is_guest_mode =3D true; - pi.vcpu_data =3D &vcpu_info; - ret =3D irq_set_vcpu_affinity(host_irq, &pi); - - /** - * Here, we successfully setting up vcpu affinity in - * IOMMU guest mode. Now, we need to store the posted - * interrupt information in a per-vcpu ir_list so that - * we can reference to them directly when we update vcpu - * scheduling information in IOMMU irte. - */ - if (!ret && pi.is_guest_mode) - svm_ir_list_add(svm, irqfd, &pi); - } - - if (!ret && svm) { - trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id, - e->gsi, vcpu_info.vector, - vcpu_info.pi_desc_addr, !!new); - } - - if (ret < 0) { - pr_err("%s: failed to update PI IRTE\n", __func__); - goto out; - } + if (!ret) + ret =3D svm_ir_list_add(svm, irqfd, &pi); + } + + if (!ret && svm) { + trace_kvm_pi_irte_update(host_irq, svm->vcpu.vcpu_id, + guest_irq, vcpu_info.vector, + vcpu_info.pi_desc_addr, !!new); + } + + if (ret < 0) { + pr_err("%s: failed to update PI IRTE\n", __func__); + goto out; } =20 if (enable_remapped_mode) @@ -940,7 +921,6 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, else ret =3D 0; out: - srcu_read_unlock(&kvm->irq_srcu, idx); return ret; } =20 --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4962F22D4C0 for ; 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Fri, 04 Apr 2025 12:40:38 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:45 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-31-seanjc@google.com> Subject: [PATCH 30/67] KVM: VMX: Stop walking list of routing table entries when updating IRTE From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that KVM provides the to-be-updated routing entry, stop walking the routing table to find that entry. KVM, via setup_routing_entry() and sanity checked by kvm_get_msi_route(), disallows having a GSI configured to trigger multiple MSIs, i.e. the for-loop can only process one entry. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/vmx/posted_intr.c | 100 +++++++++++---------------------- 1 file changed, 33 insertions(+), 67 deletions(-) diff --git a/arch/x86/kvm/vmx/posted_intr.c b/arch/x86/kvm/vmx/posted_intr.c index 00818ca30ee0..786912cee3f8 100644 --- a/arch/x86/kvm/vmx/posted_intr.c +++ b/arch/x86/kvm/vmx/posted_intr.c @@ -268,78 +268,44 @@ int vmx_pi_update_irte(struct kvm_kernel_irqfd *irqfd= , struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, struct kvm_kernel_irq_routing_entry *new) { - struct kvm_kernel_irq_routing_entry *e; - struct kvm_irq_routing_table *irq_rt; - bool enable_remapped_mode =3D true; struct kvm_lapic_irq irq; struct kvm_vcpu *vcpu; struct vcpu_data vcpu_info; - bool set =3D !!new; - int idx, ret =3D 0; =20 if (!vmx_can_use_vtd_pi(kvm)) return 0; =20 - idx =3D srcu_read_lock(&kvm->irq_srcu); - irq_rt =3D srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); - if (guest_irq >=3D irq_rt->nr_rt_entries || - hlist_empty(&irq_rt->map[guest_irq])) { - pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", - guest_irq, irq_rt->nr_rt_entries); - goto out; - } - - hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { - if (e->type !=3D KVM_IRQ_ROUTING_MSI) - continue; - - WARN_ON_ONCE(new && memcmp(e, new, sizeof(*new))); - - /* - * VT-d PI cannot support posting multicast/broadcast - * interrupts to a vCPU, we still use interrupt remapping - * for these kind of interrupts. - * - * For lowest-priority interrupts, we only support - * those with single CPU as the destination, e.g. user - * configures the interrupts via /proc/irq or uses - * irqbalance to make the interrupts single-CPU. - * - * We will support full lowest-priority interrupt later. - * - * In addition, we can only inject generic interrupts using - * the PI mechanism, refuse to route others through it. - */ - - kvm_set_msi_irq(kvm, e, &irq); - if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || - !kvm_irq_is_postable(&irq)) - continue; - - vcpu_info.pi_desc_addr =3D __pa(vcpu_to_pi_desc(vcpu)); - vcpu_info.vector =3D irq.vector; - - trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi, - vcpu_info.vector, vcpu_info.pi_desc_addr, set); - - if (!set) - continue; - - enable_remapped_mode =3D false; - - ret =3D irq_set_vcpu_affinity(host_irq, &vcpu_info); - if (ret < 0) { - printk(KERN_INFO "%s: failed to update PI IRTE\n", - __func__); - goto out; - } - } - - if (enable_remapped_mode) - ret =3D irq_set_vcpu_affinity(host_irq, NULL); - - ret =3D 0; -out: - srcu_read_unlock(&kvm->irq_srcu, idx); - return ret; + /* + * VT-d PI cannot support posting multicast/broadcast + * interrupts to a vCPU, we still use interrupt remapping + * for these kind of interrupts. + * + * For lowest-priority interrupts, we only support + * those with single CPU as the destination, e.g. user + * configures the interrupts via /proc/irq or uses + * irqbalance to make the interrupts single-CPU. + * + * We will support full lowest-priority interrupt later. + * + * In addition, we can only inject generic interrupts using + * the PI mechanism, refuse to route others through it. + */ + if (!new || new->type !=3D KVM_IRQ_ROUTING_MSI) + goto do_remapping; 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Fri, 04 Apr 2025 12:40:40 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:46 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-32-seanjc@google.com> Subject: [PATCH 31/67] KVM: SVM: Extract SVM specific code out of get_pi_vcpu_info() From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Genericize SVM's get_pi_vcpu_info() so that it can be shared with VMX. The only SVM specific information it provides is the AVIC back page, and that can be trivially retrieved by its sole caller. No functional change intended. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 685a7b01194b..ea6eae72b941 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -825,14 +825,14 @@ static int svm_ir_list_add(struct vcpu_svm *svm, */ static int get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, - struct vcpu_data *vcpu_info, struct vcpu_svm **svm) + struct vcpu_data *vcpu_info, struct kvm_vcpu **vcpu) { struct kvm_lapic_irq irq; - struct kvm_vcpu *vcpu =3D NULL; + *vcpu =3D NULL; =20 kvm_set_msi_irq(kvm, e, &irq); =20 - if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || + if (!kvm_intr_is_single_vcpu(kvm, &irq, vcpu) || !kvm_irq_is_postable(&irq)) { pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n", __func__, irq.vector); @@ -841,8 +841,6 @@ get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq= _routing_entry *e, =20 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__, irq.vector); - *svm =3D to_svm(vcpu); - vcpu_info->pi_desc_addr =3D avic_get_backing_page_address(*svm); vcpu_info->vector =3D irq.vector; =20 return 0; @@ -854,7 +852,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, { bool enable_remapped_mode =3D true; struct vcpu_data vcpu_info; - struct vcpu_svm *svm =3D NULL; + struct kvm_vcpu *vcpu =3D NULL; int ret =3D 0; =20 if (!kvm_arch_has_assigned_device(kvm) || !kvm_arch_has_irq_bypass()) @@ -876,20 +874,21 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqf= d, struct kvm *kvm, * 3. APIC virtualization is disabled for the vcpu. * 4. IRQ has incompatible delivery mode (SMI, INIT, etc) */ - if (new && new->type =3D=3D KVM_IRQ_ROUTING_MSI && - !get_pi_vcpu_info(kvm, new, &vcpu_info, &svm) && - kvm_vcpu_apicv_active(&svm->vcpu)) { + if (new && new && new->type =3D=3D KVM_IRQ_ROUTING_MSI && + !get_pi_vcpu_info(kvm, new, &vcpu_info, &vcpu) && + kvm_vcpu_apicv_active(vcpu)) { struct amd_iommu_pi_data pi; =20 enable_remapped_mode =3D false; =20 + vcpu_info.pi_desc_addr =3D avic_get_backing_page_address(to_svm(vcpu)); + /* * Try to enable guest_mode in IRTE. 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Fri, 04 Apr 2025 12:40:42 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:47 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-33-seanjc@google.com> Subject: [PATCH 32/67] KVM: x86: Nullify irqfd->producer after updating IRTEs From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Nullify irqfd->producer (when it's going away) _after_ updating IRTEs so that the producer can be queried during the update. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/x86.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 52d8d0635603..b8b259847d05 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -13608,7 +13608,6 @@ void kvm_arch_irq_bypass_del_producer(struct irq_by= pass_consumer *cons, * int this case doesn't want to receive the interrupts. */ spin_lock_irq(&kvm->irqfds.lock); - irqfd->producer =3D NULL; =20 if (irqfd->irq_entry.type =3D=3D KVM_IRQ_ROUTING_MSI) { ret =3D kvm_x86_call(pi_update_irte)(irqfd, irqfd->kvm, prod->irq, @@ -13617,6 +13616,7 @@ void kvm_arch_irq_bypass_del_producer(struct irq_by= pass_consumer *cons, pr_info("irq bypass consumer (token %p) unregistration fails: %d\n", irqfd->consumer.token, ret); } + irqfd->producer =3D NULL; =20 spin_unlock_irq(&kvm->irqfds.lock); =20 --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D194F22DF86 for ; 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Fri, 04 Apr 2025 12:40:44 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:48 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-34-seanjc@google.com> Subject: [PATCH 33/67] KVM: x86: Dedup AVIC vs. PI code for identifying target vCPU From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Hoist the logic for identifying the target vCPU for a posted interrupt into common x86. The code is functionally identical between Intel and AMD. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/include/asm/kvm_host.h | 3 +- arch/x86/kvm/svm/avic.c | 83 ++++++++------------------------- arch/x86/kvm/svm/svm.h | 3 +- arch/x86/kvm/vmx/posted_intr.c | 56 ++++++---------------- arch/x86/kvm/vmx/posted_intr.h | 3 +- arch/x86/kvm/x86.c | 46 +++++++++++++++--- 6 files changed, 81 insertions(+), 113 deletions(-) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index 85f45fc5156d..cb98d8d3c6c2 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1838,7 +1838,8 @@ struct kvm_x86_ops { =20 int (*pi_update_irte)(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, - struct kvm_kernel_irq_routing_entry *new); + struct kvm_kernel_irq_routing_entry *new, + struct kvm_vcpu *vcpu, u32 vector); void (*pi_start_assignment)(struct kvm *kvm); void (*apicv_pre_state_restore)(struct kvm_vcpu *vcpu); void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index ea6eae72b941..666f518340a7 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -812,52 +812,13 @@ static int svm_ir_list_add(struct vcpu_svm *svm, return 0; } =20 -/* - * Note: - * The HW cannot support posting multicast/broadcast - * interrupts to a vCPU. So, we still use legacy interrupt - * remapping for these kind of interrupts. - * - * For lowest-priority interrupts, we only support - * those with single CPU as the destination, e.g. user - * configures the interrupts via /proc/irq or uses - * irqbalance to make the interrupts single-CPU. - */ -static int -get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e, - struct vcpu_data *vcpu_info, struct kvm_vcpu **vcpu) -{ - struct kvm_lapic_irq irq; - *vcpu =3D NULL; - - kvm_set_msi_irq(kvm, e, &irq); - - if (!kvm_intr_is_single_vcpu(kvm, &irq, vcpu) || - !kvm_irq_is_postable(&irq)) { - pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n", - __func__, irq.vector); - return -1; - } - - pr_debug("SVM: %s: use GA mode for irq %u\n", __func__, - irq.vector); - vcpu_info->vector =3D irq.vector; - - return 0; -} - int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, - struct kvm_kernel_irq_routing_entry *new) + struct kvm_kernel_irq_routing_entry *new, + struct kvm_vcpu *vcpu, u32 vector) { - bool enable_remapped_mode =3D true; - struct vcpu_data vcpu_info; - struct kvm_vcpu *vcpu =3D NULL; int ret =3D 0; =20 - if (!kvm_arch_has_assigned_device(kvm) || !kvm_arch_has_irq_bypass()) - return 0; - /* * If the IRQ was affined to a different vCPU, remove the IRTE metadata * from the *previous* vCPU's list. @@ -865,7 +826,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, svm_ir_list_del(irqfd); =20 pr_debug("SVM: %s: host_irq=3D%#x, guest_irq=3D%#x, set=3D%#x\n", - __func__, host_irq, guest_irq, !!new); + __func__, host_irq, guest_irq, !!vcpu); =20 /** * Here, we setup with legacy mode in the following cases: @@ -874,23 +835,23 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqf= d, struct kvm *kvm, * 3. APIC virtualization is disabled for the vcpu. * 4. IRQ has incompatible delivery mode (SMI, INIT, etc) */ - if (new && new && new->type =3D=3D KVM_IRQ_ROUTING_MSI && - !get_pi_vcpu_info(kvm, new, &vcpu_info, &vcpu) && - kvm_vcpu_apicv_active(vcpu)) { - struct amd_iommu_pi_data pi; - - enable_remapped_mode =3D false; - - vcpu_info.pi_desc_addr =3D avic_get_backing_page_address(to_svm(vcpu)); - + if (vcpu && kvm_vcpu_apicv_active(vcpu)) { /* * Try to enable guest_mode in IRTE. Note, the address * of the vCPU's AVIC backing page is passed to the * IOMMU via vcpu_info->pi_desc_addr. */ - pi.ga_tag =3D AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id, vcpu->vcpu_id); - pi.is_guest_mode =3D true; - pi.vcpu_data =3D &vcpu_info; + struct vcpu_data vcpu_info =3D { + .pi_desc_addr =3D avic_get_backing_page_address(to_svm(vcpu)), + .vector =3D vector, + }; + + struct amd_iommu_pi_data pi =3D { + .ga_tag =3D AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id, vcpu->vcpu_id), + .is_guest_mode =3D true, + .vcpu_data =3D &vcpu_info, + }; + ret =3D irq_set_vcpu_affinity(host_irq, &pi); =20 /** @@ -902,12 +863,11 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqf= d, struct kvm *kvm, */ if (!ret) ret =3D svm_ir_list_add(to_svm(vcpu), irqfd, &pi); - } =20 - if (!ret && vcpu) { - trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, - guest_irq, vcpu_info.vector, - vcpu_info.pi_desc_addr, !!new); + trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, guest_irq, + vector, vcpu_info.pi_desc_addr, true); + } else { + ret =3D irq_set_vcpu_affinity(host_irq, NULL); } =20 if (ret < 0) { @@ -915,10 +875,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd= , struct kvm *kvm, goto out; } =20 - if (enable_remapped_mode) - ret =3D irq_set_vcpu_affinity(host_irq, NULL); - else - ret =3D 0; + ret =3D 0; out: return ret; } diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 6ad0aa86f78d..5ce240085ee0 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -741,7 +741,8 @@ void avic_apicv_post_state_restore(struct kvm_vcpu *vcp= u); void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu); int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, - struct kvm_kernel_irq_routing_entry *new); + struct kvm_kernel_irq_routing_entry *new, + struct kvm_vcpu *vcpu, u32 vector); void avic_vcpu_blocking(struct kvm_vcpu *vcpu); void avic_vcpu_unblocking(struct kvm_vcpu *vcpu); void avic_ring_doorbell(struct kvm_vcpu *vcpu); diff --git a/arch/x86/kvm/vmx/posted_intr.c b/arch/x86/kvm/vmx/posted_intr.c index 786912cee3f8..fd5f6a125614 100644 --- a/arch/x86/kvm/vmx/posted_intr.c +++ b/arch/x86/kvm/vmx/posted_intr.c @@ -266,46 +266,20 @@ void vmx_pi_start_assignment(struct kvm *kvm) =20 int vmx_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, - struct kvm_kernel_irq_routing_entry *new) + struct kvm_kernel_irq_routing_entry *new, + struct kvm_vcpu *vcpu, u32 vector) { - struct kvm_lapic_irq irq; - struct kvm_vcpu *vcpu; - struct vcpu_data vcpu_info; - - if (!vmx_can_use_vtd_pi(kvm)) - return 0; - - /* - * VT-d PI cannot support posting multicast/broadcast - * interrupts to a vCPU, we still use interrupt remapping - * for these kind of interrupts. - * - * For lowest-priority interrupts, we only support - * those with single CPU as the destination, e.g. user - * configures the interrupts via /proc/irq or uses - * irqbalance to make the interrupts single-CPU. - * - * We will support full lowest-priority interrupt later. - * - * In addition, we can only inject generic interrupts using - * the PI mechanism, refuse to route others through it. - */ - if (!new || new->type !=3D KVM_IRQ_ROUTING_MSI) - goto do_remapping; - - kvm_set_msi_irq(kvm, new, &irq); - - if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || - !kvm_irq_is_postable(&irq)) - goto do_remapping; - - vcpu_info.pi_desc_addr =3D __pa(vcpu_to_pi_desc(vcpu)); - vcpu_info.vector =3D irq.vector; - - trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, guest_irq, - vcpu_info.vector, vcpu_info.pi_desc_addr, true); - - return irq_set_vcpu_affinity(host_irq, &vcpu_info); -do_remapping: - return irq_set_vcpu_affinity(host_irq, NULL); + if (vcpu) { + struct vcpu_data vcpu_info =3D { + .pi_desc_addr =3D __pa(vcpu_to_pi_desc(vcpu)), + .vector =3D vector, + }; + + trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, guest_irq, + vcpu_info.vector, vcpu_info.pi_desc_addr, true); + + return irq_set_vcpu_affinity(host_irq, &vcpu_info); + } else { + return irq_set_vcpu_affinity(host_irq, NULL); + } } diff --git a/arch/x86/kvm/vmx/posted_intr.h b/arch/x86/kvm/vmx/posted_intr.h index a586d6aaf862..ee3e19e976ac 100644 --- a/arch/x86/kvm/vmx/posted_intr.h +++ b/arch/x86/kvm/vmx/posted_intr.h @@ -15,7 +15,8 @@ void __init pi_init_cpu(int cpu); bool pi_has_pending_interrupt(struct kvm_vcpu *vcpu); int vmx_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, - struct kvm_kernel_irq_routing_entry *new); + struct kvm_kernel_irq_routing_entry *new, + struct kvm_vcpu *vcpu, u32 vector); void vmx_pi_start_assignment(struct kvm *kvm); =20 static inline int pi_find_highest_vector(struct pi_desc *pi_desc) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index b8b259847d05..0ab818bba743 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -13567,6 +13567,43 @@ bool kvm_arch_has_irq_bypass(void) } EXPORT_SYMBOL_GPL(kvm_arch_has_irq_bypass); =20 +static int kvm_pi_update_irte(struct kvm_kernel_irqfd *irqfd, + struct kvm_kernel_irq_routing_entry *old, + struct kvm_kernel_irq_routing_entry *new) +{ + struct kvm *kvm =3D irqfd->kvm; + struct kvm_vcpu *vcpu =3D NULL; + struct kvm_lapic_irq irq; + + if (!irqchip_in_kernel(kvm) || + !kvm_arch_has_irq_bypass() || + !kvm_arch_has_assigned_device(kvm)) + return 0; + + if (new && new->type =3D=3D KVM_IRQ_ROUTING_MSI) { + kvm_set_msi_irq(kvm, new, &irq); + + /* + * Force remapped mode if hardware doesn't support posting the + * virtual interrupt to a vCPU. Only IRQs are postable (NMIs, + * SMIs, etc. are not), and neither AMD nor Intel IOMMUs support + * posting multicast/broadcast IRQs. If the interrupt can't be + * posted, the device MSI needs to be routed to the host so that + * the guest's desired interrupt can be synthesized by KVM. + * + * This means that KVM can only post lowest-priority interrupts + * if they have a single CPU as the destination, e.g. only if + * the guest has affined the interrupt to a single vCPU. + */ + if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || + !kvm_irq_is_postable(&irq)) + vcpu =3D NULL; + } + + return kvm_x86_call(pi_update_irte)(irqfd, irqfd->kvm, irqfd->producer->i= rq, + irqfd->gsi, new, vcpu, irq.vector); +} + int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, struct irq_bypass_producer *prod) { @@ -13581,8 +13618,7 @@ int kvm_arch_irq_bypass_add_producer(struct irq_byp= ass_consumer *cons, irqfd->producer =3D prod; =20 if (irqfd->irq_entry.type =3D=3D KVM_IRQ_ROUTING_MSI) { - ret =3D kvm_x86_call(pi_update_irte)(irqfd, irqfd->kvm, prod->irq, - irqfd->gsi, &irqfd->irq_entry); + ret =3D kvm_pi_update_irte(irqfd, NULL, &irqfd->irq_entry); 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Fri, 04 Apr 2025 12:40:45 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:49 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-35-seanjc@google.com> Subject: [PATCH 34/67] KVM: x86: Move posted interrupt tracepoint to common code From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move the pi_irte_update tracepoint to common x86, and call it whenever the IRTE is modified. Tracing only the modifications that result in an IRQ being posted to a vCPU makes the tracepoint useless for debugging. Drop the vendor specific address; plumbing that into common code isn't worth the trouble, as the address is meaningless without a whole pile of other information that isn't provided in any tracepoint. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 6 ------ arch/x86/kvm/trace.h | 19 +++++++------------ arch/x86/kvm/vmx/posted_intr.c | 3 --- arch/x86/kvm/x86.c | 12 +++++++++--- 4 files changed, 16 insertions(+), 24 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 666f518340a7..dcfe908f5b98 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -825,9 +825,6 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, */ svm_ir_list_del(irqfd); =20 - pr_debug("SVM: %s: host_irq=3D%#x, guest_irq=3D%#x, set=3D%#x\n", - __func__, host_irq, guest_irq, !!vcpu); - /** * Here, we setup with legacy mode in the following cases: * 1. When cannot target interrupt to a specific vcpu. @@ -863,9 +860,6 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, */ if (!ret) ret =3D svm_ir_list_add(to_svm(vcpu), irqfd, &pi); - - trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, guest_irq, - vector, vcpu_info.pi_desc_addr, true); } else { ret =3D irq_set_vcpu_affinity(host_irq, NULL); } diff --git a/arch/x86/kvm/trace.h b/arch/x86/kvm/trace.h index ccda95e53f62..be4f55c23ec7 100644 --- a/arch/x86/kvm/trace.h +++ b/arch/x86/kvm/trace.h @@ -1089,37 +1089,32 @@ TRACE_EVENT(kvm_smm_transition, * Tracepoint for VT-d posted-interrupts and AMD-Vi Guest Virtual APIC. */ TRACE_EVENT(kvm_pi_irte_update, - TP_PROTO(unsigned int host_irq, unsigned int vcpu_id, - unsigned int gsi, unsigned int gvec, - u64 pi_desc_addr, bool set), - TP_ARGS(host_irq, vcpu_id, gsi, gvec, pi_desc_addr, set), + TP_PROTO(unsigned int host_irq, struct kvm_vcpu *vcpu, + unsigned int gsi, unsigned int gvec, bool set), + TP_ARGS(host_irq, vcpu, gsi, gvec, set), =20 TP_STRUCT__entry( __field( unsigned int, host_irq ) - __field( unsigned int, vcpu_id ) + __field( int, vcpu_id ) __field( unsigned int, gsi ) __field( unsigned int, gvec ) - __field( u64, pi_desc_addr ) __field( bool, set ) ), =20 TP_fast_assign( __entry->host_irq =3D host_irq; - __entry->vcpu_id =3D vcpu_id; + __entry->vcpu_id =3D vcpu ? vcpu->vcpu_id : -1; __entry->gsi =3D gsi; __entry->gvec =3D gvec; - __entry->pi_desc_addr =3D pi_desc_addr; __entry->set =3D set; ), =20 - TP_printk("PI is %s for irq %u, vcpu %u, gsi: 0x%x, " - "gvec: 0x%x, pi_desc_addr: 0x%llx", + TP_printk("PI is %s for irq %u, vcpu %d, gsi: 0x%x, gvec: 0x%x", __entry->set ? "enabled and being updated" : "disabled", __entry->host_irq, __entry->vcpu_id, __entry->gsi, - __entry->gvec, - __entry->pi_desc_addr) + __entry->gvec) ); =20 /* diff --git a/arch/x86/kvm/vmx/posted_intr.c b/arch/x86/kvm/vmx/posted_intr.c index fd5f6a125614..baf627839498 100644 --- a/arch/x86/kvm/vmx/posted_intr.c +++ b/arch/x86/kvm/vmx/posted_intr.c @@ -275,9 +275,6 @@ int vmx_pi_update_irte(struct kvm_kernel_irqfd *irqfd, = struct kvm *kvm, .vector =3D vector, }; =20 - trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, guest_irq, - vcpu_info.vector, vcpu_info.pi_desc_addr, true); - return irq_set_vcpu_affinity(host_irq, &vcpu_info); } else { return irq_set_vcpu_affinity(host_irq, NULL); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 0ab818bba743..a20d461718cc 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -13571,9 +13571,11 @@ static int kvm_pi_update_irte(struct kvm_kernel_ir= qfd *irqfd, struct kvm_kernel_irq_routing_entry *old, struct kvm_kernel_irq_routing_entry *new) { + unsigned int host_irq =3D irqfd->producer->irq; struct kvm *kvm =3D irqfd->kvm; struct kvm_vcpu *vcpu =3D NULL; struct kvm_lapic_irq irq; + int r; =20 if (!irqchip_in_kernel(kvm) || !kvm_arch_has_irq_bypass() || @@ -13600,8 +13602,13 @@ static int kvm_pi_update_irte(struct kvm_kernel_ir= qfd *irqfd, vcpu =3D NULL; } =20 - return kvm_x86_call(pi_update_irte)(irqfd, irqfd->kvm, irqfd->producer->i= rq, - irqfd->gsi, new, vcpu, irq.vector); + r =3D kvm_x86_call(pi_update_irte)(irqfd, irqfd->kvm, host_irq, irqfd->gs= i, + new, vcpu, irq.vector); + if (r) + return r; + + trace_kvm_pi_irte_update(host_irq, vcpu, irqfd->gsi, irq.vector, !!vcpu); + return 0; } =20 int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons, @@ -14074,7 +14081,6 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts); EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset); EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window_update); EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full); -EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update); EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access); 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charset="utf-8" Clean up the return paths for avic_pi_update_irte() now that the refactoring dust has settled. Opportunistically drop the pr_err() on IRTE update failures. Logging that a failure occurred without _any_ context is quite useless. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 20 +++++--------------- 1 file changed, 5 insertions(+), 15 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index dcfe908f5b98..4382ab2eaea6 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -817,8 +817,6 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, struct kvm_kernel_irq_routing_entry *new, struct kvm_vcpu *vcpu, u32 vector) { - int ret =3D 0; - /* * If the IRQ was affined to a different vCPU, remove the IRTE metadata * from the *previous* vCPU's list. @@ -848,8 +846,11 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd= , struct kvm *kvm, .is_guest_mode =3D true, .vcpu_data =3D &vcpu_info, }; + int ret; =20 ret =3D irq_set_vcpu_affinity(host_irq, &pi); + if (ret) + return ret; =20 /** * Here, we successfully setting up vcpu affinity in @@ -858,20 +859,9 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd= , struct kvm *kvm, * we can reference to them directly when we update vcpu * scheduling information in IOMMU irte. */ - if (!ret) - ret =3D svm_ir_list_add(to_svm(vcpu), irqfd, &pi); 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charset="utf-8" Split the vcpu_data structure that serves as a handoff from KVM to IOMMU drivers into vendor specific structures. Overloading a single structure makes the code hard to read and maintain, is *very* misleading as it suggests that mixing vendors is actually supported, and bastardizing Intel's posted interrupt descriptor address when AMD's IOMMU already has its own structure is quite unnecessary. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/include/asm/irq_remapping.h | 15 ++++++++++++++- arch/x86/kvm/svm/avic.c | 21 ++++++++------------- arch/x86/kvm/vmx/posted_intr.c | 4 ++-- drivers/iommu/amd/iommu.c | 12 ++++-------- drivers/iommu/intel/irq_remapping.c | 10 +++++----- include/linux/amd-iommu.h | 12 ------------ 6 files changed, 33 insertions(+), 41 deletions(-) diff --git a/arch/x86/include/asm/irq_remapping.h b/arch/x86/include/asm/ir= q_remapping.h index 5036f13ab69f..2dbc9cb61c2f 100644 --- a/arch/x86/include/asm/irq_remapping.h +++ b/arch/x86/include/asm/irq_remapping.h @@ -26,7 +26,20 @@ enum { IRQ_REMAP_X2APIC_MODE, }; =20 -struct vcpu_data { +/* + * This is mainly used to communicate information back-and-forth + * between SVM and IOMMU for setting up and tearing down posted + * interrupt + */ +struct amd_iommu_pi_data { + u64 vapic_addr; /* Physical address of the vCPU's vAPIC. */ + u32 ga_tag; + u32 vector; /* Guest vector of the interrupt */ + bool is_guest_mode; + void *ir_data; +}; + +struct intel_iommu_pi_data { u64 pi_desc_addr; /* Physical address of PI Descriptor */ u32 vector; /* Guest vector of the interrupt */ }; diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 4382ab2eaea6..355673f95b70 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -832,23 +832,18 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqf= d, struct kvm *kvm, */ if (vcpu && kvm_vcpu_apicv_active(vcpu)) { /* - * Try to enable guest_mode in IRTE. Note, the address - * of the vCPU's AVIC backing page is passed to the - * IOMMU via vcpu_info->pi_desc_addr. + * Try to enable guest_mode in IRTE. */ - struct vcpu_data vcpu_info =3D { - .pi_desc_addr =3D avic_get_backing_page_address(to_svm(vcpu)), - .vector =3D vector, - }; - - struct amd_iommu_pi_data pi =3D { - .ga_tag =3D AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id, vcpu->vcpu_id), + struct amd_iommu_pi_data pi_data =3D { + .ga_tag =3D AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id, + vcpu->vcpu_id), .is_guest_mode =3D true, - .vcpu_data =3D &vcpu_info, + .vapic_addr =3D avic_get_backing_page_address(to_svm(vcpu)), + .vector =3D vector, }; int ret; =20 - ret =3D irq_set_vcpu_affinity(host_irq, &pi); + ret =3D irq_set_vcpu_affinity(host_irq, &pi_data); if (ret) return ret; =20 @@ -859,7 +854,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, * we can reference to them directly when we update vcpu * scheduling information in IOMMU irte. */ - return svm_ir_list_add(to_svm(vcpu), irqfd, &pi); + return svm_ir_list_add(to_svm(vcpu), irqfd, &pi_data); } return irq_set_vcpu_affinity(host_irq, NULL); } diff --git a/arch/x86/kvm/vmx/posted_intr.c b/arch/x86/kvm/vmx/posted_intr.c index baf627839498..2958b631fde8 100644 --- a/arch/x86/kvm/vmx/posted_intr.c +++ b/arch/x86/kvm/vmx/posted_intr.c @@ -270,12 +270,12 @@ int vmx_pi_update_irte(struct kvm_kernel_irqfd *irqfd= , struct kvm *kvm, struct kvm_vcpu *vcpu, u32 vector) { if (vcpu) { - struct vcpu_data vcpu_info =3D { + struct intel_iommu_pi_data pi_data =3D { .pi_desc_addr =3D __pa(vcpu_to_pi_desc(vcpu)), .vector =3D vector, }; =20 - return irq_set_vcpu_affinity(host_irq, &vcpu_info); + return irq_set_vcpu_affinity(host_irq, &pi_data); } else { return irq_set_vcpu_affinity(host_irq, NULL); } diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 08c4fa31da5d..bc6f7eb2f04b 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3831,10 +3831,10 @@ int amd_iommu_deactivate_guest_mode(void *data) } EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode); =20 -static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info) +static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *info) { int ret; - struct amd_iommu_pi_data *pi_data =3D vcpu_info; + struct amd_iommu_pi_data *pi_data =3D info; struct amd_ir_data *ir_data =3D data->chip_data; struct irq_2_irte *irte_info =3D &ir_data->irq_2_irte; struct iommu_dev_data *dev_data; @@ -3857,14 +3857,10 @@ static int amd_ir_set_vcpu_affinity(struct irq_data= *data, void *vcpu_info) ir_data->cfg =3D irqd_cfg(data); =20 if (pi_data) { - struct vcpu_data *vcpu_pi_info =3D pi_data->vcpu_data; - pi_data->ir_data =3D ir_data; =20 - WARN_ON_ONCE(!pi_data->is_guest_mode); - - ir_data->ga_root_ptr =3D (vcpu_pi_info->pi_desc_addr >> 12); - ir_data->ga_vector =3D vcpu_pi_info->vector; + ir_data->ga_root_ptr =3D (pi_data->vapic_addr >> 12); + ir_data->ga_vector =3D pi_data->vector; ir_data->ga_tag =3D pi_data->ga_tag; ret =3D amd_iommu_activate_guest_mode(ir_data); } else { diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_= remapping.c index ad795c772f21..8ccec30e5f45 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -1236,10 +1236,10 @@ static void intel_ir_compose_msi_msg(struct irq_dat= a *irq_data, static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info) { struct intel_ir_data *ir_data =3D data->chip_data; - struct vcpu_data *vcpu_pi_info =3D info; + struct intel_iommu_pi_data *pi_data =3D info; =20 /* stop posting interrupts, back to the default mode */ - if (!vcpu_pi_info) { + if (!pi_data) { modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry); } else { struct irte irte_pi; @@ -1257,10 +1257,10 @@ static int intel_ir_set_vcpu_affinity(struct irq_da= ta *data, void *info) /* Update the posted mode fields */ irte_pi.p_pst =3D 1; irte_pi.p_urgent =3D 0; - irte_pi.p_vector =3D vcpu_pi_info->vector; - irte_pi.pda_l =3D (vcpu_pi_info->pi_desc_addr >> + irte_pi.p_vector =3D pi_data->vector; + irte_pi.pda_l =3D (pi_data->pi_desc_addr >> (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT); - irte_pi.pda_h =3D (vcpu_pi_info->pi_desc_addr >> 32) & + irte_pi.pda_h =3D (pi_data->pi_desc_addr >> 32) & ~(-1UL << PDA_HIGH_BIT); =20 modify_irte(&ir_data->irq_2_iommu, &irte_pi); diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h index deeefc92a5cf..99b4fa9a0296 100644 --- a/include/linux/amd-iommu.h +++ b/include/linux/amd-iommu.h @@ -12,18 +12,6 @@ =20 struct amd_iommu; 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charset="utf-8" Don't bother WARNing if updating an IRTE route fails now that vendor code provides much more precise WARNs. The generic WARN doesn't provide enough information to actually debug the problem, and has obviously done nothing to surface the myriad bugs in KVM's implementation. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/x86.c | 8 ++++---- include/linux/kvm_host.h | 6 +++--- virt/kvm/eventfd.c | 15 ++++++--------- 3 files changed, 13 insertions(+), 16 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index a20d461718cc..c2c102f23fa7 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -13666,11 +13666,11 @@ void kvm_arch_irq_bypass_del_producer(struct irq_= bypass_consumer *cons, kvm_arch_end_assignment(irqfd->kvm); } =20 -int kvm_arch_update_irqfd_routing(struct kvm_kernel_irqfd *irqfd, - struct kvm_kernel_irq_routing_entry *old, - struct kvm_kernel_irq_routing_entry *new) +void kvm_arch_update_irqfd_routing(struct kvm_kernel_irqfd *irqfd, + struct kvm_kernel_irq_routing_entry *old, + struct kvm_kernel_irq_routing_entry *new) { - return kvm_pi_update_irte(irqfd, old, new); + kvm_pi_update_irte(irqfd, old, new); } =20 bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old, diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index 2d9f3aeb766a..7e8f5cb4fc9a 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -2392,9 +2392,9 @@ void kvm_arch_irq_bypass_del_producer(struct irq_bypa= ss_consumer *, struct irq_bypass_producer *); void kvm_arch_irq_bypass_stop(struct irq_bypass_consumer *); void kvm_arch_irq_bypass_start(struct irq_bypass_consumer *); -int kvm_arch_update_irqfd_routing(struct kvm_kernel_irqfd *irqfd, - struct kvm_kernel_irq_routing_entry *old, - struct kvm_kernel_irq_routing_entry *new); +void kvm_arch_update_irqfd_routing(struct kvm_kernel_irqfd *irqfd, + struct kvm_kernel_irq_routing_entry *old, + struct kvm_kernel_irq_routing_entry *new); bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *, struct kvm_kernel_irq_routing_entry *); #endif /* CONFIG_HAVE_KVM_IRQ_BYPASS */ diff --git a/virt/kvm/eventfd.c b/virt/kvm/eventfd.c index ad71e3e4d1c3..7ccdaa4071c8 100644 --- a/virt/kvm/eventfd.c +++ b/virt/kvm/eventfd.c @@ -285,11 +285,11 @@ void __attribute__((weak)) kvm_arch_irq_bypass_start( { } =20 -int __weak kvm_arch_update_irqfd_routing(struct kvm_kernel_irqfd *irqfd, - struct kvm_kernel_irq_routing_entry *old, - struct kvm_kernel_irq_routing_entry *new) +void __weak kvm_arch_update_irqfd_routing(struct kvm_kernel_irqfd *irqfd, + struct kvm_kernel_irq_routing_entry *old, + struct kvm_kernel_irq_routing_entry *new) { - return 0; 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Fri, 04 Apr 2025 12:40:52 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:53 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-39-seanjc@google.com> Subject: [PATCH 38/67] KVM: Fold kvm_arch_irqfd_route_changed() into kvm_arch_update_irqfd_routing() From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fold kvm_arch_irqfd_route_changed() into kvm_arch_update_irqfd_routing(). Calling arch code to know whether or not to call arch code is absurd. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/x86.c | 15 +++++---------- include/linux/kvm_host.h | 2 -- virt/kvm/eventfd.c | 10 +--------- 3 files changed, 6 insertions(+), 21 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index c2c102f23fa7..36d4a9ed144d 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -13670,19 +13670,14 @@ void kvm_arch_update_irqfd_routing(struct kvm_ker= nel_irqfd *irqfd, struct kvm_kernel_irq_routing_entry *old, struct kvm_kernel_irq_routing_entry *new) { + if (old->type =3D=3D KVM_IRQ_ROUTING_MSI && + new->type =3D=3D KVM_IRQ_ROUTING_MSI && + !memcmp(&old->msi, &new->msi, sizeof(new->msi))) + return; + kvm_pi_update_irte(irqfd, old, new); } =20 -bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *old, - struct kvm_kernel_irq_routing_entry *new) -{ - if (old->type !=3D KVM_IRQ_ROUTING_MSI || - new->type !=3D KVM_IRQ_ROUTING_MSI) - return true; - - return !!memcmp(&old->msi, &new->msi, sizeof(new->msi)); -} - bool kvm_vector_hashing_enabled(void) { return vector_hashing; diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index 7e8f5cb4fc9a..d1a41c40ae79 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -2395,8 +2395,6 @@ void kvm_arch_irq_bypass_start(struct irq_bypass_cons= umer *); void kvm_arch_update_irqfd_routing(struct kvm_kernel_irqfd *irqfd, struct kvm_kernel_irq_routing_entry *old, struct kvm_kernel_irq_routing_entry *new); -bool kvm_arch_irqfd_route_changed(struct kvm_kernel_irq_routing_entry *, - struct kvm_kernel_irq_routing_entry *); #endif /* CONFIG_HAVE_KVM_IRQ_BYPASS */ =20 #ifdef CONFIG_HAVE_KVM_INVALID_WAKEUPS diff --git a/virt/kvm/eventfd.c b/virt/kvm/eventfd.c index 7ccdaa4071c8..b9810c3654f5 100644 --- a/virt/kvm/eventfd.c +++ b/virt/kvm/eventfd.c @@ -291,13 +291,6 @@ void __weak kvm_arch_update_irqfd_routing(struct kvm_k= ernel_irqfd *irqfd, { =20 } - -bool __attribute__((weak)) kvm_arch_irqfd_route_changed( - struct kvm_kernel_irq_routing_entry *old, - struct kvm_kernel_irq_routing_entry *new) -{ - return true; -} #endif =20 static int @@ -617,8 +610,7 @@ void kvm_irq_routing_update(struct kvm *kvm) irqfd_update(kvm, irqfd); =20 #ifdef CONFIG_HAVE_KVM_IRQ_BYPASS - if (irqfd->producer && - kvm_arch_irqfd_route_changed(&old, &irqfd->irq_entry)) + if (irqfd->producer) kvm_arch_update_irqfd_routing(irqfd, &old, &irqfd->irq_entry); #endif } --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pj1-f74.google.com (mail-pj1-f74.google.com [209.85.216.74]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAE16230BCC for ; Fri, 4 Apr 2025 19:40:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.74 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743795656; cv=none; b=TGXUBm6tNsIVbeFYuAMrKNldhuvqoSc4xlS9v7/leKart87/sFur1yxAe9ESYIb9pohrgMt+pvYf8vUiS77O3aTM2ZeaO05LGLVlS2N4TgHaZ51bfgDOGPbtbJuBkN9JHwaMmi/PW5NYImuvuH2C4LJOAQcivToULgsvuy/X4So= ARC-Message-Signature: i=1; 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charset="utf-8" Track the vCPU that is being targeted for IRQ bypass, a.k.a. for a posted IRQ, in common x86 code. This will allow for additional consolidation of the SVM and VMX code. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 4 ---- arch/x86/kvm/x86.c | 7 ++++++- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 355673f95b70..bd1fcf2ea1e5 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -776,22 +776,18 @@ static void svm_ir_list_del(struct kvm_kernel_irqfd *= irqfd) spin_lock_irqsave(&to_svm(vcpu)->ir_list_lock, flags); list_del(&irqfd->vcpu_list); spin_unlock_irqrestore(&to_svm(vcpu)->ir_list_lock, flags); - - irqfd->irq_bypass_vcpu =3D NULL; } =20 static int svm_ir_list_add(struct vcpu_svm *svm, struct kvm_kernel_irqfd *irqfd, struct amd_iommu_pi_data *pi) { - struct kvm_vcpu *vcpu =3D &svm->vcpu; unsigned long flags; u64 entry; =20 if (WARN_ON_ONCE(!pi->ir_data)) return -EINVAL; =20 - irqfd->irq_bypass_vcpu =3D vcpu; irqfd->irq_bypass_data =3D pi->ir_data; =20 spin_lock_irqsave(&svm->ir_list_lock, flags); diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 36d4a9ed144d..0d9bd8535f61 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -13604,8 +13604,13 @@ static int kvm_pi_update_irte(struct kvm_kernel_ir= qfd *irqfd, =20 r =3D kvm_x86_call(pi_update_irte)(irqfd, irqfd->kvm, host_irq, irqfd->gs= i, new, vcpu, irq.vector); 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charset="utf-8" Don't "reconfigure" an IRTE into host controlled mode when it's already in the state, i.e. if KVM's GSI routing changes but the IRQ wasn't and still isn't being posted to a vCPU. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/x86.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 0d9bd8535f61..8325a908fa25 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -13602,6 +13602,9 @@ static int kvm_pi_update_irte(struct kvm_kernel_irq= fd *irqfd, vcpu =3D NULL; } =20 + if (!irqfd->irq_bypass_vcpu && !vcpu) + return 0; + r =3D kvm_x86_call(pi_update_irte)(irqfd, irqfd->kvm, host_irq, irqfd->gs= i, new, vcpu, irq.vector); if (r) { --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pg1-f201.google.com (mail-pg1-f201.google.com [209.85.215.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F26C923496B for ; Fri, 4 Apr 2025 19:40:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.201 ARC-Seal: i=1; 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Fri, 04 Apr 2025 12:40:57 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:56 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-42-seanjc@google.com> Subject: [PATCH 41/67] KVM: x86: Don't update IRTE entries when old and new routes were !MSI From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Skip the entirety of IRTE updates on a GSI routing change if neither the old nor the new routing is for an MSI, i.e. if the neither routing setup allows for posting to a vCPU. If the IRTE isn't already host controlled, KVM has bigger problems. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/x86.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 8325a908fa25..0dc3b45cb664 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -13678,6 +13678,10 @@ void kvm_arch_update_irqfd_routing(struct kvm_kern= el_irqfd *irqfd, struct kvm_kernel_irq_routing_entry *old, struct kvm_kernel_irq_routing_entry *new) { + if (new->type !=3D KVM_IRQ_ROUTING_MSI && + old->type !=3D KVM_IRQ_ROUTING_MSI) + return; + if (old->type =3D=3D KVM_IRQ_ROUTING_MSI && new->type =3D=3D KVM_IRQ_ROUTING_MSI && !memcmp(&old->msi, &new->msi, sizeof(new->msi))) --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1D4323718D for ; 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Fri, 04 Apr 2025 12:40:59 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:38:57 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-43-seanjc@google.com> Subject: [PATCH 42/67] KVM: SVM: Revert IRTE to legacy mode if IOMMU doesn't provide IR metadata From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Revert the IRTE back to remapping mode if the AMD IOMMU driver mucks up and doesn't provide the necessary metadata. Returning an error up the stack without actually handling the error is useless and confusing. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 23 +++++++++++++++-------- 1 file changed, 15 insertions(+), 8 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index bd1fcf2ea1e5..22fa49fc9717 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -778,16 +778,13 @@ static void svm_ir_list_del(struct kvm_kernel_irqfd *= irqfd) spin_unlock_irqrestore(&to_svm(vcpu)->ir_list_lock, flags); } =20 -static int svm_ir_list_add(struct vcpu_svm *svm, - struct kvm_kernel_irqfd *irqfd, - struct amd_iommu_pi_data *pi) +static void svm_ir_list_add(struct vcpu_svm *svm, + struct kvm_kernel_irqfd *irqfd, + struct amd_iommu_pi_data *pi) { unsigned long flags; u64 entry; =20 - if (WARN_ON_ONCE(!pi->ir_data)) - return -EINVAL; - irqfd->irq_bypass_data =3D pi->ir_data; =20 spin_lock_irqsave(&svm->ir_list_lock, flags); @@ -805,7 +802,6 @@ static int svm_ir_list_add(struct vcpu_svm *svm, =20 list_add(&irqfd->vcpu_list, &svm->ir_list); spin_unlock_irqrestore(&svm->ir_list_lock, flags); - return 0; } =20 int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, @@ -843,6 +839,16 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd= , struct kvm *kvm, if (ret) return ret; =20 + /* + * Revert to legacy mode if the IOMMU didn't provide metadata + * for the IRTE, which KVM needs to keep the IRTE up-to-date, + * e.g. if the vCPU is migrated or AVIC is disabled. + */ + if (WARN_ON_ONCE(!pi_data.ir_data)) { + irq_set_vcpu_affinity(host_irq, NULL); + return -EIO; + } + /** * Here, we successfully setting up vcpu affinity in * IOMMU guest mode. Now, we need to store the posted @@ -850,7 +856,8 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, * we can reference to them directly when we update vcpu * scheduling information in IOMMU irte. */ - return svm_ir_list_add(to_svm(vcpu), irqfd, &pi_data); + svm_ir_list_add(to_svm(vcpu), irqfd, &pi_data); + return 0; } return irq_set_vcpu_affinity(host_irq, NULL); } --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A394238D27 for ; Fri, 4 Apr 2025 19:41:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743795664; cv=none; b=N61dsTXlRVM1f81apCFhqcEBoPerkv8ST6BTBSKQwErSoDCHsi7dZxLN4cqfvNnYq7DQHv5Ty9QZGwAAXt0SzS+etRm/PS3KGyUI2cyC98zIj4MAT4H8Objm1+H/AVrCjxcwzVIj2XvVWhff1bWeZbjCmSkole8MWolil6xCnkI= ARC-Message-Signature: i=1; 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charset="utf-8" Now that svm_ir_list_add() isn't overloaded with all manner of weird things, fold it into avic_pi_update_irte(), and more importantly take ir_list_lock across the irq_set_vcpu_affinity() calls to ensure the info that's shoved into the IRTE is fresh. While preemption (and IRQs) is disabled on the task performing the IRTE update, thanks to irqfds.lock, that task doesn't hold the vCPU's mutex, i.e. preemption being disabled is irrelevant. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 55 +++++++++++++++++------------------------ 1 file changed, 22 insertions(+), 33 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 22fa49fc9717..4dbbb5a6cacc 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -778,32 +778,6 @@ static void svm_ir_list_del(struct kvm_kernel_irqfd *i= rqfd) spin_unlock_irqrestore(&to_svm(vcpu)->ir_list_lock, flags); } =20 -static void svm_ir_list_add(struct vcpu_svm *svm, - struct kvm_kernel_irqfd *irqfd, - struct amd_iommu_pi_data *pi) -{ - unsigned long flags; - u64 entry; - - irqfd->irq_bypass_data =3D pi->ir_data; - - spin_lock_irqsave(&svm->ir_list_lock, flags); - - /* - * Update the target pCPU for IOMMU doorbells if the vCPU is running. - * If the vCPU is NOT running, i.e. is blocking or scheduled out, KVM - * will update the pCPU info when the vCPU awkened and/or scheduled in. - * See also avic_vcpu_load(). - */ - entry =3D svm->avic_physical_id_entry; - if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) - amd_iommu_update_ga(entry & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK, - true, pi->ir_data); - - list_add(&irqfd->vcpu_list, &svm->ir_list); - spin_unlock_irqrestore(&svm->ir_list_lock, flags); -} - int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, struct kvm_kernel_irq_routing_entry *new, @@ -833,8 +807,18 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd= , struct kvm *kvm, .vapic_addr =3D avic_get_backing_page_address(to_svm(vcpu)), .vector =3D vector, }; + struct vcpu_svm *svm =3D to_svm(vcpu); + u64 entry; int ret; =20 + /* + * Prevent the vCPU from being scheduled out or migrated until + * the IRTE is updated and its metadata has been added to the + * list of IRQs being posted to the vCPU, to ensure the IRTE + * isn't programmed with stale pCPU/IsRunning information. + */ + guard(spinlock_irqsave)(&svm->ir_list_lock); + ret =3D irq_set_vcpu_affinity(host_irq, &pi_data); if (ret) return ret; @@ -849,14 +833,19 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqf= d, struct kvm *kvm, return -EIO; } =20 - /** - * Here, we successfully setting up vcpu affinity in - * IOMMU guest mode. Now, we need to store the posted - * interrupt information in a per-vcpu ir_list so that - * we can reference to them directly when we update vcpu - * scheduling information in IOMMU irte. + /* + * Update the target pCPU for IOMMU doorbells if the vCPU is + * running. If the vCPU is NOT running, i.e. is blocking or + * scheduled out, KVM will update the pCPU info when the vCPU + * is awakened and/or scheduled in. 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charset="utf-8" Infer whether or not a vCPU should be marked running from the validity of the pCPU on which it is running. amd_iommu_update_ga() already skips the IRTE update if the pCPU is invalid, i.e. passing %true for is_run with an invalid pCPU would be a blatant and egregrious KVM bug. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 11 +++++------ drivers/iommu/amd/iommu.c | 6 ++++-- include/linux/amd-iommu.h | 6 ++---- 3 files changed, 11 insertions(+), 12 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 4dbbb5a6cacc..3fcec297e3e3 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -842,7 +842,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, entry =3D svm->avic_physical_id_entry; if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) amd_iommu_update_ga(entry & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MAS= K, - true, pi_data.ir_data); + pi_data.ir_data); =20 irqfd->irq_bypass_data =3D pi_data.ir_data; list_add(&irqfd->vcpu_list, &svm->ir_list); @@ -851,8 +851,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, return irq_set_vcpu_affinity(host_irq, NULL); } =20 -static inline int -avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r) +static inline int avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, i= nt cpu) { int ret =3D 0; struct amd_svm_iommu_ir *ir; @@ -871,7 +870,7 @@ avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, = int cpu, bool r) return 0; =20 list_for_each_entry(ir, &svm->ir_list, node) { - ret =3D amd_iommu_update_ga(cpu, r, ir->data); + ret =3D amd_iommu_update_ga(cpu, ir->data); if (ret) return ret; } @@ -933,7 +932,7 @@ void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) =20 WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry); =20 - avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, true); + avic_update_iommu_vcpu_affinity(vcpu, h_physical_id); =20 spin_unlock_irqrestore(&svm->ir_list_lock, flags); } @@ -973,7 +972,7 @@ void avic_vcpu_put(struct kvm_vcpu *vcpu) */ spin_lock_irqsave(&svm->ir_list_lock, flags); =20 - avic_update_iommu_vcpu_affinity(vcpu, -1, 0); + avic_update_iommu_vcpu_affinity(vcpu, -1); =20 entry &=3D ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; svm->avic_physical_id_entry =3D entry; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index bc6f7eb2f04b..ba3a1a403cb2 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3957,7 +3957,7 @@ int amd_iommu_create_irq_domain(struct amd_iommu *iom= mu) return 0; } =20 -int amd_iommu_update_ga(int cpu, bool is_run, void *data) +int amd_iommu_update_ga(int cpu, void *data) { struct amd_ir_data *ir_data =3D (struct amd_ir_data *)data; struct irte_ga *entry =3D (struct irte_ga *) ir_data->entry; @@ -3974,8 +3974,10 @@ int amd_iommu_update_ga(int cpu, bool is_run, void *= data) APICID_TO_IRTE_DEST_LO(cpu); entry->hi.fields.destination =3D APICID_TO_IRTE_DEST_HI(cpu); + entry->lo.fields_vapic.is_run =3D true; + } else { + entry->lo.fields_vapic.is_run =3D false; } - entry->lo.fields_vapic.is_run =3D is_run; =20 return __modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, ir_data->irq_2_irte.index, entry); diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h index 99b4fa9a0296..fe0e16ffe0e5 100644 --- a/include/linux/amd-iommu.h +++ b/include/linux/amd-iommu.h @@ -30,8 +30,7 @@ static inline void amd_iommu_detect(void) { } /* IOMMU AVIC Function */ extern int amd_iommu_register_ga_log_notifier(int (*notifier)(u32)); =20 -extern int -amd_iommu_update_ga(int cpu, bool is_run, void *data); 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charset="utf-8" Split the guts of amd_iommu_update_ga() to a dedicated helper so that the logic can be shared with flows that put the IRTE into posted mode. Opportunistically move amd_iommu_update_ga() and its new helper above amd_iommu_activate_guest_mode() so that it's all co-located. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- drivers/iommu/amd/iommu.c | 59 +++++++++++++++++++++------------------ 1 file changed, 32 insertions(+), 27 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index ba3a1a403cb2..4fdf1502be69 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3775,6 +3775,38 @@ static const struct irq_domain_ops amd_ir_domain_ops= =3D { .deactivate =3D irq_remapping_deactivate, }; =20 +static void __amd_iommu_update_ga(struct irte_ga *entry, int cpu) +{ + if (cpu >=3D 0) { + entry->lo.fields_vapic.destination =3D + APICID_TO_IRTE_DEST_LO(cpu); + entry->hi.fields.destination =3D + APICID_TO_IRTE_DEST_HI(cpu); + entry->lo.fields_vapic.is_run =3D true; + } else { + entry->lo.fields_vapic.is_run =3D false; + } +} + +int amd_iommu_update_ga(int cpu, void *data) +{ + struct amd_ir_data *ir_data =3D (struct amd_ir_data *)data; + struct irte_ga *entry =3D (struct irte_ga *) ir_data->entry; + + if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || + !entry || !entry->lo.fields_vapic.guest_mode) + return 0; + + if (!ir_data->iommu) + return -ENODEV; + + __amd_iommu_update_ga(entry, cpu); + + return __modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, + ir_data->irq_2_irte.index, entry); +} +EXPORT_SYMBOL(amd_iommu_update_ga); + int amd_iommu_activate_guest_mode(void *data) { struct amd_ir_data *ir_data =3D (struct amd_ir_data *)data; @@ -3956,31 +3988,4 @@ int amd_iommu_create_irq_domain(struct amd_iommu *io= mmu) =20 return 0; } - -int amd_iommu_update_ga(int cpu, void *data) -{ - struct amd_ir_data *ir_data =3D (struct amd_ir_data *)data; - struct irte_ga *entry =3D (struct irte_ga *) ir_data->entry; - - if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || - !entry || !entry->lo.fields_vapic.guest_mode) - return 0; - - if (!ir_data->iommu) - return -ENODEV; - - if (cpu >=3D 0) { - entry->lo.fields_vapic.destination =3D - APICID_TO_IRTE_DEST_LO(cpu); - entry->hi.fields.destination =3D - APICID_TO_IRTE_DEST_HI(cpu); - entry->lo.fields_vapic.is_run =3D true; - } else { - entry->lo.fields_vapic.is_run =3D false; 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AJvYcCUcj/ClEw3FYF63DjdM1r1VC4QQuohaqupgtnr98sxJucQ8l2zq+ARuv7+INpQQjConqdti06o6dRv5KEI=@vger.kernel.org X-Gm-Message-State: AOJu0YwlqDdK6llNNZmgSBN1cM5sB1Kusthb6Hn62Pk0kV8i36Imxj8L YCQCSQlcbJgw3aOwee/GtaK64NLMix9IKf7YTFv0UJ05k3sRkhdlUQ+/tD5HioenNb0WS5lsNOJ CNw== X-Google-Smtp-Source: AGHT+IGPj22UXTH/Zcy5qZIqn9/BjQASYjiq8B8h2ade9XrhvSEXkbVGkfxvkxUFnqdy7NHyCw+NgEfc9co= X-Received: from pfch7.prod.google.com ([2002:a05:6a00:1707:b0:736:aaee:120e]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:3cc2:b0:730:75b1:7219 with SMTP id d2e1a72fcca58-739e70575e6mr4840675b3a.12.1743795666219; Fri, 04 Apr 2025 12:41:06 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:39:01 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-47-seanjc@google.com> Subject: [PATCH 46/67] iommu/amd: KVM: SVM: Set pCPU info in IRTE when setting vCPU affinity From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that setting vCPU affinity is guarded with ir_list_lock, i.e. now that avic_physical_id_entry can be safely accessed, set the pCPU info straight-away when setting vCPU affinity. Putting the IRTE into posted mode, and then immediately updating the IRTE a second time if the target vCPU is running is wasteful and confusing. This also fixes a flaw where a posted IRQ that arrives between putting the IRTE into guest_mode and setting the correct destination could cause the IOMMU to ring the doorbell on the wrong pCPU. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/include/asm/irq_remapping.h | 1 + arch/x86/kvm/svm/avic.c | 26 ++++++++++++++------------ drivers/iommu/amd/iommu.c | 6 ++++-- include/linux/amd-iommu.h | 4 ++-- 4 files changed, 21 insertions(+), 16 deletions(-) diff --git a/arch/x86/include/asm/irq_remapping.h b/arch/x86/include/asm/ir= q_remapping.h index 2dbc9cb61c2f..4c75a17632f6 100644 --- a/arch/x86/include/asm/irq_remapping.h +++ b/arch/x86/include/asm/irq_remapping.h @@ -35,6 +35,7 @@ struct amd_iommu_pi_data { u64 vapic_addr; /* Physical address of the vCPU's vAPIC. */ u32 ga_tag; u32 vector; /* Guest vector of the interrupt */ + int cpu; bool is_guest_mode; void *ir_data; }; diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 3fcec297e3e3..086139e85242 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -735,6 +735,7 @@ void avic_apicv_post_state_restore(struct kvm_vcpu *vcp= u) =20 static int avic_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate) { + int apic_id =3D kvm_cpu_get_apicid(vcpu->cpu); int ret =3D 0; unsigned long flags; struct amd_svm_iommu_ir *ir; @@ -754,7 +755,7 @@ static int avic_set_pi_irte_mode(struct kvm_vcpu *vcpu,= bool activate) =20 list_for_each_entry(ir, &svm->ir_list, node) { if (activate) - ret =3D amd_iommu_activate_guest_mode(ir->data); + ret =3D amd_iommu_activate_guest_mode(ir->data, apic_id); else ret =3D amd_iommu_deactivate_guest_mode(ir->data); if (ret) @@ -819,6 +820,18 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd= , struct kvm *kvm, */ guard(spinlock_irqsave)(&svm->ir_list_lock); =20 + /* + * Update the target pCPU for IOMMU doorbells if the vCPU is + * running. If the vCPU is NOT running, i.e. is blocking or + * scheduled out, KVM will update the pCPU info when the vCPU + * is awakened and/or scheduled in. See also avic_vcpu_load(). + */ + entry =3D svm->avic_physical_id_entry; + if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) + pi_data.cpu =3D entry & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; + else + pi_data.cpu =3D -1; + ret =3D irq_set_vcpu_affinity(host_irq, &pi_data); if (ret) return ret; @@ -833,17 +846,6 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd= , struct kvm *kvm, return -EIO; } =20 - /* - * Update the target pCPU for IOMMU doorbells if the vCPU is - * running. If the vCPU is NOT running, i.e. is blocking or - * scheduled out, KVM will update the pCPU info when the vCPU - * is awakened and/or scheduled in. See also avic_vcpu_load(). - */ - entry =3D svm->avic_physical_id_entry; - if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) - amd_iommu_update_ga(entry & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MAS= K, - pi_data.ir_data); - irqfd->irq_bypass_data =3D pi_data.ir_data; list_add(&irqfd->vcpu_list, &svm->ir_list); return 0; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 4fdf1502be69..b0b4c5ca16a8 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3807,7 +3807,7 @@ int amd_iommu_update_ga(int cpu, void *data) } EXPORT_SYMBOL(amd_iommu_update_ga); =20 -int amd_iommu_activate_guest_mode(void *data) +int amd_iommu_activate_guest_mode(void *data, int cpu) { struct amd_ir_data *ir_data =3D (struct amd_ir_data *)data; struct irte_ga *entry =3D (struct irte_ga *) ir_data->entry; @@ -3828,6 +3828,8 @@ int amd_iommu_activate_guest_mode(void *data) entry->hi.fields.vector =3D ir_data->ga_vector; entry->lo.fields_vapic.ga_tag =3D ir_data->ga_tag; =20 + __amd_iommu_update_ga(entry, cpu); + return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, ir_data->irq_2_irte.index, entry); } @@ -3894,7 +3896,7 @@ static int amd_ir_set_vcpu_affinity(struct irq_data *= data, void *info) ir_data->ga_root_ptr =3D (pi_data->vapic_addr >> 12); ir_data->ga_vector =3D pi_data->vector; ir_data->ga_tag =3D pi_data->ga_tag; - ret =3D amd_iommu_activate_guest_mode(ir_data); + ret =3D amd_iommu_activate_guest_mode(ir_data, pi_data->cpu); } else { ret =3D amd_iommu_deactivate_guest_mode(ir_data); } diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h index fe0e16ffe0e5..c9f2df0c4596 100644 --- a/include/linux/amd-iommu.h +++ b/include/linux/amd-iommu.h @@ -32,7 +32,7 @@ extern int amd_iommu_register_ga_log_notifier(int (*notif= ier)(u32)); =20 extern int amd_iommu_update_ga(int cpu, void *data); =20 -extern int amd_iommu_activate_guest_mode(void *data); +extern int amd_iommu_activate_guest_mode(void *data, int cpu); extern int amd_iommu_deactivate_guest_mode(void *data); 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charset="utf-8" If an IRQ can be posted to a vCPU, but AVIC is currently inhibited on the vCPU, go through the dance of "affining" the IRTE to the vCPU, but leave the actual IRTE in remapped mode. KVM already handles the case where AVIC is inhibited =3D> uninhibited with posted IRQs (see avic_set_pi_irte_mode()= ), but doesn't handle the scenario where a postable IRQ comes along while AVIC is inhibited. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 16 ++++++---------- drivers/iommu/amd/iommu.c | 5 ++++- 2 files changed, 10 insertions(+), 11 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 086139e85242..04bc1aa88dcc 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -790,21 +790,17 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqf= d, struct kvm *kvm, */ svm_ir_list_del(irqfd); =20 - /** - * Here, we setup with legacy mode in the following cases: - * 1. When cannot target interrupt to a specific vcpu. - * 2. Unsetting posted interrupt. - * 3. APIC virtualization is disabled for the vcpu. - * 4. IRQ has incompatible delivery mode (SMI, INIT, etc) - */ - if (vcpu && kvm_vcpu_apicv_active(vcpu)) { + if (vcpu) { /* - * Try to enable guest_mode in IRTE. + * Try to enable guest_mode in IRTE, unless AVIC is inhibited, + * in which case configure the IRTE for legacy mode, but track + * the IRTE metadata so that it can be converted to guest mode + * if AVIC is enabled/uninhibited in the future. */ struct amd_iommu_pi_data pi_data =3D { .ga_tag =3D AVIC_GATAG(to_kvm_svm(kvm)->avic_vm_id, vcpu->vcpu_id), - .is_guest_mode =3D true, + .is_guest_mode =3D kvm_vcpu_apicv_active(vcpu), .vapic_addr =3D avic_get_backing_page_address(to_svm(vcpu)), .vector =3D vector, }; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index b0b4c5ca16a8..a881fad027fd 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3896,7 +3896,10 @@ static int amd_ir_set_vcpu_affinity(struct irq_data = *data, void *info) ir_data->ga_root_ptr =3D (pi_data->vapic_addr >> 12); ir_data->ga_vector =3D pi_data->vector; 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charset="utf-8" Don't bother checking if a VM has an assigned device when updating AVIC vCPU affinity, querying ir_list is just as cheap and nothing prevents racing with changes in device assignment. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 04bc1aa88dcc..fc06bb9cad88 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -857,9 +857,6 @@ static inline int avic_update_iommu_vcpu_affinity(struc= t kvm_vcpu *vcpu, int cpu =20 lockdep_assert_held(&svm->ir_list_lock); =20 - if (!kvm_arch_has_assigned_device(vcpu->kvm)) - return 0; - /* * Here, we go through the per-vcpu ir_list to update all existing * interrupt remapping table entry targeting this vcpu. --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F18CC23CEF8 for ; Fri, 4 Apr 2025 19:41:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 04 Apr 2025 12:41:11 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:39:04 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-50-seanjc@google.com> Subject: [PATCH 49/67] KVM: SVM: Don't check for assigned device(s) when activating AVIC From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Don't short-circuit IRTE updating when (de)activating AVIC based on the VM having assigned devices, as nothing prevents AVIC (de)activation from racing with device (de)assignment. And from a performance perspective, bailing early when there is no assigned device doesn't add much, as ir_list_lock will never be contended if there's no assigned device. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index fc06bb9cad88..620772e07993 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -741,9 +741,6 @@ static int avic_set_pi_irte_mode(struct kvm_vcpu *vcpu,= bool activate) struct amd_svm_iommu_ir *ir; struct vcpu_svm *svm =3D to_svm(vcpu); =20 - if (!kvm_arch_has_assigned_device(vcpu->kvm)) - return 0; - /* * Here, we go through the per-vcpu ir_list to update all existing * interrupt remapping table entry targeting this vcpu. --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com [209.85.214.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08F1923E35C for ; Fri, 4 Apr 2025 19:41:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 04 Apr 2025 12:41:13 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:39:05 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-51-seanjc@google.com> Subject: [PATCH 50/67] KVM: SVM: WARN if (de)activating guest mode in IOMMU fails From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" WARN if (de)activating "guest mode" for an IRTE entry fails as modifying an IRTE should only fail if KVM is buggy, e.g. has stale metadata. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 620772e07993..5f5022d12b1b 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -733,10 +733,9 @@ void avic_apicv_post_state_restore(struct kvm_vcpu *vc= pu) avic_handle_ldr_update(vcpu); } =20 -static int avic_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate) +static void avic_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate) { int apic_id =3D kvm_cpu_get_apicid(vcpu->cpu); - int ret =3D 0; unsigned long flags; struct amd_svm_iommu_ir *ir; struct vcpu_svm *svm =3D to_svm(vcpu); @@ -752,15 +751,12 @@ static int avic_set_pi_irte_mode(struct kvm_vcpu *vcp= u, bool activate) =20 list_for_each_entry(ir, &svm->ir_list, node) { if (activate) - ret =3D amd_iommu_activate_guest_mode(ir->data, apic_id); + WARN_ON_ONCE(amd_iommu_activate_guest_mode(ir->data, apic_id)); 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charset="utf-8" When updating IRTE GA fields, keep processing all other IRTEs if an update fails, as not updating later entries risks making a bad situation worse. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 5f5022d12b1b..5544e8e88926 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -857,12 +857,10 @@ static inline int avic_update_iommu_vcpu_affinity(str= uct kvm_vcpu *vcpu, int cpu if (list_empty(&svm->ir_list)) return 0; =20 - list_for_each_entry(ir, &svm->ir_list, node) { + list_for_each_entry(ir, &svm->ir_list, node) ret =3D amd_iommu_update_ga(cpu, ir->data); - if (ret) - return ret; - } - return 0; + + return ret; } =20 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C64FE221542 for ; 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Fri, 04 Apr 2025 12:41:17 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:39:07 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-53-seanjc@google.com> Subject: [PATCH 52/67] KVM: SVM: WARN if updating IRTE GA fields in IOMMU fails From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" WARN if updating GA information for an IRTE entry fails as modifying an IRTE should only fail if KVM is buggy, e.g. has stale metadata, and because returning an error that is always ignored is pointless. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 5544e8e88926..a932eba1f42c 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -842,9 +842,8 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, return irq_set_vcpu_affinity(host_irq, NULL); } =20 -static inline int avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, i= nt cpu) +static void avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu) { - int ret =3D 0; struct amd_svm_iommu_ir *ir; struct vcpu_svm *svm =3D to_svm(vcpu); =20 @@ -855,12 +854,10 @@ static inline int avic_update_iommu_vcpu_affinity(str= uct kvm_vcpu *vcpu, int cpu * interrupt remapping table entry targeting this vcpu. */ if (list_empty(&svm->ir_list)) - return 0; + return; =20 list_for_each_entry(ir, &svm->ir_list, node) - ret =3D amd_iommu_update_ga(cpu, ir->data); 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AJvYcCXA0pVRClENOqr9+600mx/m8Y0bpEU7hA983Muc5pympkk+yHmkJEGRCNGb7RwYB10wFDOXCfC2EEephH8=@vger.kernel.org X-Gm-Message-State: AOJu0Yw17UHeOgMgsVt3mfMaLEg2FKmh6qOzgZI+5XVdQ5SUS8EfdNy2 aYHnU/VQEaZkXvdWcYi9xRH0KSG/TIaYdFsp1JRtjCx4jCgj26XOoL4HZNKar999ElvLdIJ0kHb P2A== X-Google-Smtp-Source: AGHT+IHERn8C/szUZcLSKQMAG6WxKIsTl8yFgLvt40FKuJ8sJxPaz/AKn88FnY3pmMlvJjyBpp9M9NdBiow= X-Received: from pfbdf1.prod.google.com ([2002:a05:6a00:4701:b0:737:69cc:5b41]) (user=seanjc job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6a00:a04:b0:736:3e50:bfec with SMTP id d2e1a72fcca58-73b6aa3d9b9mr865356b3a.8.1743795678916; Fri, 04 Apr 2025 12:41:18 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:39:08 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-54-seanjc@google.com> Subject: [PATCH 53/67] KVM: x86: Drop superfluous "has assigned device" check in kvm_pi_update_irte() From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Don't bother checking if the VM has an assigned device when updating IRTE entries. kvm_arch_irq_bypass_add_producer() explicitly increments the assigned device count, kvm_arch_irq_bypass_del_producer() explicitly decrements the count before invoking kvm_pi_update_irte(), and kvm_irq_routing_update() only updates IRTE entries if there's an active IRQ bypass producer. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/x86.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 0dc3b45cb664..513307952089 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -13577,9 +13577,7 @@ static int kvm_pi_update_irte(struct kvm_kernel_irq= fd *irqfd, struct kvm_lapic_irq irq; int r; =20 - if (!irqchip_in_kernel(kvm) || - !kvm_arch_has_irq_bypass() || - !kvm_arch_has_assigned_device(kvm)) + if (!irqchip_in_kernel(kvm) || !kvm_arch_has_irq_bypass()) return 0; =20 if (new && new->type =3D=3D KVM_IRQ_ROUTING_MSI) { --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C784243958 for ; Fri, 4 Apr 2025 19:41:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 04 Apr 2025 12:41:20 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:39:09 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-55-seanjc@google.com> Subject: [PATCH 54/67] KVM: x86: WARN if IRQ bypass isn't supported in kvm_pi_update_irte() From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" WARN if kvm_pi_update_irte() is reached without IRQ bypass support, as the code is only reachable if the VM already has an IRQ bypass producer (see kvm_irq_routing_update()), or from kvm_arch_irq_bypass_{add,del}_producer(), which, stating the obvious, are called if and only if KVM enables its IRQ bypass hooks. Cc: David Matlack Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/x86.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 513307952089..d05bffef88b7 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -13577,7 +13577,7 @@ static int kvm_pi_update_irte(struct kvm_kernel_irq= fd *irqfd, struct kvm_lapic_irq irq; int r; =20 - if (!irqchip_in_kernel(kvm) || !kvm_arch_has_irq_bypass()) + if (!irqchip_in_kernel(kvm) || WARN_ON_ONCE(!kvm_arch_has_irq_bypass())) return 0; =20 if (new && new->type =3D=3D KVM_IRQ_ROUTING_MSI) { --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pg1-f202.google.com (mail-pg1-f202.google.com [209.85.215.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2C382459C8 for ; Fri, 4 Apr 2025 19:41:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 04 Apr 2025 12:41:22 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:39:10 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-56-seanjc@google.com> Subject: [PATCH 55/67] KVM: x86: WARN if IRQ bypass routing is updated without in-kernel local APIC From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Yell if kvm_pi_update_irte() is reached without an in-kernel local APIC, as kvm_arch_irqfd_allowed() should prevent attaching an irqfd and thus any and all postable IRQs to an APIC-less VM. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/x86.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index d05bffef88b7..49c3360eb4e8 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -13577,8 +13577,8 @@ static int kvm_pi_update_irte(struct kvm_kernel_irq= fd *irqfd, struct kvm_lapic_irq irq; int r; =20 - if (!irqchip_in_kernel(kvm) || WARN_ON_ONCE(!kvm_arch_has_irq_bypass())) - return 0; + if (WARN_ON_ONCE(!irqchip_in_kernel(kvm) || !kvm_arch_has_irq_bypass())) + return -EINVAL; =20 if (new && new->type =3D=3D KVM_IRQ_ROUTING_MSI) { kvm_set_msi_irq(kvm, new, &irq); --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B2972459E6 for ; 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Fri, 04 Apr 2025 12:41:23 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:39:11 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-57-seanjc@google.com> Subject: [PATCH 56/67] KVM: SVM: WARN if ir_list is non-empty at vCPU free From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that AVIC IRTE tracking is in a mostly sane state, WARN if a vCPU is freed with ir_list entries, i.e. if KVM leaves a dangling IRTE. Initialize the per-vCPU interrupt remapping list and its lock even if AVIC is disabled so that the WARN doesn't hit false positives (and so that KVM doesn't need to call into AVIC code for a simple sanity check). Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 5 +++-- arch/x86/kvm/svm/svm.c | 2 ++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index a932eba1f42c..d2cbb7ac91f4 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -713,6 +713,9 @@ int avic_init_vcpu(struct vcpu_svm *svm) int ret; struct kvm_vcpu *vcpu =3D &svm->vcpu; =20 + INIT_LIST_HEAD(&svm->ir_list); + spin_lock_init(&svm->ir_list_lock); + if (!enable_apicv || !irqchip_in_kernel(vcpu->kvm)) return 0; =20 @@ -720,8 +723,6 @@ int avic_init_vcpu(struct vcpu_svm *svm) if (ret) return ret; =20 - INIT_LIST_HEAD(&svm->ir_list); - spin_lock_init(&svm->ir_list_lock); svm->dfr_reg =3D APIC_DFR_FLAT; =20 return ret; diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 43c4933d7da6..71b52ad13577 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -1499,6 +1499,8 @@ static void svm_vcpu_free(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm =3D to_svm(vcpu); =20 + WARN_ON_ONCE(!list_empty(&svm->ir_list)); + /* * The vmcb page can be recycled, causing a false negative in * svm_vcpu_load(). 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As evidenced by commit 2edd9cb79fb3 ("kvm: detect assigned device via irqbypass manager"), it's possible for a device to be able to post IRQs to a vCPU without said device being assigned to a VM. Leave the calls to kvm_arch_{start,end}_assignment() alone for the moment to avoid regressing the MMIO stale data mitigation. KVM is abusing the assigned device count when applying mmio_stale_data_clear, and it's not at all clear if vDPA devices rely on this behavior. This will hopefully be cleaned up in the future, as the number of assigned devices is a terrible heuristic for detecting if a VM has access to host MMIO. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/include/asm/kvm-x86-ops.h | 2 +- arch/x86/include/asm/kvm_host.h | 3 ++- arch/x86/kvm/vmx/main.c | 2 +- arch/x86/kvm/vmx/posted_intr.c | 16 ++++++++++------ arch/x86/kvm/vmx/posted_intr.h | 2 +- arch/x86/kvm/x86.c | 12 +++++++++--- 6 files changed, 24 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/kvm-x86-ops.h b/arch/x86/include/asm/kvm-= x86-ops.h index 823c0434bbad..435b9b76e464 100644 --- a/arch/x86/include/asm/kvm-x86-ops.h +++ b/arch/x86/include/asm/kvm-x86-ops.h @@ -111,7 +111,7 @@ KVM_X86_OP_OPTIONAL(update_cpu_dirty_logging) KVM_X86_OP_OPTIONAL(vcpu_blocking) KVM_X86_OP_OPTIONAL(vcpu_unblocking) KVM_X86_OP_OPTIONAL(pi_update_irte) -KVM_X86_OP_OPTIONAL(pi_start_assignment) +KVM_X86_OP_OPTIONAL(pi_start_bypass) KVM_X86_OP_OPTIONAL(apicv_pre_state_restore) KVM_X86_OP_OPTIONAL(apicv_post_state_restore) KVM_X86_OP_OPTIONAL_RET0(dy_apicv_has_pending_interrupt) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index cb98d8d3c6c2..88b842cd8959 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1372,6 +1372,7 @@ struct kvm_arch { atomic_t noncoherent_dma_count; #define __KVM_HAVE_ARCH_ASSIGNED_DEVICE atomic_t assigned_device_count; + unsigned long nr_possible_bypass_irqs; struct kvm_pic *vpic; struct kvm_ioapic *vioapic; struct kvm_pit *vpit; @@ -1840,7 +1841,7 @@ struct kvm_x86_ops { unsigned int host_irq, uint32_t guest_irq, struct kvm_kernel_irq_routing_entry *new, struct kvm_vcpu *vcpu, u32 vector); - void (*pi_start_assignment)(struct kvm *kvm); + void (*pi_start_bypass)(struct kvm *kvm); void (*apicv_pre_state_restore)(struct kvm_vcpu *vcpu); void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); bool (*dy_apicv_has_pending_interrupt)(struct kvm_vcpu *vcpu); diff --git a/arch/x86/kvm/vmx/main.c b/arch/x86/kvm/vmx/main.c index 43ee9ed11291..95371f26ce20 100644 --- a/arch/x86/kvm/vmx/main.c +++ b/arch/x86/kvm/vmx/main.c @@ -133,7 +133,7 @@ struct kvm_x86_ops vt_x86_ops __initdata =3D { .nested_ops =3D &vmx_nested_ops, =20 .pi_update_irte =3D vmx_pi_update_irte, - .pi_start_assignment =3D vmx_pi_start_assignment, + .pi_start_bypass =3D vmx_pi_start_bypass, =20 #ifdef CONFIG_X86_64 .set_hv_timer =3D vmx_set_hv_timer, diff --git a/arch/x86/kvm/vmx/posted_intr.c b/arch/x86/kvm/vmx/posted_intr.c index 2958b631fde8..457a5b21c9d3 100644 --- a/arch/x86/kvm/vmx/posted_intr.c +++ b/arch/x86/kvm/vmx/posted_intr.c @@ -132,8 +132,13 @@ void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) =20 static bool vmx_can_use_vtd_pi(struct kvm *kvm) { + /* + * Note, reading the number of possible bypass IRQs can race with a + * bypass IRQ being attached to the VM. vmx_pi_start_bypass() ensures + * blockng vCPUs will see an elevated count or get KVM_REQ_UNBLOCK. + */ return irqchip_in_kernel(kvm) && kvm_arch_has_irq_bypass() && - kvm_arch_has_assigned_device(kvm); + READ_ONCE(kvm->arch.nr_possible_bypass_irqs); } =20 /* @@ -251,12 +256,11 @@ bool pi_has_pending_interrupt(struct kvm_vcpu *vcpu) =20 =20 /* - * Bail out of the block loop if the VM has an assigned - * device, but the blocking vCPU didn't reconfigure the - * PI.NV to the wakeup vector, i.e. the assigned device - * came along after the initial check in vmx_vcpu_pi_put(). + * Kick all vCPUs when the first possible bypass IRQ is attached to a VM, = as + * blocking vCPUs may scheduled out without reconfiguring PID.NV to the wa= keup + * vector, i.e. if the bypass IRQ came along after vmx_vcpu_pi_put(). */ -void vmx_pi_start_assignment(struct kvm *kvm) +void vmx_pi_start_bypass(struct kvm *kvm) { if (!kvm_arch_has_irq_bypass()) return; diff --git a/arch/x86/kvm/vmx/posted_intr.h b/arch/x86/kvm/vmx/posted_intr.h index ee3e19e976ac..c3f12a35a7c1 100644 --- a/arch/x86/kvm/vmx/posted_intr.h +++ b/arch/x86/kvm/vmx/posted_intr.h @@ -17,7 +17,7 @@ int vmx_pi_update_irte(struct kvm_kernel_irqfd *irqfd, st= ruct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, struct kvm_kernel_irq_routing_entry *new, struct kvm_vcpu *vcpu, u32 vector); -void vmx_pi_start_assignment(struct kvm *kvm); +void vmx_pi_start_bypass(struct kvm *kvm); =20 static inline int pi_find_highest_vector(struct pi_desc *pi_desc) { diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 49c3360eb4e8..fec43d6a2b63 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -13511,8 +13511,7 @@ bool kvm_arch_can_dequeue_async_page_present(struct= kvm_vcpu *vcpu) =20 void kvm_arch_start_assignment(struct kvm *kvm) { - if (atomic_inc_return(&kvm->arch.assigned_device_count) =3D=3D 1) - kvm_x86_call(pi_start_assignment)(kvm); + atomic_inc(&kvm->arch.assigned_device_count); } EXPORT_SYMBOL_GPL(kvm_arch_start_assignment); =20 @@ -13630,10 +13629,15 @@ int kvm_arch_irq_bypass_add_producer(struct irq_b= ypass_consumer *cons, spin_lock_irq(&kvm->irqfds.lock); irqfd->producer =3D prod; =20 + if (!kvm->arch.nr_possible_bypass_irqs++) + kvm_x86_call(pi_start_bypass)(kvm); + if (irqfd->irq_entry.type =3D=3D KVM_IRQ_ROUTING_MSI) { ret =3D kvm_pi_update_irte(irqfd, NULL, &irqfd->irq_entry); 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charset="utf-8" WARN if KVM attempts to "start" IRQ bypass when VT-d Posted IRQs are disabled, to make it obvious that the logic is a sanity check, and so that a bug related to nr_possible_bypass_irqs is more like to cause noisy failures, e.g. so that KVM doesn't silently fail to wake blocking vCPUs. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/vmx/posted_intr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/posted_intr.c b/arch/x86/kvm/vmx/posted_intr.c index 457a5b21c9d3..29804dfa826c 100644 --- a/arch/x86/kvm/vmx/posted_intr.c +++ b/arch/x86/kvm/vmx/posted_intr.c @@ -262,7 +262,7 @@ bool pi_has_pending_interrupt(struct kvm_vcpu *vcpu) */ void vmx_pi_start_bypass(struct kvm *kvm) { - if (!kvm_arch_has_irq_bypass()) + if (WARN_ON_ONCE(!vmx_can_use_vtd_pi(kvm))) return; =20 kvm_make_all_cpus_request(kvm, KVM_REQ_UNBLOCK); --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6EAE624CEE5 for ; Fri, 4 Apr 2025 19:41:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 04 Apr 2025 12:41:28 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:39:14 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-60-seanjc@google.com> Subject: [PATCH 59/67] KVM: SVM: Use vcpu_idx, not vcpu_id, for GA log tag/metadata From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use a vCPU's index, not its ID, for the GA log tag/metadata that's used to find and kick vCPUs when a device posted interrupt serves as a wake event. Lookups on a vCPU index are O(fast) (not sure what xa_load() actually provides), whereas a vCPU ID lookup is O(n) if a vCPU's ID doesn't match its index. Unlike the Physical APIC Table, which is accessed by hardware when virtualizing IPIs, hardware doesn't consume the GA tag, i.e. KVM _must_ use APIC IDs to fill the Physical APIC Table, but KVM has free rein over the format/meaning of the GA tag. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 37 ++++++++++++++++++++----------------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index d2cbb7ac91f4..d567d62463ac 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -29,36 +29,39 @@ #include "svm.h" =20 /* - * Encode the arbitrary VM ID and the vCPU's default APIC ID, i.e the vCPU= ID, - * into the GATag so that KVM can retrieve the correct vCPU from a GALog e= ntry - * if an interrupt can't be delivered, e.g. because the vCPU isn't running. + * Encode the arbitrary VM ID and the vCPU's _index_ into the GATag so that + * KVM can retrieve the correct vCPU from a GALog entry if an interrupt ca= n't + * be delivered, e.g. because the vCPU isn't running. Use the vCPU's index + * instead of its ID (a.k.a. its default APIC ID), as KVM is guaranteed a = fast + * lookup on the index, where as vCPUs whose index doesn't match their ID = need + * to walk the entire xarray of vCPUs in the worst case scenario. * - * For the vCPU ID, use however many bits are currently allowed for the max + * For the vCPU index, use however many bits are currently allowed for the= max * guest physical APIC ID (limited by the size of the physical ID table), = and * use whatever bits remain to assign arbitrary AVIC IDs to VMs. Note, the * size of the GATag is defined by hardware (32 bits), but is an opaque va= lue * as far as hardware is concerned. */ -#define AVIC_VCPU_ID_MASK AVIC_PHYSICAL_MAX_INDEX_MASK +#define AVIC_VCPU_IDX_MASK AVIC_PHYSICAL_MAX_INDEX_MASK =20 #define AVIC_VM_ID_SHIFT HWEIGHT32(AVIC_PHYSICAL_MAX_INDEX_MASK) #define AVIC_VM_ID_MASK (GENMASK(31, AVIC_VM_ID_SHIFT) >> AVIC_VM_ID_SHI= FT) =20 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VM_ID_SHIFT) & AVIC_VM_ID_MASK) -#define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK) +#define AVIC_GATAG_TO_VCPUIDX(x) (x & AVIC_VCPU_IDX_MASK) =20 -#define __AVIC_GATAG(vm_id, vcpu_id) ((((vm_id) & AVIC_VM_ID_MASK) << AVIC= _VM_ID_SHIFT) | \ - ((vcpu_id) & AVIC_VCPU_ID_MASK)) -#define AVIC_GATAG(vm_id, vcpu_id) \ +#define __AVIC_GATAG(vm_id, vcpu_idx) ((((vm_id) & AVIC_VM_ID_MASK) << AVI= C_VM_ID_SHIFT) | \ + ((vcpu_idx) & AVIC_VCPU_IDX_MASK)) +#define AVIC_GATAG(vm_id, vcpu_idx) \ ({ \ - u32 ga_tag =3D __AVIC_GATAG(vm_id, vcpu_id); \ + u32 ga_tag =3D __AVIC_GATAG(vm_id, vcpu_idx); \ \ - WARN_ON_ONCE(AVIC_GATAG_TO_VCPUID(ga_tag) !=3D (vcpu_id)); \ + WARN_ON_ONCE(AVIC_GATAG_TO_VCPUIDX(ga_tag) !=3D (vcpu_idx)); \ WARN_ON_ONCE(AVIC_GATAG_TO_VMID(ga_tag) !=3D (vm_id)); \ ga_tag; \ }) =20 -static_assert(__AVIC_GATAG(AVIC_VM_ID_MASK, AVIC_VCPU_ID_MASK) =3D=3D -1u); +static_assert(__AVIC_GATAG(AVIC_VM_ID_MASK, AVIC_VCPU_IDX_MASK) =3D=3D -1u= ); =20 static bool force_avic; module_param_unsafe(force_avic, bool, 0444); @@ -148,16 +151,16 @@ int avic_ga_log_notifier(u32 ga_tag) struct kvm_svm *kvm_svm; struct kvm_vcpu *vcpu =3D NULL; u32 vm_id =3D AVIC_GATAG_TO_VMID(ga_tag); - u32 vcpu_id =3D AVIC_GATAG_TO_VCPUID(ga_tag); + u32 vcpu_idx =3D AVIC_GATAG_TO_VCPUIDX(ga_tag); =20 - pr_debug("SVM: %s: vm_id=3D%#x, vcpu_id=3D%#x\n", __func__, vm_id, vcpu_i= d); - trace_kvm_avic_ga_log(vm_id, vcpu_id); + pr_debug("SVM: %s: vm_id=3D%#x, vcpu_idx=3D%#x\n", __func__, vm_id, vcpu_= idx); + trace_kvm_avic_ga_log(vm_id, vcpu_idx); =20 spin_lock_irqsave(&svm_vm_data_hash_lock, flags); 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Fri, 04 Apr 2025 12:41:30 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:39:15 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-61-seanjc@google.com> Subject: [PATCH 60/67] iommu/amd: WARN if KVM calls GA IRTE helpers without virtual APIC support From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" WARN if KVM attempts to update IRTE entries when virtual APIC isn't fully supported, as KVM should guard all such calls on IRQ posting being enabled. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- drivers/iommu/amd/iommu.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index a881fad027fd..2e016b98fa1b 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3793,8 +3793,10 @@ int amd_iommu_update_ga(int cpu, void *data) struct amd_ir_data *ir_data =3D (struct amd_ir_data *)data; struct irte_ga *entry =3D (struct irte_ga *) ir_data->entry; =20 - if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || - !entry || !entry->lo.fields_vapic.guest_mode) + if (WARN_ON_ONCE(!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))) + return -EINVAL; + + if (!entry || !entry->lo.fields_vapic.guest_mode) return 0; =20 if (!ir_data->iommu) @@ -3813,7 +3815,10 @@ int amd_iommu_activate_guest_mode(void *data, int cp= u) struct irte_ga *entry =3D (struct irte_ga *) ir_data->entry; u64 valid; =20 - if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) || !entry) + if (WARN_ON_ONCE(!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))) + return -EINVAL; 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Fri, 04 Apr 2025 12:41:32 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:39:16 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-62-seanjc@google.com> Subject: [PATCH 61/67] KVM: SVM: Fold avic_set_pi_irte_mode() into its sole caller From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fold avic_set_pi_irte_mode() into avic_refresh_apicv_exec_ctrl() in anticipation of moving the __avic_vcpu_{load,put}() calls into the critical section, and because having a one-off helper with a name that's easily confused with avic_pi_update_irte() is unnecessary. No functional change intended. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 48 ++++++++++++++++++----------------------- 1 file changed, 21 insertions(+), 27 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index d567d62463ac..0425cc374a79 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -737,32 +737,6 @@ void avic_apicv_post_state_restore(struct kvm_vcpu *vc= pu) avic_handle_ldr_update(vcpu); } =20 -static void avic_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate) -{ - int apic_id =3D kvm_cpu_get_apicid(vcpu->cpu); - unsigned long flags; - struct amd_svm_iommu_ir *ir; - struct vcpu_svm *svm =3D to_svm(vcpu); - - /* - * Here, we go through the per-vcpu ir_list to update all existing - * interrupt remapping table entry targeting this vcpu. - */ - spin_lock_irqsave(&svm->ir_list_lock, flags); - - if (list_empty(&svm->ir_list)) - goto out; - - list_for_each_entry(ir, &svm->ir_list, node) { - if (activate) - WARN_ON_ONCE(amd_iommu_activate_guest_mode(ir->data, apic_id)); - else - WARN_ON_ONCE(amd_iommu_deactivate_guest_mode(ir->data)); - } -out: - spin_unlock_irqrestore(&svm->ir_list_lock, flags); -} - static void svm_ir_list_del(struct kvm_kernel_irqfd *irqfd) { struct kvm_vcpu *vcpu =3D irqfd->irq_bypass_vcpu; @@ -998,6 +972,10 @@ void avic_refresh_virtual_apic_mode(struct kvm_vcpu *v= cpu) void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) { bool activated =3D kvm_vcpu_apicv_active(vcpu); + int apic_id =3D kvm_cpu_get_apicid(vcpu->cpu); + struct vcpu_svm *svm =3D to_svm(vcpu); + struct amd_svm_iommu_ir *ir; + unsigned long flags; =20 if (!enable_apicv) return; @@ -1009,7 +987,23 @@ void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vc= pu) else avic_vcpu_put(vcpu); =20 - avic_set_pi_irte_mode(vcpu, activated); + /* + * Here, we go through the per-vcpu ir_list to update all existing + * interrupt remapping table entry targeting this vcpu. + */ + spin_lock_irqsave(&svm->ir_list_lock, flags); + + if (list_empty(&svm->ir_list)) + goto out; + + list_for_each_entry(ir, &svm->ir_list, node) { + if (activated) + WARN_ON_ONCE(amd_iommu_activate_guest_mode(ir->data, apic_id)); + else + WARN_ON_ONCE(amd_iommu_deactivate_guest_mode(ir->data)); + } +out: + spin_unlock_irqrestore(&svm->ir_list_lock, flags); } =20 void avic_vcpu_blocking(struct kvm_vcpu *vcpu) --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACB552512DF for ; Fri, 4 Apr 2025 19:41:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743795696; cv=none; b=bY1lfhFEMfZvsMJujvrOtRFZ5NU8bzG+zeIeavWH/LGDV+9hBevuVh6PwLmw+R8XqomZU2OL8meGJJkGMk3h5ncMBw2bIjW7zaFwUgaNw4DZXMdxq5FYlbCwpnfZ2IfwmGm46s4yC7PUL8fyYGw8Ixlc+xolO2qNWrGNWjyCGmA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743795696; 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charset="utf-8" Don't query a vCPU's blocking status when toggling AVIC on/off; barring KVM bugs, the vCPU can't be blocking when refrecing AVIC controls. And if there are KVM bugs, ensuring the vCPU and its associated IRTEs are in the correct state is desirable, i.e. well worth any overhead in a buggy scenario. Isolating the "real" load/put flows will allow moving the IOMMU IRTE (de)activation logic from avic_refresh_apicv_exec_ctrl() to avic_update_iommu_vcpu_affinity(), i.e. will allow updating the vCPU's physical ID entry and its IRTEs in a common path, under a single critical section of ir_list_lock. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 65 +++++++++++++++++++++++------------------ 1 file changed, 37 insertions(+), 28 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 0425cc374a79..d5fa915d0827 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -838,7 +838,7 @@ static void avic_update_iommu_vcpu_affinity(struct kvm_= vcpu *vcpu, int cpu) WARN_ON_ONCE(amd_iommu_update_ga(cpu, ir->data)); } =20 -void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) +static void __avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) { struct kvm_svm *kvm_svm =3D to_kvm_svm(vcpu->kvm); int h_physical_id =3D kvm_cpu_get_apicid(cpu); @@ -854,16 +854,6 @@ void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) if (WARN_ON_ONCE(vcpu->vcpu_id * sizeof(entry) >=3D PAGE_SIZE)) return; =20 - /* - * No need to update anything if the vCPU is blocking, i.e. if the vCPU - * is being scheduled in after being preempted. The CPU entries in the - * Physical APIC table and IRTE are consumed iff IsRun{ning} is '1'. - * If the vCPU was migrated, its new CPU value will be stuffed when the - * vCPU unblocks. - */ - if (kvm_vcpu_is_blocking(vcpu)) - return; - /* * Grab the per-vCPU interrupt remapping lock even if the VM doesn't * _currently_ have assigned devices, as that can change. Holding @@ -898,31 +888,33 @@ void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) spin_unlock_irqrestore(&svm->ir_list_lock, flags); } =20 -void avic_vcpu_put(struct kvm_vcpu *vcpu) +void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) +{ + /* + * No need to update anything if the vCPU is blocking, i.e. if the vCPU + * is being scheduled in after being preempted. The CPU entries in the + * Physical APIC table and IRTE are consumed iff IsRun{ning} is '1'. + * If the vCPU was migrated, its new CPU value will be stuffed when the + * vCPU unblocks. + */ + if (kvm_vcpu_is_blocking(vcpu)) + return; + + __avic_vcpu_load(vcpu, cpu); +} + +static void __avic_vcpu_put(struct kvm_vcpu *vcpu) { struct kvm_svm *kvm_svm =3D to_kvm_svm(vcpu->kvm); struct vcpu_svm *svm =3D to_svm(vcpu); unsigned long flags; - u64 entry; + u64 entry =3D svm->avic_physical_id_entry; =20 lockdep_assert_preemption_disabled(); =20 if (WARN_ON_ONCE(vcpu->vcpu_id * sizeof(entry) >=3D PAGE_SIZE)) return; =20 - /* - * Note, reading the Physical ID entry outside of ir_list_lock is safe - * as only the pCPU that has loaded (or is loading) the vCPU is allowed - * to modify the entry, and preemption is disabled. I.e. the vCPU - * can't be scheduled out and thus avic_vcpu_{put,load}() can't run - * recursively. - */ - entry =3D svm->avic_physical_id_entry; - - /* Nothing to do if IsRunning =3D=3D '0' due to vCPU blocking. */ - if (!(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)) - return; - /* * Take and hold the per-vCPU interrupt remapping lock while updating * the Physical ID entry even though the lock doesn't protect against @@ -942,7 +934,24 @@ void avic_vcpu_put(struct kvm_vcpu *vcpu) WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry); =20 spin_unlock_irqrestore(&svm->ir_list_lock, flags); +} =20 +void avic_vcpu_put(struct kvm_vcpu *vcpu) +{ + /* + * Note, reading the Physical ID entry outside of ir_list_lock is safe + * as only the pCPU that has loaded (or is loading) the vCPU is allowed + * to modify the entry, and preemption is disabled. I.e. the vCPU + * can't be scheduled out and thus avic_vcpu_{put,load}() can't run + * recursively. + */ + u64 entry =3D to_svm(vcpu)->avic_physical_id_entry; + + /* Nothing to do if IsRunning =3D=3D '0' due to vCPU blocking. */ + if (!(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)) + return; + + __avic_vcpu_put(vcpu); } =20 void avic_refresh_virtual_apic_mode(struct kvm_vcpu *vcpu) @@ -983,9 +992,9 @@ void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) avic_refresh_virtual_apic_mode(vcpu); =20 if (activated) - avic_vcpu_load(vcpu, vcpu->cpu); + __avic_vcpu_load(vcpu, vcpu->cpu); else - avic_vcpu_put(vcpu); + __avic_vcpu_put(vcpu); =20 /* * Here, we go through the per-vcpu ir_list to update all existing --=20 2.49.0.504.g3bcea36a83-goog From nobody Wed Dec 17 03:45:21 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24BB82528F8 for ; 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Fri, 04 Apr 2025 12:41:35 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:39:18 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-64-seanjc@google.com> Subject: [PATCH 63/67] KVM: SVM: Consolidate IRTE update when toggling AVIC on/off From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fold the IRTE modification logic in avic_refresh_apicv_exec_ctrl() into __avic_vcpu_{load,put}(), and add a param to the helpers to communicate whether or not AVIC is being toggled, i.e. if IRTE needs a "full" update, or just a quick update to set the CPU and IsRun. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 55 ++++++++++++++--------------------------- 1 file changed, 19 insertions(+), 36 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index d5fa915d0827..c896f00f901c 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -820,7 +820,8 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, return irq_set_vcpu_affinity(host_irq, NULL); } =20 -static void avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu) +static void avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, + bool toggle_avic) { struct amd_svm_iommu_ir *ir; struct vcpu_svm *svm =3D to_svm(vcpu); @@ -834,11 +835,17 @@ static void avic_update_iommu_vcpu_affinity(struct kv= m_vcpu *vcpu, int cpu) if (list_empty(&svm->ir_list)) return; =20 - list_for_each_entry(ir, &svm->ir_list, node) - WARN_ON_ONCE(amd_iommu_update_ga(cpu, ir->data)); + list_for_each_entry(ir, &svm->ir_list, node) { + if (!toggle_avic) + WARN_ON_ONCE(amd_iommu_update_ga(cpu, ir->data)); + else if (cpu >=3D 0) + WARN_ON_ONCE(amd_iommu_activate_guest_mode(ir->data, cpu)); + else + WARN_ON_ONCE(amd_iommu_deactivate_guest_mode(ir->data)); + } } =20 -static void __avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) +static void __avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu, bool toggle_a= vic) { struct kvm_svm *kvm_svm =3D to_kvm_svm(vcpu->kvm); int h_physical_id =3D kvm_cpu_get_apicid(cpu); @@ -883,7 +890,7 @@ static void __avic_vcpu_load(struct kvm_vcpu *vcpu, int= cpu) =20 WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry); =20 - avic_update_iommu_vcpu_affinity(vcpu, h_physical_id); + avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, toggle_avic); =20 spin_unlock_irqrestore(&svm->ir_list_lock, flags); } @@ -900,10 +907,10 @@ void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) if (kvm_vcpu_is_blocking(vcpu)) return; =20 - __avic_vcpu_load(vcpu, cpu); + __avic_vcpu_load(vcpu, cpu, false); } =20 -static void __avic_vcpu_put(struct kvm_vcpu *vcpu) +static void __avic_vcpu_put(struct kvm_vcpu *vcpu, bool toggle_avic) { struct kvm_svm *kvm_svm =3D to_kvm_svm(vcpu->kvm); struct vcpu_svm *svm =3D to_svm(vcpu); @@ -925,7 +932,7 @@ static void __avic_vcpu_put(struct kvm_vcpu *vcpu) */ spin_lock_irqsave(&svm->ir_list_lock, flags); =20 - avic_update_iommu_vcpu_affinity(vcpu, -1); + avic_update_iommu_vcpu_affinity(vcpu, -1, toggle_avic); =20 entry &=3D ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; svm->avic_physical_id_entry =3D entry; @@ -951,7 +958,7 @@ void avic_vcpu_put(struct kvm_vcpu *vcpu) if (!(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)) return; =20 - __avic_vcpu_put(vcpu); + __avic_vcpu_put(vcpu, false); } =20 void avic_refresh_virtual_apic_mode(struct kvm_vcpu *vcpu) @@ -980,39 +987,15 @@ void avic_refresh_virtual_apic_mode(struct kvm_vcpu *= vcpu) =20 void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) { - bool activated =3D kvm_vcpu_apicv_active(vcpu); - int apic_id =3D kvm_cpu_get_apicid(vcpu->cpu); - struct vcpu_svm *svm =3D to_svm(vcpu); - struct amd_svm_iommu_ir *ir; - unsigned long flags; - if (!enable_apicv) return; =20 avic_refresh_virtual_apic_mode(vcpu); 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Fri, 04 Apr 2025 12:41:37 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:39:19 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-65-seanjc@google.com> Subject: [PATCH 64/67] iommu/amd: KVM: SVM: Allow KVM to control need for GA log interrupts From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add plumbing to the AMD IOMMU driver to allow KVM to control whether or not an IRTE is configured to generate GA log interrupts. KVM only needs a notification if the target vCPU is blocking, so the vCPU can be awakened. If a vCPU is preempted or exits to userspace, KVM clears is_run, but will set the vCPU back to running when userspace does KVM_RUN and/or the vCPU task is scheduled back in, i.e. KVM doesn't need a notification. Unconditionally pass "true" in all KVM paths to isolate the IOMMU changes from the KVM changes insofar as possible. Opportunistically swap the ordering of parameters for amd_iommu_update_ga() so that the match amd_iommu_activate_guest_mode(). Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/include/asm/irq_remapping.h | 1 + arch/x86/kvm/svm/avic.c | 10 ++++++---- drivers/iommu/amd/iommu.c | 17 ++++++++++------- include/linux/amd-iommu.h | 9 ++++----- 4 files changed, 21 insertions(+), 16 deletions(-) diff --git a/arch/x86/include/asm/irq_remapping.h b/arch/x86/include/asm/ir= q_remapping.h index 4c75a17632f6..5a0d42464d44 100644 --- a/arch/x86/include/asm/irq_remapping.h +++ b/arch/x86/include/asm/irq_remapping.h @@ -36,6 +36,7 @@ struct amd_iommu_pi_data { u32 ga_tag; u32 vector; /* Guest vector of the interrupt */ int cpu; + bool ga_log_intr; bool is_guest_mode; void *ir_data; }; diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index c896f00f901c..1466e66cca6c 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -794,10 +794,12 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqf= d, struct kvm *kvm, * is awakened and/or scheduled in. See also avic_vcpu_load(). */ entry =3D svm->avic_physical_id_entry; - if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) + if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK) { pi_data.cpu =3D entry & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; - else + } else { pi_data.cpu =3D -1; + pi_data.ga_log_intr =3D true; + } =20 ret =3D irq_set_vcpu_affinity(host_irq, &pi_data); if (ret) @@ -837,9 +839,9 @@ static void avic_update_iommu_vcpu_affinity(struct kvm_= vcpu *vcpu, int cpu, =20 list_for_each_entry(ir, &svm->ir_list, node) { if (!toggle_avic) - WARN_ON_ONCE(amd_iommu_update_ga(cpu, ir->data)); + WARN_ON_ONCE(amd_iommu_update_ga(ir->data, cpu, true)); else if (cpu >=3D 0) - WARN_ON_ONCE(amd_iommu_activate_guest_mode(ir->data, cpu)); + WARN_ON_ONCE(amd_iommu_activate_guest_mode(ir->data, cpu, true)); else WARN_ON_ONCE(amd_iommu_deactivate_guest_mode(ir->data)); } diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 2e016b98fa1b..27b03e718980 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3775,7 +3775,8 @@ static const struct irq_domain_ops amd_ir_domain_ops = =3D { .deactivate =3D irq_remapping_deactivate, }; =20 -static void __amd_iommu_update_ga(struct irte_ga *entry, int cpu) +static void __amd_iommu_update_ga(struct irte_ga *entry, int cpu, + bool ga_log_intr) { if (cpu >=3D 0) { entry->lo.fields_vapic.destination =3D @@ -3783,12 +3784,14 @@ static void __amd_iommu_update_ga(struct irte_ga *e= ntry, int cpu) entry->hi.fields.destination =3D APICID_TO_IRTE_DEST_HI(cpu); entry->lo.fields_vapic.is_run =3D true; + entry->lo.fields_vapic.ga_log_intr =3D false; } else { entry->lo.fields_vapic.is_run =3D false; + entry->lo.fields_vapic.ga_log_intr =3D ga_log_intr; } } =20 -int amd_iommu_update_ga(int cpu, void *data) +int amd_iommu_update_ga(void *data, int cpu, bool ga_log_intr) { struct amd_ir_data *ir_data =3D (struct amd_ir_data *)data; struct irte_ga *entry =3D (struct irte_ga *) ir_data->entry; @@ -3802,14 +3805,14 @@ int amd_iommu_update_ga(int cpu, void *data) if (!ir_data->iommu) return -ENODEV; =20 - __amd_iommu_update_ga(entry, cpu); + __amd_iommu_update_ga(entry, cpu, ga_log_intr); =20 return __modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, ir_data->irq_2_irte.index, entry); } EXPORT_SYMBOL(amd_iommu_update_ga); =20 -int amd_iommu_activate_guest_mode(void *data, int cpu) +int amd_iommu_activate_guest_mode(void *data, int cpu, bool ga_log_intr) { struct amd_ir_data *ir_data =3D (struct amd_ir_data *)data; struct irte_ga *entry =3D (struct irte_ga *) ir_data->entry; @@ -3828,12 +3831,11 @@ int amd_iommu_activate_guest_mode(void *data, int c= pu) =20 entry->lo.fields_vapic.valid =3D valid; entry->lo.fields_vapic.guest_mode =3D 1; - entry->lo.fields_vapic.ga_log_intr =3D 1; entry->hi.fields.ga_root_ptr =3D ir_data->ga_root_ptr; entry->hi.fields.vector =3D ir_data->ga_vector; entry->lo.fields_vapic.ga_tag =3D ir_data->ga_tag; =20 - __amd_iommu_update_ga(entry, cpu); + __amd_iommu_update_ga(entry, cpu, ga_log_intr); =20 return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, ir_data->irq_2_irte.index, entry); @@ -3904,7 +3906,8 @@ static int amd_ir_set_vcpu_affinity(struct irq_data *= data, void *info) ir_data->ga_vector =3D pi_data->vector; ir_data->ga_tag =3D pi_data->ga_tag; if (pi_data->is_guest_mode) - ret =3D amd_iommu_activate_guest_mode(ir_data, pi_data->cpu); + ret =3D amd_iommu_activate_guest_mode(ir_data, pi_data->cpu, + pi_data->ga_log_intr); else ret =3D amd_iommu_deactivate_guest_mode(ir_data); } else { diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h index c9f2df0c4596..8cced632ecd0 100644 --- a/include/linux/amd-iommu.h +++ b/include/linux/amd-iommu.h @@ -30,9 +30,8 @@ static inline void amd_iommu_detect(void) { } /* IOMMU AVIC Function */ extern int amd_iommu_register_ga_log_notifier(int (*notifier)(u32)); =20 -extern int amd_iommu_update_ga(int cpu, void *data); - -extern int amd_iommu_activate_guest_mode(void *data, int cpu); +extern int amd_iommu_update_ga(void *data, int cpu, bool ga_log_intr); +extern int amd_iommu_activate_guest_mode(void *data, int cpu, bool ga_log_= intr); extern int amd_iommu_deactivate_guest_mode(void *data); =20 #else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */ @@ -43,12 +42,12 @@ amd_iommu_register_ga_log_notifier(int (*notifier)(u32)) return 0; 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charset="utf-8" Configure IRTEs to GA log interrupts for device posted IRQs that hit non-running vCPUs if and only if the target vCPU is blocking, i.e. actually needs a wake event. If the vCPU has exited to userspace or was preempted, generating GA log entries and interrupts is wasteful and unnecessary, as the vCPU will be re-loaded and/or scheduled back in irrespective of the GA log notification (avic_ga_log_notifier() is just a fancy wrapper for kvm_vcpu_wake_up()). Use a should-be-zero bit in the vCPU's Physical APIC ID Table Entry to track whether or not the vCPU's associated IRTEs are configured to generate GA logs, but only set the synthetic bit in KVM's "cache", i.e. never set the should-be-zero bit in tables that are used by hardware. Use a synthetic bit instead of a dedicated boolean to minimize the odds of messing up the locking, i.e. so that all the existing rules that apply to avic_physical_id_entry for IS_RUNNING are reused verbatim for GA_LOG_INTR. Note, because KVM (by design) "puts" AVIC state in a "pre-blocking" phase, using kvm_vcpu_is_blocking() to track the need for notifications isn't a viable option. Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/include/asm/svm.h | 7 ++++++ arch/x86/kvm/svm/avic.c | 49 +++++++++++++++++++++++++++----------- 2 files changed, 42 insertions(+), 14 deletions(-) diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index 8b07939ef3b9..be6e833bf92c 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -246,6 +246,13 @@ struct __attribute__ ((__packed__)) vmcb_control_area { #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31) =20 +/* + * GA_LOG_INTR is a synthetic flag that's never propagated to hardware-vis= ible + * tables. GA_LOG_INTR is set if the vCPU needs device posted IRQs to gen= erate + * GA log interrupts to wake the vCPU (because it's blocking or about to b= lock). + */ +#define AVIC_PHYSICAL_ID_ENTRY_GA_LOG_INTR BIT_ULL(61) + #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK GENMASK_ULL(11, 0) #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK GENMASK_ULL(51, 12) #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 1466e66cca6c..0d2a17a74be6 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -798,7 +798,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, pi_data.cpu =3D entry & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; } else { pi_data.cpu =3D -1; - pi_data.ga_log_intr =3D true; + pi_data.ga_log_intr =3D entry & AVIC_PHYSICAL_ID_ENTRY_GA_LOG_INTR; } =20 ret =3D irq_set_vcpu_affinity(host_irq, &pi_data); @@ -823,7 +823,7 @@ int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd,= struct kvm *kvm, } =20 static void avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, - bool toggle_avic) + bool toggle_avic, bool ga_log_intr) { struct amd_svm_iommu_ir *ir; struct vcpu_svm *svm =3D to_svm(vcpu); @@ -839,9 +839,9 @@ static void avic_update_iommu_vcpu_affinity(struct kvm_= vcpu *vcpu, int cpu, =20 list_for_each_entry(ir, &svm->ir_list, node) { if (!toggle_avic) - WARN_ON_ONCE(amd_iommu_update_ga(ir->data, cpu, true)); + WARN_ON_ONCE(amd_iommu_update_ga(ir->data, cpu, ga_log_intr)); else if (cpu >=3D 0) - WARN_ON_ONCE(amd_iommu_activate_guest_mode(ir->data, cpu, true)); + WARN_ON_ONCE(amd_iommu_activate_guest_mode(ir->data, cpu, ga_log_intr)); else WARN_ON_ONCE(amd_iommu_deactivate_guest_mode(ir->data)); } @@ -875,7 +875,8 @@ static void __avic_vcpu_load(struct kvm_vcpu *vcpu, int= cpu, bool toggle_avic) entry =3D svm->avic_physical_id_entry; WARN_ON_ONCE(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK); =20 - entry &=3D ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK; + entry &=3D ~(AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK | + AVIC_PHYSICAL_ID_ENTRY_GA_LOG_INTR); entry |=3D (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK); entry |=3D AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; =20 @@ -892,7 +893,7 @@ static void __avic_vcpu_load(struct kvm_vcpu *vcpu, int= cpu, bool toggle_avic) =20 WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry); =20 - avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, toggle_avic); + avic_update_iommu_vcpu_affinity(vcpu, h_physical_id, toggle_avic, false); =20 spin_unlock_irqrestore(&svm->ir_list_lock, flags); } @@ -912,7 +913,8 @@ void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu) __avic_vcpu_load(vcpu, cpu, false); } =20 -static void __avic_vcpu_put(struct kvm_vcpu *vcpu, bool toggle_avic) +static void __avic_vcpu_put(struct kvm_vcpu *vcpu, bool toggle_avic, + bool is_blocking) { struct kvm_svm *kvm_svm =3D to_kvm_svm(vcpu->kvm); struct vcpu_svm *svm =3D to_svm(vcpu); @@ -934,14 +936,28 @@ static void __avic_vcpu_put(struct kvm_vcpu *vcpu, bo= ol toggle_avic) */ spin_lock_irqsave(&svm->ir_list_lock, flags); =20 - avic_update_iommu_vcpu_affinity(vcpu, -1, toggle_avic); + avic_update_iommu_vcpu_affinity(vcpu, -1, toggle_avic, is_blocking); =20 + WARN_ON_ONCE(entry & AVIC_PHYSICAL_ID_ENTRY_GA_LOG_INTR); + + /* + * Keep the previouv APIC ID in the entry so that a rogue doorbell from + * hardware is at least restricted to a CPU associated with the vCPU. + */ entry &=3D ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK; - svm->avic_physical_id_entry =3D entry; =20 if (enable_ipiv) WRITE_ONCE(kvm_svm->avic_physical_id_table[vcpu->vcpu_id], entry); =20 + /* + * Note! Don't set AVIC_PHYSICAL_ID_ENTRY_GA_LOG_INTR in the table as + * it's a synthetic flag that usurps an unused a should-be-zero bit. + */ + if (is_blocking) + entry |=3D AVIC_PHYSICAL_ID_ENTRY_GA_LOG_INTR; + + svm->avic_physical_id_entry =3D entry; + spin_unlock_irqrestore(&svm->ir_list_lock, flags); } =20 @@ -957,10 +973,15 @@ void avic_vcpu_put(struct kvm_vcpu *vcpu) u64 entry =3D to_svm(vcpu)->avic_physical_id_entry; =20 /* Nothing to do if IsRunning =3D=3D '0' due to vCPU blocking. */ - if (!(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)) - return; + if (!(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)) { + if (WARN_ON_ONCE(!kvm_vcpu_is_blocking(vcpu))) + return; =20 - __avic_vcpu_put(vcpu, false); + if (!(WARN_ON_ONCE(!(entry & AVIC_PHYSICAL_ID_ENTRY_GA_LOG_INTR)))) + return; + } + + __avic_vcpu_put(vcpu, false, kvm_vcpu_is_blocking(vcpu)); } =20 void avic_refresh_virtual_apic_mode(struct kvm_vcpu *vcpu) @@ -997,7 +1018,7 @@ void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcp= u) if (kvm_vcpu_apicv_active(vcpu)) __avic_vcpu_load(vcpu, vcpu->cpu, true); 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charset="utf-8" Hack the IOMMU half of AMD device posted IRQ support to allow testing a decent chunk of the related code on systems with AVIC capable CPUs, but no IOMMU virtual APIC support. E.g. some Milan CPUs allow enabling AVIC even though it's not advertised as being supported, but the IOMMU unfortunately doesn't allow the same shenanigans. Not-signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- arch/x86/kvm/svm/avic.c | 76 ++++++++++++++++++++++++++++++++++++--- arch/x86/kvm/svm/svm.c | 2 ++ drivers/iommu/amd/init.c | 8 +++-- drivers/iommu/amd/iommu.c | 50 +++++++++++++++++++++++++- 4 files changed, 128 insertions(+), 8 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index 0d2a17a74be6..425674e1a04c 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -28,6 +28,8 @@ #include "irq.h" #include "svm.h" =20 +#include "../../../drivers/iommu/amd/amd_iommu_types.h" + /* * Encode the arbitrary VM ID and the vCPU's _index_ into the GATag so that * KVM can retrieve the correct vCPU from a GALog entry if an interrupt ca= n't @@ -141,11 +143,7 @@ static void avic_deactivate_vmcb(struct vcpu_svm *svm) svm_set_x2apic_msr_interception(svm, true); } =20 -/* Note: - * This function is called from IOMMU driver to notify - * SVM to schedule in a particular vCPU of a particular VM. - */ -int avic_ga_log_notifier(u32 ga_tag) +static struct kvm_vcpu *avic_ga_log_get_vcpu(u32 ga_tag) { unsigned long flags; struct kvm_svm *kvm_svm; @@ -165,6 +163,17 @@ int avic_ga_log_notifier(u32 ga_tag) } spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags); =20 + return vcpu; +} + +/* Note: + * This function is called from IOMMU driver to notify + * SVM to schedule in a particular vCPU of a particular VM. + */ +int avic_ga_log_notifier(u32 ga_tag) +{ + struct kvm_vcpu *vcpu =3D avic_ga_log_get_vcpu(ga_tag); + /* Note: * At this point, the IOMMU should have already set the pending * bit in the vAPIC backing page. So, we just need to schedule @@ -750,6 +759,8 @@ static void svm_ir_list_del(struct kvm_kernel_irqfd *ir= qfd) spin_unlock_irqrestore(&to_svm(vcpu)->ir_list_lock, flags); } =20 +extern struct amd_iommu_pi_data amd_iommu_fake_irte; + int avic_pi_update_irte(struct kvm_kernel_irqfd *irqfd, struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, struct kvm_kernel_irq_routing_entry *new, @@ -1055,6 +1066,58 @@ void avic_vcpu_unblocking(struct kvm_vcpu *vcpu) avic_vcpu_load(vcpu, vcpu->cpu); } =20 +static void avic_pi_handler(void) +{ + struct amd_iommu_pi_data pi; + struct kvm_vcpu *vcpu; + + memcpy(&pi, &amd_iommu_fake_irte, sizeof(pi)); + + if (!pi.is_guest_mode) { + pr_warn("IRQ %u arrived with !is_guest_mode\n", pi.vector); + return; + } + + vcpu =3D avic_ga_log_get_vcpu(pi.ga_tag); + if (!vcpu) { + pr_warn("No vCPU for IRQ %u\n", pi.vector); + return; + } + WARN_ON_ONCE(pi.vapic_addr << 12 !=3D avic_get_backing_page_address(to_sv= m(vcpu))); + + /* + * When updating a vCPU's IRTE, the fake posted IRQ can race with the + * IRTE update. Take ir_list_lock so that the IRQ can be processed + * atomically. In real hardware, the IOMMU will complete IRQ delivery + * before accepting the new IRTE. + */ + guard(spinlock_irqsave)(&to_svm(vcpu)->ir_list_lock); + + if (amd_iommu_fake_irte.ga_tag !=3D pi.ga_tag) { + WARN_ON_ONCE(amd_iommu_fake_irte.is_guest_mode); + return; + } + + memcpy(&pi, &amd_iommu_fake_irte, sizeof(pi)); + +#if 0 + pr_warn("In PI handler, guest =3D %u, cpu =3D %d, tag =3D %x, intr =3D %u= , vector =3D %u\n", + pi.is_guest_mode, pi.cpu, + pi.ga_tag, pi.ga_log_intr, pi.vector); +#endif + + if (!pi.is_guest_mode) + return; + + kvm_lapic_set_irr(pi.vector, vcpu->arch.apic); + smp_mb__after_atomic(); + + if (pi.cpu >=3D 0) + avic_ring_doorbell(vcpu); + else if (pi.ga_log_intr) + avic_ga_log_notifier(pi.ga_tag); +} + /* * Note: * - The module param avic enable both xAPIC and x2APIC mode. @@ -1107,5 +1170,8 @@ bool avic_hardware_setup(void) =20 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); =20 + pr_warn("Register AVIC PI wakeup handler\n"); + kvm_set_posted_intr_wakeup_handler(avic_pi_handler); + return true; } diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 71b52ad13577..b8adeb87e800 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -1122,6 +1122,8 @@ static void svm_hardware_unsetup(void) { int cpu; =20 + kvm_set_posted_intr_wakeup_handler(NULL); + sev_hardware_unsetup(); =20 for_each_possible_cpu(cpu) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index cb536d372b12..28cc8552ca95 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -2863,8 +2863,12 @@ static void enable_iommus_vapic(void) return; } =20 - if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) && - !check_feature(FEATURE_GAM_VAPIC)) { + if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) + return; + + if (!check_feature(FEATURE_GAM_VAPIC)) { + pr_warn("IOMMU lacks GAM_VAPIC, fudging IRQ posting\n"); + amd_iommu_irq_ops.capability |=3D (1 << IRQ_POSTING_CAP); amd_iommu_guest_ir =3D AMD_IOMMU_GUEST_IR_LEGACY_GA; return; } diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 27b03e718980..f2bd262330fa 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3775,6 +3775,15 @@ static const struct irq_domain_ops amd_ir_domain_ops= =3D { .deactivate =3D irq_remapping_deactivate, }; =20 +struct amd_iommu_pi_data amd_iommu_fake_irte; +EXPORT_SYMBOL_GPL(amd_iommu_fake_irte); + +static bool amd_iommu_fudge_pi(void) +{ + return irq_remapping_cap(IRQ_POSTING_CAP) && + !AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir); +} + static void __amd_iommu_update_ga(struct irte_ga *entry, int cpu, bool ga_log_intr) { @@ -3796,6 +3805,12 @@ int amd_iommu_update_ga(void *data, int cpu, bool ga= _log_intr) struct amd_ir_data *ir_data =3D (struct amd_ir_data *)data; struct irte_ga *entry =3D (struct irte_ga *) ir_data->entry; =20 + if (amd_iommu_fudge_pi()) { + amd_iommu_fake_irte.cpu =3D cpu; + amd_iommu_fake_irte.ga_log_intr =3D ga_log_intr; + return 0; + } + if (WARN_ON_ONCE(!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))) return -EINVAL; =20 @@ -3818,6 +3833,26 @@ int amd_iommu_activate_guest_mode(void *data, int cp= u, bool ga_log_intr) struct irte_ga *entry =3D (struct irte_ga *) ir_data->entry; u64 valid; =20 + if (amd_iommu_fudge_pi()) { + if (WARN_ON_ONCE(!entry->lo.fields_remap.valid)) + return -EINVAL; + + if (WARN_ON_ONCE(entry->lo.fields_remap.int_type !=3D APIC_DELIVERY_MODE= _FIXED)) + return -EINVAL; + + amd_iommu_fake_irte.cpu =3D cpu; + amd_iommu_fake_irte.vapic_addr =3D ir_data->ga_root_ptr; + amd_iommu_fake_irte.vector =3D ir_data->ga_vector; + amd_iommu_fake_irte.ga_tag =3D ir_data->ga_tag; + amd_iommu_fake_irte.ga_log_intr =3D ga_log_intr; + amd_iommu_fake_irte.is_guest_mode =3D true; + + entry->hi.fields.vector =3D POSTED_INTR_WAKEUP_VECTOR; + + return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid, + ir_data->irq_2_irte.index, entry); + } + if (WARN_ON_ONCE(!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))) return -EINVAL; =20 @@ -3849,12 +3884,18 @@ int amd_iommu_deactivate_guest_mode(void *data) struct irq_cfg *cfg =3D ir_data->cfg; u64 valid; =20 + if (amd_iommu_fudge_pi() && entry) { + memset(&amd_iommu_fake_irte, 0, sizeof(amd_iommu_fake_irte)); + goto fudge; + } + if (WARN_ON_ONCE(!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))) return -EINVAL; =20 if (!entry || !entry->lo.fields_vapic.guest_mode) return 0; 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Fri, 04 Apr 2025 12:41:42 -0700 (PDT) Reply-To: Sean Christopherson Date: Fri, 4 Apr 2025 12:39:22 -0700 In-Reply-To: <20250404193923.1413163-1-seanjc@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250404193923.1413163-1-seanjc@google.com> X-Mailer: git-send-email 2.49.0.504.g3bcea36a83-goog Message-ID: <20250404193923.1413163-68-seanjc@google.com> Subject: [PATCH 67/67] *** DO NOT MERGE *** KVM: selftests: WIP posted interrupts test From: Sean Christopherson To: Sean Christopherson , Paolo Bonzini , Joerg Roedel , David Woodhouse , Lu Baolu Cc: kvm@vger.kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, Maxim Levitsky , Joao Martins , David Matlack Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Signed-off-by: Sean Christopherson Tested-by: Sairaj Kodilkar --- tools/testing/selftests/kvm/Makefile.kvm | 2 + .../selftests/kvm/include/vfio_pci_util.h | 149 ++++++ .../selftests/kvm/include/x86/processor.h | 21 + .../testing/selftests/kvm/lib/vfio_pci_util.c | 201 ++++++++ tools/testing/selftests/kvm/mercury_device.h | 118 +++++ tools/testing/selftests/kvm/vfio_irq_test.c | 429 ++++++++++++++++++ 6 files changed, 920 insertions(+) create mode 100644 tools/testing/selftests/kvm/include/vfio_pci_util.h create mode 100644 tools/testing/selftests/kvm/lib/vfio_pci_util.c create mode 100644 tools/testing/selftests/kvm/mercury_device.h create mode 100644 tools/testing/selftests/kvm/vfio_irq_test.c diff --git a/tools/testing/selftests/kvm/Makefile.kvm b/tools/testing/selft= ests/kvm/Makefile.kvm index f773f8f99249..8f017b858d4b 100644 --- a/tools/testing/selftests/kvm/Makefile.kvm +++ b/tools/testing/selftests/kvm/Makefile.kvm @@ -15,6 +15,7 @@ LIBKVM +=3D lib/sparsebit.c LIBKVM +=3D lib/test_util.c LIBKVM +=3D lib/ucall_common.c LIBKVM +=3D lib/userfaultfd_util.c +LIBKVM +=3D lib/vfio_pci_util.c =20 LIBKVM_STRING +=3D lib/string_override.c =20 @@ -133,6 +134,7 @@ TEST_GEN_PROGS_x86 +=3D mmu_stress_test TEST_GEN_PROGS_x86 +=3D rseq_test TEST_GEN_PROGS_x86 +=3D set_memory_region_test TEST_GEN_PROGS_x86 +=3D steal_time +TEST_GEN_PROGS_x86 +=3D vfio_irq_test TEST_GEN_PROGS_x86 +=3D kvm_binary_stats_test TEST_GEN_PROGS_x86 +=3D system_counter_offset_test TEST_GEN_PROGS_x86 +=3D pre_fault_memory_test diff --git a/tools/testing/selftests/kvm/include/vfio_pci_util.h b/tools/te= sting/selftests/kvm/include/vfio_pci_util.h new file mode 100644 index 000000000000..2a697dcb741e --- /dev/null +++ b/tools/testing/selftests/kvm/include/vfio_pci_util.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2022, Google LLC. + */ + +#ifndef SELFTEST_KVM_VFIO_UTIL_H +#define SELFTEST_KVM_VFIO_UTIL_H + +#include +#include + +#include "kvm_util.h" +#include "test_util.h" + +struct vfio_pci_dev { + int fd; + int group_fd; + int container_fd; +}; + +struct vfio_pci_dev *__vfio_pci_init(const char *bdf, unsigned long iommu_= type); +void vfio_pci_free(struct vfio_pci_dev *dev); + +static inline struct vfio_pci_dev *vfio_pci_init(const char *bdf) +{ + return __vfio_pci_init(bdf, VFIO_TYPE1v2_IOMMU); +} + +#define __vfio_ioctl(vfio_fd, cmd, arg) \ +({ \ + __kvm_ioctl(vfio_fd, cmd, arg); \ +}) + +#define vfio_ioctl(vfio_fd, cmd, arg) \ +({ \ + int ret =3D __vfio_ioctl(vfio_fd, cmd, arg); \ + \ + TEST_ASSERT(!ret, __KVM_IOCTL_ERROR(#cmd, ret)); \ +}) + +static inline uint32_t vfio_pci_get_nr_irqs(struct vfio_pci_dev *dev, + uint32_t irq_type) +{ + struct vfio_irq_info irq_info =3D { + .argsz =3D sizeof(struct vfio_irq_info), + .index =3D irq_type, + }; + + vfio_ioctl(dev->fd, VFIO_DEVICE_GET_IRQ_INFO, &irq_info); + + TEST_ASSERT(irq_info.flags & VFIO_IRQ_INFO_EVENTFD, + "eventfd signalling unsupported by IRQ type '%u'", irq_type); + return irq_info.count; +} + +static inline uint32_t vfio_pci_get_nr_msi_irqs(struct vfio_pci_dev *dev) +{ + return vfio_pci_get_nr_irqs(dev, VFIO_PCI_MSI_IRQ_INDEX); +} + +static inline uint32_t vfio_pci_get_nr_msix_irqs(struct vfio_pci_dev *dev) +{ + return vfio_pci_get_nr_irqs(dev, VFIO_PCI_MSIX_IRQ_INDEX); +} + +static inline void __vfio_pci_irq_eventfd(struct vfio_pci_dev *dev, int ev= entfd, + uint32_t irq_type, uint32_t set) +{ + struct { + struct vfio_irq_set vfio; + uint32_t eventfd; + } buffer =3D {}; + + memset(&buffer, 0, sizeof(buffer)); + buffer.vfio.argsz =3D sizeof(buffer); + buffer.vfio.flags =3D set | VFIO_IRQ_SET_ACTION_TRIGGER; + buffer.vfio.index =3D irq_type; + buffer.vfio.count =3D 1; + buffer.eventfd =3D eventfd; + + vfio_ioctl(dev->fd, VFIO_DEVICE_SET_IRQS, &buffer.vfio); +} + +static inline void vfio_pci_assign_irq_eventfd(struct vfio_pci_dev *dev, + int eventfd, uint32_t irq_type) +{ + __vfio_pci_irq_eventfd(dev, eventfd, irq_type, VFIO_IRQ_SET_DATA_EVENTFD); +} + +static inline void vfio_pci_assign_msix(struct vfio_pci_dev *dev, int even= tfd) +{ + vfio_pci_assign_irq_eventfd(dev, eventfd, VFIO_PCI_MSIX_IRQ_INDEX); +} + +static inline void vfio_pci_release_irq_eventfds(struct vfio_pci_dev *dev, + uint32_t irq_type) +{ + struct vfio_irq_set vfio =3D { + .argsz =3D sizeof(struct vfio_irq_set), + .flags =3D VFIO_IRQ_SET_DATA_NONE | VFIO_IRQ_SET_ACTION_TRIGGER, + .index =3D irq_type, + .count =3D 0, + }; + + vfio_ioctl(dev->fd, VFIO_DEVICE_SET_IRQS, &vfio); +} + +static inline void vfio_pci_release_msix(struct vfio_pci_dev *dev) +{ + vfio_pci_release_irq_eventfds(dev, VFIO_PCI_MSIX_IRQ_INDEX); +} + +static inline void vfio_pci_send_irq_eventfd(struct vfio_pci_dev *dev, + int eventfd, uint32_t irq_type) +{ + __vfio_pci_irq_eventfd(dev, eventfd, irq_type, VFIO_IRQ_SET_DATA_NONE); +} + +static inline void vfio_pci_send_msix(struct vfio_pci_dev *dev, int eventf= d) +{ + vfio_pci_send_irq_eventfd(dev, eventfd, VFIO_PCI_MSIX_IRQ_INDEX); +} + +void *vfio_pci_map_bar(struct vfio_pci_dev *dev, unsigned int bar_idx, + uint64_t *size); + +void vfio_pci_read_config_data(struct vfio_pci_dev *dev, size_t offset, + size_t size, void *data); + +static inline uint16_t vfio_pci_config_read_u16(struct vfio_pci_dev *dev, + size_t offset) +{ + uint16_t val; + + vfio_pci_read_config_data(dev, offset, sizeof(val), &val); + return le16toh(val); +} + +static inline uint16_t vfio_pci_get_vendor_id(struct vfio_pci_dev *dev) +{ + return vfio_pci_config_read_u16(dev, PCI_VENDOR_ID); +} + +static inline uint16_t vfio_pci_get_device_id(struct vfio_pci_dev *dev) +{ + return vfio_pci_config_read_u16(dev, PCI_DEVICE_ID); +} + +#endif /* SELFTEST_KVM_VFIO_UTIL_H */ diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/te= sting/selftests/kvm/include/x86/processor.h index 32ab6ca7ec32..251dcc074503 100644 --- a/tools/testing/selftests/kvm/include/x86/processor.h +++ b/tools/testing/selftests/kvm/include/x86/processor.h @@ -19,6 +19,27 @@ #include "kvm_util.h" #include "ucall_common.h" =20 + +static inline void writel(uint32_t val, volatile void *addr) +{ + *(volatile uint32_t *)addr =3D val; +} + +static inline uint32_t readl(volatile void *addr) +{ + return *(volatile uint32_t *)addr; +} + +static inline void writeq(uint64_t val, volatile void *addr) +{ + *(volatile uint64_t *)addr =3D val; +} + +static inline uint64_t readq(volatile void *addr) +{ + return *(volatile uint64_t *)addr; +} + extern bool host_cpu_is_intel; extern bool host_cpu_is_amd; extern uint64_t guest_tsc_khz; diff --git a/tools/testing/selftests/kvm/lib/vfio_pci_util.c b/tools/testin= g/selftests/kvm/lib/vfio_pci_util.c new file mode 100644 index 000000000000..878d91be2212 --- /dev/null +++ b/tools/testing/selftests/kvm/lib/vfio_pci_util.c @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "test_util.h" +#include "kvm_util.h" +#include "vfio_pci_util.h" + +#define VFIO_DEV_PATH "/dev/vfio/vfio" +#define PCI_SYSFS_PATH "/sys/bus/pci/devices/" + +void *vfio_pci_map_bar(struct vfio_pci_dev *dev, unsigned int bar_idx, + uint64_t *size) +{ + struct vfio_region_info info =3D { + .argsz =3D sizeof(struct vfio_region_info), + .index =3D bar_idx, + }; + int fd =3D dev->fd; + void *bar; + int prot; + + TEST_ASSERT(bar_idx <=3D VFIO_PCI_BAR5_REGION_INDEX, + "Invalid BAR index: %d", bar_idx); + + /* Currently only support the cases where the BAR can be mmap-ed */ + vfio_ioctl(fd, VFIO_DEVICE_GET_REGION_INFO, &info); + TEST_ASSERT(info.flags & VFIO_REGION_INFO_FLAG_MMAP, + "BAR%d doesn't support mmap", bar_idx); + + TEST_ASSERT(info.flags & VFIO_REGION_INFO_FLAG_READ, + "BAR%d doesn't support read?", bar_idx); + + prot =3D PROT_READ; + if (info.flags & VFIO_REGION_INFO_FLAG_WRITE) + prot |=3D PROT_WRITE; + + bar =3D mmap(NULL, info.size, prot, MAP_FILE | MAP_SHARED, fd, info.offse= t); + TEST_ASSERT(bar !=3D MAP_FAILED, "mmap(BAR%d) failed", bar_idx); + + *size =3D info.size; + return bar; +} + +/* + * Read the PCI config space data + * + * Input Args: + * vfio_pci: Pointer to struct vfio_pci_dev + * config: The config space field's offset to read from (eg: PCI_VENDOR_= ID) + * size: The size to read from the config region (could be one or more f= ields). + * data: Pointer to the region where the read data is to be copied into + * + * The data returned is in little-endian format, which is the standard fo= r PCI config space. + */ +void vfio_pci_read_config_data(struct vfio_pci_dev *dev, size_t offset, + size_t size, void *data) +{ + struct vfio_region_info info =3D { + .argsz =3D sizeof(struct vfio_region_info), + .index =3D VFIO_PCI_CONFIG_REGION_INDEX, + }; + int ret; + + vfio_ioctl(dev->fd, VFIO_DEVICE_GET_REGION_INFO, &info); + + TEST_ASSERT(offset + size <=3D PCI_CFG_SPACE_EXP_SIZE, + "Requested config (%lu) and size (%lu) is out of bounds (%u)", + offset, size, PCI_CFG_SPACE_EXP_SIZE); + + ret =3D pread(dev->fd, data, size, info.offset + offset); + TEST_ASSERT(ret =3D=3D size, "Failed to read the PCI config: 0x%lx\n", of= fset); +} + +static unsigned int vfio_pci_get_group_from_dev(const char *bdf) +{ + char dev_iommu_group_path[PATH_MAX] =3D {0}; + unsigned int pci_dev_sysfs_path_len; + char *pci_dev_sysfs_path; + unsigned int group; + int ret; + + pci_dev_sysfs_path_len =3D strlen(PCI_SYSFS_PATH) + strlen("DDDD:BB:DD.F/= iommu_group") + 1; + + pci_dev_sysfs_path =3D calloc(1, pci_dev_sysfs_path_len); + TEST_ASSERT(pci_dev_sysfs_path, "Insufficient memory for pci dev sysfs pa= th"); + + snprintf(pci_dev_sysfs_path, pci_dev_sysfs_path_len, + "%s%s/iommu_group", PCI_SYSFS_PATH, bdf); + + ret =3D readlink(pci_dev_sysfs_path, dev_iommu_group_path, + sizeof(dev_iommu_group_path)); + TEST_ASSERT(ret !=3D -1, "Failed to get IOMMU group for device: %s", bdf); + + ret =3D sscanf(basename(dev_iommu_group_path), "%u", &group); + TEST_ASSERT(ret =3D=3D 1, "Failed to get IOMMU group for device: %s", bdf= ); + + free(pci_dev_sysfs_path); + return group; +} + +static void vfio_pci_setup_group(struct vfio_pci_dev *dev, const char *bdf) +{ + char group_path[32]; + struct vfio_group_status group_status =3D { + .argsz =3D sizeof(group_status), + }; + int group; + + group =3D vfio_pci_get_group_from_dev(bdf); + snprintf(group_path, sizeof(group_path), "/dev/vfio/%d", group); + + dev->group_fd =3D open(group_path, O_RDWR); + TEST_ASSERT(dev->group_fd >=3D 0, + "Failed to open the VFIO group %d for device: %s\n", group, bdf); + + __vfio_ioctl(dev->group_fd, VFIO_GROUP_GET_STATUS, &group_status); + TEST_ASSERT(group_status.flags & VFIO_GROUP_FLAGS_VIABLE, + "Group %d for device %s not viable. Ensure all devices are bound to= vfio-pci", + group, bdf); + + vfio_ioctl(dev->group_fd, VFIO_GROUP_SET_CONTAINER, &dev->container_fd); +} + +static void vfio_pci_set_iommu(struct vfio_pci_dev *dev, unsigned long iom= mu_type) +{ + TEST_ASSERT_EQ(__vfio_ioctl(dev->container_fd, VFIO_CHECK_EXTENSION, (voi= d *)iommu_type), 1); + vfio_ioctl(dev->container_fd, VFIO_SET_IOMMU, (void *)iommu_type); +} + +static void vfio_pci_open_device(struct vfio_pci_dev *dev, const char *bdf) +{ + struct vfio_device_info dev_info =3D { + .argsz =3D sizeof(dev_info), + }; + + dev->fd =3D __vfio_ioctl(dev->group_fd, VFIO_GROUP_GET_DEVICE_FD, bdf); + TEST_ASSERT(dev->fd >=3D 0, "Failed to get the device fd\n"); + + vfio_ioctl(dev->fd, VFIO_DEVICE_GET_INFO, &dev_info); + + TEST_ASSERT(!(dev_info.flags & VFIO_DEVICE_FLAGS_RESET), + "If VFIO tries to reset the VF, it will fail."); + + /* Require at least all BAR regions and the config space. */ + TEST_ASSERT(dev_info.num_regions >=3D VFIO_PCI_CONFIG_REGION_INDEX, + "Required number regions not supported (%d) for device: %s", + dev_info.num_regions, bdf); + + /* Check for at least VFIO_PCI_MSIX_IRQ_INDEX irqs */ + TEST_ASSERT(dev_info.num_irqs >=3D VFIO_PCI_MSIX_IRQ_INDEX, + "MSI-X IRQs (%d) not supported for device: %s", + dev_info.num_irqs, bdf); +} + +/* bdf: PCI device's Domain:Bus:Device:Function in "DDDD:BB:DD.F" format */ +struct vfio_pci_dev *__vfio_pci_init(const char *bdf, unsigned long iommu_= type) +{ + struct vfio_pci_dev *dev; + int vfio_version; + + TEST_ASSERT(bdf, "PCI BDF not supplied\n"); + + dev =3D calloc(1, sizeof(*dev)); + TEST_ASSERT(dev, "Insufficient memory for vfio_pci_dev"); + + dev->container_fd =3D open_path_or_exit(VFIO_DEV_PATH, O_RDWR); + + vfio_version =3D __vfio_ioctl(dev->container_fd, VFIO_GET_API_VERSION, NU= LL); + TEST_REQUIRE(vfio_version =3D=3D VFIO_API_VERSION); + + + vfio_pci_setup_group(dev, bdf); + vfio_pci_set_iommu(dev, iommu_type); + vfio_pci_open_device(dev, bdf); + + return dev; +} + +void vfio_pci_free(struct vfio_pci_dev *dev) +{ + close(dev->fd); + vfio_ioctl(dev->group_fd, VFIO_GROUP_UNSET_CONTAINER, NULL); + + close(dev->group_fd); + close(dev->container_fd); + + free(dev); +} diff --git a/tools/testing/selftests/kvm/mercury_device.h b/tools/testing/s= elftests/kvm/mercury_device.h new file mode 100644 index 000000000000..fd4a3a5bac25 --- /dev/null +++ b/tools/testing/selftests/kvm/mercury_device.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2022, Google LLC. + */ + +#ifndef SELFTEST_KVM_MERCURY_DEVICE_H +#define SELFTEST_KVM_MERCURY_DEVICE_H + +#include "processor.h" +#include "test_util.h" + +#define MERCURY_VENDOR_ID 0x1ae0 +#define MERCURY_DEVICE_ID 0x0050 + +/* The base registers of the mercury device begin at the below offset from= BAR0 */ +#define MERCURY_BASE_OFFSET (768 * 1024) + +#define MERCURY_MSIX_VECTOR 0 +#define MERCURY_MSIX_COUNT 1 /* Currently, only 1 vector is assigned to me= rcury */ + +#define MERCURY_DMA_MAX_BUF_SIZE_BYTES SZ_8K +#define MERCURY_DMA_MEMCPY_MAX_BUF_SIZE_BYTES SZ_1G + +/* Mercury device accepts the DMA size as double-word (4-bytes) */ +#define MERCURY_DMA_SIZE_STRIDE 4 + +#define MERCURY_ABI_VERSION 0 + +/* Register Offsets relative to MERCURY_BASE_OFFSET */ +/* Unless otherwise specified, all the registers are 32-bits */ +#define MERCURY_REG_VERSION 0x0 /* Read-only */ +#define MERCURY_REG_COMMAND 0x04 /* Write-only */ +#define MERCURY_REG_STATUS 0x08 /* Read-only, 64-bit register */ +#define MERCURY_REG_DMA_SRC_ADDR 0x10 /* Read/Write, 64-bit register */ +#define MERCURY_REG_DMA_DEST_ADDR 0x18 /* Read/Write, 64-bit register */ +#define MERCURY_REG_DMA_DW_LEN 0x20 /* Read/Write */ +#define MERCURY_REG_SCRATCH_REG0 0x24 /* Read/Write */ +#define MERCURY_REG_SCRATCH_REG1 0x1000 /* Read/Write */ + +/* Bit positions of the STATUS register */ +enum mercury_status_bit { + MERCURY_STATUS_BIT_READY =3D 0, + MERCURY_STATUS_BIT_DMA_FROM_DEV_COMPLETE =3D 1, + MERCURY_STATUS_BIT_DMA_TO_DEV_COMPLETE =3D 2, + MERCURY_STATUS_BIT_DMA_MEMCPY_COMPLETE =3D 3, + MERCURY_STATUS_BIT_FORCE_INTERRUPT =3D 4, + MERCURY_STATUS_BIT_INVAL_DMA_SIZE =3D 5, + MERCURY_STATUS_BIT_DMA_ERROR =3D 6, + MERCURY_STATUS_BIT_CMD_ERR_INVAL_CMD =3D 7, + MERCURY_STATUS_BIT_CMD_ERR_DEV_NOT_READY =3D 8, +}; + +/* List of mercury commands that can be written into MERCURY_REG_COMMAND r= egister */ +enum mercury_command { + MERCURY_COMMAND_RESET =3D 0, + MERCURY_COMMAND_TRIGGER_DMA_FROM_DEV =3D 1, + MERCURY_COMMAND_TRIGGER_DMA_TO_DEV =3D 2, + MERCURY_COMMAND_TRIGGER_DMA_MEMCPY =3D 3, + MERCURY_COMMAND_FORCE_INTERRUPT =3D 4, +}; + +static inline void mercury_write_reg64(void *bar0, uint32_t reg_off, uint6= 4_t val) +{ + void *reg =3D bar0 + MERCURY_BASE_OFFSET + reg_off; + + writeq(val, reg); +} + +static inline void mercury_write_reg32(void *bar0, uint32_t reg_off, uint3= 2_t val) +{ + void *reg =3D bar0 + MERCURY_BASE_OFFSET + reg_off; + + writel(val, reg); +} + +static inline uint32_t mercury_read_reg32(void *bar0, uint32_t reg_off) +{ + void *reg =3D bar0 + MERCURY_BASE_OFFSET + reg_off; + + return readl(reg); +} + +static inline uint64_t mercury_read_reg64(void *bar0, uint32_t reg_off) +{ + void *reg =3D bar0 + MERCURY_BASE_OFFSET + reg_off; + + return readq(reg); +} + +static inline uint64_t mercury_get_status(void *bar0) +{ + return mercury_read_reg64(bar0, MERCURY_REG_STATUS); +} + +static inline void mercury_issue_command(void *bar0, enum mercury_command = cmd) +{ + mercury_write_reg32(bar0, MERCURY_REG_COMMAND, cmd); +} + +static inline void mercury_issue_reset(void *bar0) +{ + mercury_issue_command(bar0, MERCURY_COMMAND_RESET); +} + +static inline void mercury_force_irq(void *bar0) +{ + mercury_issue_command(bar0, MERCURY_COMMAND_FORCE_INTERRUPT); +} + +static inline void mercury_set_dma_size(void *bar0, size_t sz_bytes) +{ + /* Convert the DMA size from bytes to DWORDS, as accepted by the device */ + size_t sz_dwords =3D sz_bytes / MERCURY_DMA_SIZE_STRIDE; + + mercury_write_reg32(bar0, MERCURY_REG_DMA_DW_LEN, sz_dwords); +} + +#endif /* SELFTEST_KVM_MERCURY_DEVICE_H */ diff --git a/tools/testing/selftests/kvm/vfio_irq_test.c b/tools/testing/se= lftests/kvm/vfio_irq_test.c new file mode 100644 index 000000000000..1cdc6fee9e9a --- /dev/null +++ b/tools/testing/selftests/kvm/vfio_irq_test.c @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "apic.h" +#include "processor.h" +#include "test_util.h" +#include "kvm_util.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "vfio_pci_util.h" +#include "mercury_device.h" + +#define MERCURY_GSI 32 +#define MERCURY_IRQ_VECTOR 0x80 + +#define MERCURY_BAR0_GPA 0xc0000000ul +#define MERCURY_BAR0_SLOT 10 + +/* Shared variables. */ +static bool do_guest_irq =3D true; + +/* Guest-only variables, shared across vCPUs. */ +static int irqs_received; +static int irqs_sent; + +/* Host-only variables, shared across threads. */ +static cpu_set_t possible_mask; +static int min_cpu, max_cpu; +static bool done; +static struct kvm_vcpu *target_vcpu; +static sem_t do_irq; + +static bool x2apic; + +static void guest_irq_handler(struct ex_regs *regs) +{ + WRITE_ONCE(irqs_received, irqs_received + 1); + + if (x2apic) + x2apic_write_reg(APIC_EOI, 0); + else + xapic_write_reg(APIC_EOI, 0); +} + +static void guest_nmi_handler(struct ex_regs *regs) +{ + WRITE_ONCE(irqs_received, irqs_received + 1); +} + +#define GUEST_VERIFY_IRQS() \ +do { \ + int __received; \ + \ + __received =3D READ_ONCE(irqs_received); \ + __GUEST_ASSERT(__received =3D=3D irqs_sent, \ + "Sent %u IRQ, received %u IRQs", irqs_sent, __received);\ +} while (0) + +#define GUEST_WAIT_FOR_IRQ() \ +do { \ + safe_halt(); \ + GUEST_VERIFY_IRQS(); \ + cli(); \ +} while (0) + +static void guest_code(uint32_t vcpu_id) +{ + /* GPA is identity mapped. */ + void *mercury_bar0 =3D (void *)MERCURY_BAR0_GPA; + uint64_t status; + int i; + + cli(); + + if (x2apic) { + x2apic_enable(); + GUEST_ASSERT(x2apic_read_reg(APIC_ID) =3D=3D vcpu_id); + } else { + xapic_enable(); + GUEST_ASSERT(xapic_read_reg(APIC_ID) >> 24 =3D=3D vcpu_id); + } + + if (vcpu_id =3D=3D 0) { + irqs_sent++; + GUEST_ASSERT(READ_ONCE(do_guest_irq)); + mercury_issue_reset(mercury_bar0); + GUEST_WAIT_FOR_IRQ(); + + status =3D mercury_get_status(mercury_bar0); + __GUEST_ASSERT(status & BIT(MERCURY_STATUS_BIT_READY), + "Expected device ready after reset"); + GUEST_SYNC(irqs_received); + } + + for ( ; !READ_ONCE(done); ) { + irqs_sent++; + if (READ_ONCE(do_guest_irq)) + mercury_force_irq(mercury_bar0); + GUEST_WAIT_FOR_IRQ(); + GUEST_SYNC(irqs_received); + } + + sti_nop(); + + for (i =3D 0; i < 1000; i++) { + mercury_force_irq(mercury_bar0); + cpu_relax(); + } + + GUEST_VERIFY_IRQS(); + GUEST_SYNC(irqs_received); +} + +static void *irq_worker(void *mercury_bar0) +{ + struct kvm_vcpu *vcpu; + + for (;;) { + sem_wait(&do_irq); + + if (READ_ONCE(done)) + break; + + vcpu =3D READ_ONCE(target_vcpu); + while (!vcpu_get_stat(vcpu, blocking)) + cpu_relax(); + + mercury_force_irq(mercury_bar0); + } + return NULL; +} + +static int next_cpu(int cpu) +{ + /* + * Advance to the next CPU, skipping those that weren't in the original + * affinity set. Sadly, there is no CPU_SET_FOR_EACH, and cpu_set_t's + * data storage is considered as opaque. Note, if this task is pinned + * to a small set of discontiguous CPUs, e.g. 2 and 1023, this loop will + * burn a lot cycles and the test will take longer than normal to + * complete. + */ + do { + cpu++; + if (cpu > max_cpu) { + cpu =3D min_cpu; + TEST_ASSERT(CPU_ISSET(cpu, &possible_mask), + "Min CPU =3D %d must always be usable", cpu); + break; + } + } while (!CPU_ISSET(cpu, &possible_mask)); + + return cpu; +} + +static void *migration_worker(void *__guest_tid) +{ + pid_t guest_tid =3D (pid_t)(unsigned long)__guest_tid; + cpu_set_t allowed_mask; + int r, i, cpu; + + CPU_ZERO(&allowed_mask); + + for (i =3D 0, cpu =3D min_cpu; !READ_ONCE(done); i++, cpu =3D next_cpu(cp= u)) { + CPU_SET(cpu, &allowed_mask); + + r =3D sched_setaffinity(guest_tid, sizeof(allowed_mask), &allowed_mask); + TEST_ASSERT(!r, "sched_setaffinity failed, errno =3D %d (%s)", + errno, strerror(errno)); + + CPU_CLR(cpu, &allowed_mask); + + usleep((i % 10) + 10); + } + return NULL; +} + +static void calc_min_max_cpu(void) +{ + int i, cnt, nproc; + + TEST_REQUIRE(CPU_COUNT(&possible_mask) >=3D 2); + + /* + * CPU_SET doesn't provide a FOR_EACH helper, get the min/max CPU that + * this task is affined to in order to reduce the time spent querying + * unusable CPUs, e.g. if this task is pinned to a small percentage of + * total CPUs. + */ + nproc =3D get_nprocs_conf(); + min_cpu =3D -1; + max_cpu =3D -1; + cnt =3D 0; + + for (i =3D 0; i < nproc; i++) { + if (!CPU_ISSET(i, &possible_mask)) + continue; + if (min_cpu =3D=3D -1) + min_cpu =3D i; + max_cpu =3D i; + cnt++; + } + + __TEST_REQUIRE(cnt >=3D 2, "Only one usable CPU, task migration not possi= ble"); +} + +static void sanity_check_mercury_device(struct vfio_pci_dev *dev, void *ba= r0) +{ + uint16_t vendor_id, device_id; + uint32_t version; + + vendor_id =3D vfio_pci_get_vendor_id(dev); + device_id =3D vfio_pci_get_device_id(dev); + + TEST_ASSERT(vendor_id =3D=3D MERCURY_VENDOR_ID && + device_id =3D=3D MERCURY_DEVICE_ID, + "Mercury vendor-id/device-id mismatch. " + "Expected vendor: 0x%04x, device: 0x%04x. " + "Got vendor: 0x%04x, device: 0x%04x", + MERCURY_VENDOR_ID, MERCURY_DEVICE_ID, + vendor_id, device_id); + + version =3D mercury_read_reg32(bar0, MERCURY_REG_VERSION); + TEST_ASSERT_EQ(version, MERCURY_ABI_VERSION); +} + +static void set_empty_routing(struct kvm_vm *vm, struct kvm_irq_routing *r= outing) +{ + routing->nr =3D 0; + routing->entries[0].gsi =3D MERCURY_GSI; + routing->entries[0].type =3D KVM_IRQ_ROUTING_IRQCHIP; + routing->entries[0].flags =3D 0; + routing->entries[0].u.msi.address_lo =3D 0; + routing->entries[0].u.msi.address_hi =3D 0; + routing->entries[0].u.msi.data =3D 0xfe; + vm_ioctl(vm, KVM_SET_GSI_ROUTING, routing); +} + +static void set_gsi_dest(struct kvm_vcpu *vcpu, struct kvm_irq_routing *ro= uting, + bool do_nmi) +{ + routing->nr =3D 1; + routing->entries[0].gsi =3D MERCURY_GSI; + routing->entries[0].type =3D KVM_IRQ_ROUTING_MSI; + routing->entries[0].flags =3D 0; + routing->entries[0].u.msi.address_lo =3D (vcpu->id << 12); + routing->entries[0].u.msi.address_hi =3D 0; + if (do_nmi) + routing->entries[0].u.msi.data =3D NMI_VECTOR | (4 << 8); + else + routing->entries[0].u.msi.data =3D MERCURY_IRQ_VECTOR; + vm_ioctl(vcpu->vm, KVM_SET_GSI_ROUTING, routing); +} + +static void vcpu_run_and_verify(struct kvm_vcpu *vcpu, int nr_irqs) +{ + struct ucall uc; + + vcpu_run(vcpu); + TEST_ASSERT_EQ(get_ucall(vcpu, &uc), UCALL_SYNC); + TEST_ASSERT_EQ(uc.args[1], nr_irqs); +} + +int main(int argc, char *argv[]) +{ + bool migrate =3D false, nmi =3D false, async =3D false, empty =3D false; + pthread_t migration_thread, irq_thread; + struct kvm_irq_routing *routing; + struct vfio_pci_dev *dev; + struct kvm_vcpu *vcpus[2]; + int opt, r, eventfd, i; + int nr_irqs =3D 10000; + struct kvm_vm *vm; + uint64_t bar_size; + char *bdf =3D NULL; + void *bar; + + sem_init(&do_irq, 0, 0); + + while ((opt =3D getopt(argc, argv, "had:ei:mnx")) !=3D -1) { + switch (opt) { + case 'a': + async =3D true; + break; + case 'd': + bdf =3D strdup(optarg); + break; + case 'e': + empty =3D true; + break; + case 'i': + nr_irqs =3D atoi_positive("Number of IRQs", optarg); + break; + case 'm': + migrate =3D true; + break; + case 'n': + nmi =3D true; + break; + case 'x': + x2apic =3D false; + break; + case 'h': + default: + pr_info("Usage: %s [-h] <-d pci-bdf>\n\n", argv[0]); + pr_info("\t-d: PCI Domain, Bus, Device, Function in the format DDDD:BB:= DD.F\n"); + pr_info("\t-h: print this help screen\n"); + exit(KSFT_SKIP); + } + } + + __TEST_REQUIRE(bdf, "Required argument -d missing"); + + dev =3D vfio_pci_init(bdf); + bar =3D vfio_pci_map_bar(dev, VFIO_PCI_BAR0_REGION_INDEX, &bar_size); + sanity_check_mercury_device(dev, bar); + + vm =3D vm_create_with_vcpus(ARRAY_SIZE(vcpus), guest_code, vcpus); + vm_install_exception_handler(vm, MERCURY_IRQ_VECTOR, guest_irq_handler); + vm_install_exception_handler(vm, NMI_VECTOR, guest_nmi_handler); + + vcpu_args_set(vcpus[0], 1, 0); + vcpu_args_set(vcpus[1], 1, 1); + + virt_pg_map(vm, APIC_DEFAULT_GPA, APIC_DEFAULT_GPA); + + vm_set_user_memory_region(vm, MERCURY_BAR0_SLOT, 0, MERCURY_BAR0_GPA, + bar_size, bar); + virt_map(vm, MERCURY_BAR0_GPA, MERCURY_BAR0_GPA, + vm_calc_num_guest_pages(VM_MODE_DEFAULT, bar_size)); + + routing =3D kvm_gsi_routing_create(); + + eventfd =3D kvm_new_eventfd(); + vfio_pci_assign_msix(dev, eventfd); + kvm_assign_irqfd(vm, MERCURY_GSI, eventfd); + + r =3D sched_getaffinity(0, sizeof(possible_mask), &possible_mask); + TEST_ASSERT(!r, "sched_getaffinity failed, errno =3D %d (%s)", errno, + strerror(errno)); + + if (migrate) { + calc_min_max_cpu(); + + pthread_create(&migration_thread, NULL, migration_worker, + (void *)(unsigned long)syscall(SYS_gettid)); + } + + if (nmi || async) + pthread_create(&irq_thread, NULL, irq_worker, bar); + + set_gsi_dest(vcpus[0], routing, false); + vcpu_run_and_verify(vcpus[0], 1); + +#if 0 + /* + * Hack if the user wants to manually mess with interrupt routing while + * the test is running, e.g. by modifying smp_affinity in the host. + */ + for (i =3D 1; i < nr_irqs; i++) { + usleep(1000 * 1000); + vcpu_run_and_verify(vcpus[0], i + 1); + } +#endif + + for (i =3D 1; i < nr_irqs; i++) { + struct kvm_vcpu *vcpu =3D vcpus[!!(i & BIT(1))]; + const bool do_nmi =3D nmi && (i & BIT(2)); + const bool do_empty =3D empty && (i & BIT(3)); + const bool do_async =3D nmi || async; + + if (do_empty) + set_empty_routing(vm, routing); + + set_gsi_dest(vcpu, routing, do_nmi); + + WRITE_ONCE(do_guest_irq, !do_async); + sync_global_to_guest(vm, do_guest_irq); + + if (do_async) { + WRITE_ONCE(target_vcpu, vcpu); + sem_post(&do_irq); + } + + vcpu_run_and_verify(vcpu, i + 1); + } + + WRITE_ONCE(done, true); + sync_global_to_guest(vm, done); + sem_post(&do_irq); + + for (i =3D 0; empty && i < ARRAY_SIZE(vcpus); i++) { + struct kvm_vcpu *vcpu =3D vcpus[i]; + + if (!i) + set_gsi_dest(vcpu, routing, false); + set_empty_routing(vm, routing); + vcpu_run_and_verify(vcpu, nr_irqs); + } + + set_gsi_dest(vcpus[0], routing, false); + + if (migrate) + pthread_join(migration_thread, NULL); + + if (nmi || async) + pthread_join(irq_thread, NULL); + + r =3D munmap(bar, bar_size); + TEST_ASSERT(!r, __KVM_SYSCALL_ERROR("munmap()", r)); + + vfio_pci_free(dev); + + return 0; +} --=20 2.49.0.504.g3bcea36a83-goog