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Fri, 04 Apr 2025 04:57:00 -0700 (PDT) From: Krzysztof Kozlowski Date: Fri, 04 Apr 2025 13:56:57 +0200 Subject: [PATCH 1/5] clk: meson: Do not enable by default during compile testing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250404-kconfig-defaults-clk-v1-1-4d2df5603332@linaro.org> References: <20250404-kconfig-defaults-clk-v1-0-4d2df5603332@linaro.org> In-Reply-To: <20250404-kconfig-defaults-clk-v1-0-4d2df5603332@linaro.org> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Maxime Coquelin , Alexandre Torgue , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , =?utf-8?q?Emilio_L=C3=B3pez?= Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-sunxi@lists.linux.dev, Krzysztof Kozlowski X-Mailer: b4 0.14.2 Enabling the compile test should not cause automatic enabling of all drivers. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Martin Blumenstingl --- drivers/clk/meson/Kconfig | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index be2e3a5f83363b07cdcec2601acf15780ff24892..ff003dc5ab20d904c91fc34c701= ba499a11d0b63 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -55,7 +55,7 @@ config COMMON_CLK_MESON_CPU_DYNDIV config COMMON_CLK_MESON8B bool "Meson8 SoC Clock controller support" depends on ARM - default y + default ARCH_MESON select COMMON_CLK_MESON_REGMAP select COMMON_CLK_MESON_CLKC_UTILS select COMMON_CLK_MESON_MPLL @@ -70,7 +70,7 @@ config COMMON_CLK_MESON8B config COMMON_CLK_GXBB tristate "GXBB and GXL SoC clock controllers support" depends on ARM64 - default y + default ARCH_MESON select COMMON_CLK_MESON_REGMAP select COMMON_CLK_MESON_DUALDIV select COMMON_CLK_MESON_VID_PLL_DIV @@ -86,7 +86,7 @@ config COMMON_CLK_GXBB config COMMON_CLK_AXG tristate "AXG SoC clock controllers support" depends on ARM64 - default y + default ARCH_MESON select COMMON_CLK_MESON_REGMAP select COMMON_CLK_MESON_DUALDIV select COMMON_CLK_MESON_MPLL @@ -136,7 +136,7 @@ config COMMON_CLK_A1_PERIPHERALS config COMMON_CLK_C3_PLL tristate "Amlogic C3 PLL clock controller" depends on ARM64 - default y + default ARCH_MESON select COMMON_CLK_MESON_REGMAP select COMMON_CLK_MESON_PLL select COMMON_CLK_MESON_CLKC_UTILS @@ -149,7 +149,7 @@ config COMMON_CLK_C3_PLL config COMMON_CLK_C3_PERIPHERALS tristate "Amlogic C3 peripherals clock controller" depends on ARM64 - default y + default ARCH_MESON select COMMON_CLK_MESON_REGMAP select COMMON_CLK_MESON_DUALDIV select COMMON_CLK_MESON_CLKC_UTILS @@ -163,7 +163,7 @@ config COMMON_CLK_C3_PERIPHERALS config COMMON_CLK_G12A tristate "G12 and SM1 SoC clock controllers support" depends on ARM64 - default y + default ARCH_MESON select COMMON_CLK_MESON_REGMAP select COMMON_CLK_MESON_DUALDIV select COMMON_CLK_MESON_MPLL @@ -181,7 +181,7 @@ config COMMON_CLK_G12A config COMMON_CLK_S4_PLL tristate "S4 SoC PLL clock controllers support" depends on ARM64 - default y + default ARCH_MESON select COMMON_CLK_MESON_CLKC_UTILS select COMMON_CLK_MESON_MPLL select COMMON_CLK_MESON_PLL @@ -194,7 +194,7 @@ config COMMON_CLK_S4_PLL config COMMON_CLK_S4_PERIPHERALS tristate "S4 SoC peripherals clock controllers support" depends on ARM64 - default y + default ARCH_MESON select COMMON_CLK_MESON_CLKC_UTILS select COMMON_CLK_MESON_REGMAP select COMMON_CLK_MESON_DUALDIV --=20 2.45.2 From nobody Mon Feb 9 12:27:26 2026 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E8BDC1EA7FC for ; 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Fri, 04 Apr 2025 04:57:03 -0700 (PDT) Received: from [192.168.1.26] ([178.197.198.86]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec364cb9asm43842815e9.31.2025.04.04.04.57.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Apr 2025 04:57:02 -0700 (PDT) From: Krzysztof Kozlowski Date: Fri, 04 Apr 2025 13:56:58 +0200 Subject: [PATCH 2/5] clk: nuvoton: Do not enable by default during compile testing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250404-kconfig-defaults-clk-v1-2-4d2df5603332@linaro.org> References: <20250404-kconfig-defaults-clk-v1-0-4d2df5603332@linaro.org> In-Reply-To: <20250404-kconfig-defaults-clk-v1-0-4d2df5603332@linaro.org> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Maxime Coquelin , Alexandre Torgue , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , =?utf-8?q?Emilio_L=C3=B3pez?= Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-sunxi@lists.linux.dev, Krzysztof Kozlowski X-Mailer: b4 0.14.2 Enabling the compile test should not cause automatic enabling of all drivers. Restrict the default to ARCH also for individual driver, even though its choice is not visible without selecting parent Kconfig symbol, because otherwise selecting parent would select the child during compile testing. Signed-off-by: Krzysztof Kozlowski --- drivers/clk/nuvoton/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/nuvoton/Kconfig b/drivers/clk/nuvoton/Kconfig index fe4b7f62f467048b7c86890972d55faebd066947..e7019b69ea74824de6943108f30= ec259aa52e5f4 100644 --- a/drivers/clk/nuvoton/Kconfig +++ b/drivers/clk/nuvoton/Kconfig @@ -4,7 +4,7 @@ config COMMON_CLK_NUVOTON bool "Nuvoton clock controller common support" depends on ARCH_MA35 || COMPILE_TEST - default y + default ARCH_MA35 help Say y here to enable common clock controller for Nuvoton platforms. =20 @@ -12,7 +12,7 @@ if COMMON_CLK_NUVOTON =20 config CLK_MA35D1 bool "Nuvoton MA35D1 clock controller support" - default y + default ARCH_MA35 help Build the clock controller driver for MA35D1 SoC. =20 --=20 2.45.2 From nobody Mon Feb 9 12:27:26 2026 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 950071EEA33 for ; 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Restrict the default to ARCH also for individual driver, even though its choice is not visible without selecting parent Kconfig symbol, because otherwise selecting parent would select the child during compile testing. Signed-off-by: Krzysztof Kozlowski --- drivers/clk/stm32/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/stm32/Kconfig b/drivers/clk/stm32/Kconfig index dca409d52652213cfbd8d5ecf1a339ea53ba5d52..4d2eb993ea0838d408ff5b1e5b6= d028cbcaa9301 100644 --- a/drivers/clk/stm32/Kconfig +++ b/drivers/clk/stm32/Kconfig @@ -4,7 +4,7 @@ menuconfig COMMON_CLK_STM32MP bool "Clock support for common STM32MP clocks" depends on ARCH_STM32 || COMPILE_TEST - default y + default ARCH_STM32 select RESET_CONTROLLER help Support for STM32MP SoC family clocks. @@ -14,21 +14,21 @@ if COMMON_CLK_STM32MP config COMMON_CLK_STM32MP135 bool "Clock driver for stm32mp13x clocks" depends on ARM || COMPILE_TEST - default y + default ARCH_STM32 help Support for stm32mp13x SoC family clocks. =20 config COMMON_CLK_STM32MP157 bool "Clock driver for stm32mp15x clocks" depends on ARM || COMPILE_TEST - default y + default ARCH_STM32 help Support for stm32mp15x SoC family clocks. =20 config COMMON_CLK_STM32MP257 bool "Clock driver for stm32mp25x clocks" depends on ARM64 || COMPILE_TEST - default y + default ARCH_STM32 help Support for stm32mp25x SoC family clocks. =20 --=20 2.45.2 From nobody Mon Feb 9 12:27:26 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29A181F461F for ; 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Fri, 04 Apr 2025 04:57:07 -0700 (PDT) Received: from [192.168.1.26] ([178.197.198.86]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec364cb9asm43842815e9.31.2025.04.04.04.57.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Apr 2025 04:57:06 -0700 (PDT) From: Krzysztof Kozlowski Date: Fri, 04 Apr 2025 13:57:00 +0200 Subject: [PATCH 4/5] clk: sunxi-ng: Do not enable by default during compile testing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250404-kconfig-defaults-clk-v1-4-4d2df5603332@linaro.org> References: <20250404-kconfig-defaults-clk-v1-0-4d2df5603332@linaro.org> In-Reply-To: <20250404-kconfig-defaults-clk-v1-0-4d2df5603332@linaro.org> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Maxime Coquelin , Alexandre Torgue , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , =?utf-8?q?Emilio_L=C3=B3pez?= Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-sunxi@lists.linux.dev, Krzysztof Kozlowski X-Mailer: b4 0.14.2 Enabling the compile test should not cause automatic enabling of all drivers. Restrict the default to ARCH also for individual drivers, even though their choice is not visible without selecting parent Kconfig symbol, because otherwise selecting parent would select the child during compile testing. Signed-off-by: Krzysztof Kozlowski --- drivers/clk/sunxi-ng/Kconfig | 48 ++++++++++++++++++++++------------------= ---- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 5830a9d87bf25d536ac787fe83669c64c8214952..8896fd052ef1784d60d488ab149= 8737c1405deb2 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -9,123 +9,123 @@ if SUNXI_CCU =20 config SUNIV_F1C100S_CCU tristate "Support for the Allwinner newer F1C100s CCU" - default y + default ARCH_SUNXI depends on MACH_SUNIV || COMPILE_TEST =20 config SUN20I_D1_CCU tristate "Support for the Allwinner D1/R528/T113 CCU" - default y + default ARCH_SUNXI depends on MACH_SUN8I || RISCV || COMPILE_TEST =20 config SUN20I_D1_R_CCU tristate "Support for the Allwinner D1/R528/T113 PRCM CCU" - default y + default ARCH_SUNXI depends on MACH_SUN8I || RISCV || COMPILE_TEST =20 config SUN50I_A64_CCU tristate "Support for the Allwinner A64 CCU" - default y + default ARCH_SUNXI depends on ARM64 || COMPILE_TEST =20 config SUN50I_A100_CCU tristate "Support for the Allwinner A100 CCU" - default y + default ARCH_SUNXI depends on ARM64 || COMPILE_TEST =20 config SUN50I_A100_R_CCU tristate "Support for the Allwinner A100 PRCM CCU" - default y + default ARCH_SUNXI depends on ARM64 || COMPILE_TEST =20 config SUN50I_H6_CCU tristate "Support for the Allwinner H6 CCU" - default y + default ARCH_SUNXI depends on ARM64 || COMPILE_TEST =20 config SUN50I_H616_CCU tristate "Support for the Allwinner H616 CCU" - default y + default ARCH_SUNXI depends on ARM64 || COMPILE_TEST =20 config SUN50I_H6_R_CCU tristate "Support for the Allwinner H6 and H616 PRCM CCU" - default y + default ARCH_SUNXI depends on ARM64 || COMPILE_TEST =20 config SUN55I_A523_CCU tristate "Support for the Allwinner A523/T527 CCU" - default y + default ARCH_SUNXI depends on ARM64 || COMPILE_TEST =20 config SUN55I_A523_R_CCU tristate "Support for the Allwinner A523/T527 PRCM CCU" - default y + default ARCH_SUNXI depends on ARM64 || COMPILE_TEST =20 config SUN4I_A10_CCU tristate "Support for the Allwinner A10/A20 CCU" - default y + default ARCH_SUNXI depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST =20 config SUN5I_CCU bool "Support for the Allwinner sun5i family CCM" - default y + default ARCH_SUNXI depends on MACH_SUN5I || COMPILE_TEST depends on SUNXI_CCU=3Dy =20 config SUN6I_A31_CCU tristate "Support for the Allwinner A31/A31s CCU" - default y + default ARCH_SUNXI depends on MACH_SUN6I || COMPILE_TEST =20 config SUN6I_RTC_CCU tristate "Support for the Allwinner H616/R329 RTC CCU" - default y + default ARCH_SUNXI depends on MACH_SUN8I || ARM64 || RISCV || COMPILE_TEST =20 config SUN8I_A23_CCU tristate "Support for the Allwinner A23 CCU" - default y + default ARCH_SUNXI depends on MACH_SUN8I || COMPILE_TEST =20 config SUN8I_A33_CCU tristate "Support for the Allwinner A33 CCU" - default y + default ARCH_SUNXI depends on MACH_SUN8I || COMPILE_TEST =20 config SUN8I_A83T_CCU tristate "Support for the Allwinner A83T CCU" - default y + default ARCH_SUNXI depends on MACH_SUN8I || COMPILE_TEST =20 config SUN8I_H3_CCU tristate "Support for the Allwinner H3 CCU" - default y + default ARCH_SUNXI depends on MACH_SUN8I || ARM64 || COMPILE_TEST =20 config SUN8I_V3S_CCU tristate "Support for the Allwinner V3s CCU" - default y + default ARCH_SUNXI depends on MACH_SUN8I || COMPILE_TEST =20 config SUN8I_DE2_CCU tristate "Support for the Allwinner SoCs DE2 CCU" - default y + default ARCH_SUNXI depends on MACH_SUN8I || ARM64 || RISCV || COMPILE_TEST =20 config SUN8I_R40_CCU tristate "Support for the Allwinner R40 CCU" - default y + default ARCH_SUNXI depends on MACH_SUN8I || COMPILE_TEST =20 config SUN9I_A80_CCU tristate "Support for the Allwinner A80 CCU" - default y + default ARCH_SUNXI depends on MACH_SUN9I || COMPILE_TEST =20 config SUN8I_R_CCU tristate "Support for Allwinner SoCs' PRCM CCUs" - default y + default ARCH_SUNXI depends on MACH_SUN8I || ARM64 || COMPILE_TEST =20 endif --=20 2.45.2 From nobody Mon Feb 9 12:27:26 2026 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBEF41F4717 for ; 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Fri, 04 Apr 2025 04:57:09 -0700 (PDT) Received: from [192.168.1.26] ([178.197.198.86]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec364cb9asm43842815e9.31.2025.04.04.04.57.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Apr 2025 04:57:08 -0700 (PDT) From: Krzysztof Kozlowski Date: Fri, 04 Apr 2025 13:57:01 +0200 Subject: [PATCH 5/5] clk: sunxi: Do not enable by default during compile testing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250404-kconfig-defaults-clk-v1-5-4d2df5603332@linaro.org> References: <20250404-kconfig-defaults-clk-v1-0-4d2df5603332@linaro.org> In-Reply-To: <20250404-kconfig-defaults-clk-v1-0-4d2df5603332@linaro.org> To: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , Maxime Coquelin , Alexandre Torgue , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , =?utf-8?q?Emilio_L=C3=B3pez?= Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-sunxi@lists.linux.dev, Krzysztof Kozlowski X-Mailer: b4 0.14.2 Enabling the compile test should not cause automatic enabling of all drivers. Restrict the default to ARCH also for individual drivers, even though their choice is not visible without selecting parent Kconfig symbol, because otherwise selecting parent would select the child during compile testing. Signed-off-by: Krzysztof Kozlowski --- drivers/clk/sunxi/Kconfig | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 1c4e543366ddb76c1669b577c1ac337dc1be616f..5e2f92bfe4120981ab68b175dce= 798ac8b3268b0 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -2,13 +2,13 @@ menuconfig CLK_SUNXI bool "Legacy clock support for Allwinner SoCs" depends on (ARM && ARCH_SUNXI) || COMPILE_TEST - default y + default (ARM && ARCH_SUNXI) =20 if CLK_SUNXI =20 config CLK_SUNXI_CLOCKS bool "Legacy clock drivers" - default y + default ARCH_SUNXI help Legacy clock drivers being used on older (A10, A13, A20, A23, A31, A80) SoCs. These drivers are kept around for @@ -19,14 +19,14 @@ config CLK_SUNXI_CLOCKS =20 config CLK_SUNXI_PRCM_SUN6I bool "Legacy A31 PRCM driver" - default y + default ARCH_SUNXI help Legacy clock driver for the A31 PRCM clocks. Those are usually needed for the PMIC communication, mostly. =20 config CLK_SUNXI_PRCM_SUN8I bool "Legacy sun8i PRCM driver" - default y + default ARCH_SUNXI help Legacy clock driver for the sun8i family PRCM clocks. Those are usually needed for the PMIC communication, @@ -34,7 +34,7 @@ config CLK_SUNXI_PRCM_SUN8I =20 config CLK_SUNXI_PRCM_SUN9I bool "Legacy A80 PRCM driver" - default y + default ARCH_SUNXI help Legacy clock driver for the A80 PRCM clocks. Those are usually needed for the PMIC communication, mostly. --=20 2.45.2