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Thu, 03 Apr 2025 07:45:28 -0700 (PDT) Received: from localhost.localdomain ([5.133.47.210]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c3020d661sm2044374f8f.66.2025.04.03.07.45.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Apr 2025 07:45:27 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, Dmitry Baryshkov , Srinivas Kandagatla Subject: [PATCH v3 08/13] nvmem: core: fix bit offsets of more than one byte Date: Thu, 3 Apr 2025 15:44:56 +0100 Message-Id: <20250403144501.202742-9-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250403144501.202742-1-srinivas.kandagatla@linaro.org> References: <20250403144501.202742-1-srinivas.kandagatla@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2189; i=srinivas.kandagatla@linaro.org; h=from:subject; bh=fqrKmcbiS1AKaDRrZvXTHaNkz/q/+2qHSl68uGqUaBM=; b=owGbwMvMwMVYtfBv5HGTUHPG02pJDOnv5j1+J9jbuE050+x9yg/ZM3LfYm40Fm66s7ptm7uV4 vVHXC+udDIaszAwcjHIiimyKD33jzr259G373J3e2EGsTKBTGHg4hSAiYidYf8rad5+Y9tfjXxr 0eszWXteMStfKlsYL2ZQkOTPJid0QZ6z29Ew12Wfudziv44rb4lw65dZcC48u7/AyWK9ceR0Dca SjAKOvRrH+k2fpTywtNW1iKjZvmdvr2DboXadZ+9lBfi9+cSy5k71UfZb0xV44GqkMUdtzsvy1N pbzG/b31fqH0iY5mi7orC+4d3qyXt1Az2me2wWVs8sT2t/5ht1Yp7G1ZYF2v57lxyJVfq8PTbdi bdr9aoKvze2J+OiexLPvTINPhKcJvnjXvgX+W86Er8XPz2lHsno17IpkaXItSlUp35X8facDf8j q84dDRf8dNhKW6Dw9I/txW+f/CuqeSHoJPvxynKTkzYTAQ== X-Developer-Key: i=srinivas.kandagatla@linaro.org; a=openpgp; fpr=ED6472765AB36EC43B3EF97AD77E3FC0562560D6 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dmitry Baryshkov If the NVMEM specifies a stride to access data, reading particular cell might require bit offset that is bigger than one byte. Rework NVMEM core code to support bit offsets of more than 8 bits. Signed-off-by: Dmitry Baryshkov Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/core.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c index fff85bbf0ecd..7872903c08a1 100644 --- a/drivers/nvmem/core.c +++ b/drivers/nvmem/core.c @@ -837,7 +837,9 @@ static int nvmem_add_cells_from_dt(struct nvmem_device = *nvmem, struct device_nod if (addr && len =3D=3D (2 * sizeof(u32))) { info.bit_offset =3D be32_to_cpup(addr++); info.nbits =3D be32_to_cpup(addr); - if (info.bit_offset >=3D BITS_PER_BYTE || info.nbits < 1) { + if (info.bit_offset >=3D BITS_PER_BYTE * info.bytes || + info.nbits < 1 || + info.bit_offset + info.nbits > BITS_PER_BYTE * info.bytes) { dev_err(dev, "nvmem: invalid bits on %pOF\n", child); of_node_put(child); return -EINVAL; @@ -1630,21 +1632,29 @@ EXPORT_SYMBOL_GPL(nvmem_cell_put); static void nvmem_shift_read_buffer_in_place(struct nvmem_cell_entry *cell= , void *buf) { u8 *p, *b; - int i, extra, bit_offset =3D cell->bit_offset; + int i, extra, bytes_offset; + int bit_offset =3D cell->bit_offset; =20 p =3D b =3D buf; - if (bit_offset) { + + bytes_offset =3D bit_offset / BITS_PER_BYTE; + b +=3D bytes_offset; + bit_offset %=3D BITS_PER_BYTE; + + if (bit_offset % BITS_PER_BYTE) { /* First shift */ - *b++ >>=3D bit_offset; + *p =3D *b++ >> bit_offset; =20 /* setup rest of the bytes if any */ for (i =3D 1; i < cell->bytes; i++) { /* Get bits from next byte and shift them towards msb */ - *p |=3D *b << (BITS_PER_BYTE - bit_offset); + *p++ |=3D *b << (BITS_PER_BYTE - bit_offset); =20 - p =3D b; - *b++ >>=3D bit_offset; + *p =3D *b++ >> bit_offset; } + } else if (p !=3D b) { + memmove(p, b, cell->bytes - bytes_offset); + p +=3D cell->bytes - 1; } else { /* point to the msb */ p +=3D cell->bytes - 1; --=20 2.25.1