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Thu, 03 Apr 2025 07:45:32 -0700 (PDT) Received: from localhost.localdomain ([5.133.47.210]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c3020d661sm2044374f8f.66.2025.04.03.07.45.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Apr 2025 07:45:31 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: gregkh@linuxfoundation.org Cc: linux-kernel@vger.kernel.org, Dmitry Baryshkov , Srinivas Kandagatla Subject: [PATCH v3 11/13] nvmem: qfprom: switch to 4-byte aligned reads Date: Thu, 3 Apr 2025 15:44:59 +0100 Message-Id: <20250403144501.202742-12-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250403144501.202742-1-srinivas.kandagatla@linaro.org> References: <20250403144501.202742-1-srinivas.kandagatla@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2313; i=srinivas.kandagatla@linaro.org; h=from:subject; bh=JJiFhfRmHwPniUxF2lMkh5d/tp9H/TdB0Jvtor5rjlc=; b=owEBbQGS/pANAwAKAXqh/VnHNFU3AcsmYgBn7p7jUasBH7hrcLPZhwfh2HNMT1jUIAJKxwHVL 90k/z9bwgSJATMEAAEKAB0WIQQi509axvzi9vce3Y16of1ZxzRVNwUCZ+6e4wAKCRB6of1ZxzRV N0WIB/9LLKVJPYdPQljfkXOpXnetzkruRAcIXdAW7DjAuOWyrBnX4N7GIV3f6mE+BOO1axvE2NL MRC8FpacIHtoQMs81dGCnND0Y/4hxmlP68vLAyY3LpKZgRnpfT7HcoACjL+SSNnghMe5jbeMWn8 iK9KPp4jKk/HafC2z1LDreJC/RvTqRV2mjggEvc13KgrGERfuWbPvIiIk7SZQ9oysXYfmhhetsO uuhd9+e+yCk7PDmxKWN3vCvHGa91Eekm08yQZDpGBPPLwM9ZiymF0AoW0jPo2zKAWvIHtsRNHaj IkdUs4aKNDi8RZoYtTnnviwsRspUoRvxOM50FN/OoT/9eYwK X-Developer-Key: i=srinivas.kandagatla@linaro.org; a=openpgp; fpr=ED6472765AB36EC43B3EF97AD77E3FC0562560D6 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dmitry Baryshkov All platforms since Snapdragon 8 Gen1 (SM8450) require using 4-byte reads to access QFPROM data. While older platforms were more than happy with 1-byte reads, change the qfprom driver to use 4-byte reads for all the platforms. Specify stride and word size of 4 bytes. To retain compatibility with the existing DT and to simplify porting data from vendor kernels, use fixup_dt_cell_info in order to bump alignment requirements. Signed-off-by: Dmitry Baryshkov Signed-off-by: Srinivas Kandagatla --- drivers/nvmem/qfprom.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/nvmem/qfprom.c b/drivers/nvmem/qfprom.c index 116a39e804c7..a872c640b8c5 100644 --- a/drivers/nvmem/qfprom.c +++ b/drivers/nvmem/qfprom.c @@ -321,19 +321,32 @@ static int qfprom_reg_read(void *context, unsigned int reg, void *_val, size_t bytes) { struct qfprom_priv *priv =3D context; - u8 *val =3D _val; - int i =3D 0, words =3D bytes; + u32 *val =3D _val; void __iomem *base =3D priv->qfpcorrected; + int words =3D DIV_ROUND_UP(bytes, sizeof(u32)); + int i; =20 if (read_raw_data && priv->qfpraw) base =3D priv->qfpraw; =20 - while (words--) - *val++ =3D readb(base + reg + i++); + for (i =3D 0; i < words; i++) + *val++ =3D readl(base + reg + i * sizeof(u32)); =20 return 0; } =20 +/* Align reads to word boundary */ +static void qfprom_fixup_dt_cell_info(struct nvmem_device *nvmem, + struct nvmem_cell_info *cell) +{ + unsigned int byte_offset =3D cell->offset % sizeof(u32); + + cell->bit_offset +=3D byte_offset * BITS_PER_BYTE; + cell->offset -=3D byte_offset; + if (byte_offset && !cell->nbits) + cell->nbits =3D cell->bytes * BITS_PER_BYTE; +} + static void qfprom_runtime_disable(void *data) { pm_runtime_disable(data); @@ -358,10 +371,11 @@ static int qfprom_probe(struct platform_device *pdev) struct nvmem_config econfig =3D { .name =3D "qfprom", .add_legacy_fixed_of_cells =3D true, - .stride =3D 1, - .word_size =3D 1, + .stride =3D 4, + .word_size =3D 4, .id =3D NVMEM_DEVID_AUTO, .reg_read =3D qfprom_reg_read, + .fixup_dt_cell_info =3D qfprom_fixup_dt_cell_info, }; struct device *dev =3D &pdev->dev; struct resource *res; --=20 2.25.1