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From: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
To: alexandre.belloni@bootlin.com, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, jarkko.nikula@linux.intel.com,
linux-i3c@lists.infradead.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: andersson@kernel.org, konradybcio@kernel.org,
Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
Subject: [PATCH v3 1/3] dt-bindings: i3c: Add support for Qualcomm I3C
controller
Date: Thu, 3 Apr 2025 19:16:42 +0530
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Add device tree bindings for the Qualcomm I3C controller. This includes
the necessary documentation and properties required to describe the
hardware in the device tree.
Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
---
.../bindings/i3c/qcom,geni-i3c.yaml | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i3c/qcom,geni-i3c.yaml
diff --git a/Documentation/devicetree/bindings/i3c/qcom,geni-i3c.yaml b/Doc=
umentation/devicetree/bindings/i3c/qcom,geni-i3c.yaml
new file mode 100644
index 000000000000..25f0d92204d9
--- /dev/null
+++ b/Documentation/devicetree/bindings/i3c/qcom,geni-i3c.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i3c/qcom,geni-i3c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Geni based QUP I3C Controller
+
+maintainers:
+ - Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
+
+description:
+ I3C in master mode supports up to 12.5MHz, SDR mode data transfer in mix=
ed
+ bus mode (I2C and I3C target devices on same i3c bus). It also supports
+ hotjoin, IBI mechanism.
+
+ I3C Controller nodes must be child of GENI based Qualcomm Universal
+ Peripharal. Please refer GENI based QUP wrapper controller node bindings
+ described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yam=
l.
+
+allOf:
+ - $ref: i3c.yaml#
+
+properties:
+ compatible:
+ - qcom,geni-i3c
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: se
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,sm8550-gcc.h>
+
+ i3c@884000 {
+ compatible =3D "qcom,geni-i3c";
+ reg =3D <0x00884000 0x4000>;
+ clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
+ clock-names =3D "se";
+ interrupts =3D <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells =3D <3>;
+ #size-cells =3D <0>;
+ };
+...
--=20
2.25.1