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From: Christian Bruel <christian.bruel@foss.st.com>
To: <maz@kernel.org>, <tglx@linutronix.de>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>,
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<linux-stm32@st-md-mailman.stormreply.com>,
Christian Bruel <christian.bruel@foss.st.com>
Subject: [PATCH 2/3] irqchip/gic: Use 0x10000 offset to access GICC_DIR on
STM32MP2
Date: Thu, 3 Apr 2025 14:28:04 +0200
Message-ID: <20250403122805.1574086-3-christian.bruel@foss.st.com>
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When GIC_4KNOT64K bit in the GIC configuration register is
0 (64KB), address block is modified in such a way than only the
first 4KB of the GIC cpu interface are accessible with default
offsets.
With this bit mapping GICC_DIR register is accessible at
offset 0x10000 instead of 0x1000, thus remap accordingly
Use st,stm32mp2-cortex-a7-gic for this purpose.
Signed-off-by: Christian Bruel <christian.bruel@foss.st.com>
---
drivers/irqchip/irq-gic.c | 47 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 46 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 6503573557fd..d61dcd0eb4c6 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -72,6 +72,7 @@ struct gic_chip_data {
union gic_base cpu_base;
void __iomem *raw_dist_base;
void __iomem *raw_cpu_base;
+ phys_addr_t cpu_phys_base;
u32 percpu_offset;
#if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
@@ -108,6 +109,8 @@ static DEFINE_RAW_SPINLOCK(cpu_map_lock);
=20
#endif
=20
+static DEFINE_STATIC_KEY_FALSE(gic_stm32mp2_gicc_dir_access);
+
static DEFINE_STATIC_KEY_FALSE(needs_rmw_access);
=20
/*
@@ -225,6 +228,8 @@ static void gic_eoi_irq(struct irq_data *d)
writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_EOI);
}
=20
+#define GIC_STM32MP2_CPU_DEACTIVATE 0x10000
+
static void gic_eoimode1_eoi_irq(struct irq_data *d)
{
irq_hw_number_t hwirq =3D irqd_to_hwirq(d);
@@ -236,7 +241,10 @@ static void gic_eoimode1_eoi_irq(struct irq_data *d)
if (hwirq < 16)
hwirq =3D this_cpu_read(sgi_intid);
=20
- writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
+ if (static_branch_unlikely(&gic_stm32mp2_gicc_dir_access))
+ writel_relaxed(hwirq, gic_cpu_base(d) + GIC_STM32MP2_CPU_DEACTIVATE);
+ else
+ writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
}
=20
static int gic_irq_set_irqchip_state(struct irq_data *d,
@@ -1377,17 +1385,50 @@ static bool gic_enable_rmw_access(void *data)
return false;
}
=20
+/*
+ * 8kB GICC range is not accessible with the default 4kB translation
+ * granule. 0x1000 offset is accessible at 64kB translation.
+ */
+static bool gic_8kbaccess(void *data)
+{
+ struct gic_chip_data *gic =3D data;
+ void __iomem *alt;
+
+ if (!is_hyp_mode_available())
+ return false;
+
+ alt =3D ioremap(gic->cpu_phys_base, GIC_STM32MP2_CPU_DEACTIVATE + 4);
+ if (!alt) {
+ pr_err("Unable to remap GICC_DIR register\n");
+ return false;
+ }
+
+ iounmap(gic->raw_cpu_base);
+ gic->raw_cpu_base =3D alt;
+
+ static_branch_enable(&gic_stm32mp2_gicc_dir_access);
+
+ return true;
+}
+
static const struct gic_quirk gic_quirks[] =3D {
{
.desc =3D "broken byte access",
.compatible =3D "arm,pl390",
.init =3D gic_enable_rmw_access,
},
+ {
+ .desc =3D "4kB GICC access disabled",
+ .compatible =3D "st,stm32mp2-cortex-a7-gic",
+ .init =3D gic_8kbaccess,
+ },
{ },
};
=20
static int gic_of_setup(struct gic_chip_data *gic, struct device_node *nod=
e)
{
+ struct resource cpuif_res;
+
if (!gic || !node)
return -EINVAL;
=20
@@ -1395,6 +1436,8 @@ static int gic_of_setup(struct gic_chip_data *gic, st=
ruct device_node *node)
if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
goto error;
=20
+ of_address_to_resource(node, 1, &cpuif_res);
+ gic->cpu_phys_base =3D cpuif_res.start;
gic->raw_cpu_base =3D of_iomap(node, 1);
if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
goto error;
@@ -1510,6 +1553,7 @@ gic_of_init(struct device_node *node, struct device_n=
ode *parent)
gic_cnt++;
return 0;
}
+
IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_in=
it);
@@ -1519,6 +1563,7 @@ IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", g=
ic_of_init);
IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
+IRQCHIP_DECLARE(stm32mp2_cortex_a7_gic, "st,stm32mp2-cortex-a7-gic", gic_o=
f_init);
=20
#ifdef CONFIG_ACPI
static struct
--=20
2.34.1