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From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= <rkrcmar@ventanamicro.com>
To: kvm-riscv@lists.infradead.org
Cc: kvm@vger.kernel.org,
linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Andrew Jones <ajones@ventanamicro.com>,
Mayuresh Chitale <mchitale@ventanamicro.com>
Subject: [PATCH 3/5] KVM: RISC-V: remove unnecessary SBI reset state
Date: Thu, 3 Apr 2025 13:25:22 +0200
Message-ID: <20250403112522.1566629-6-rkrcmar@ventanamicro.com>
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The SBI reset state has only two variables -- pc and a1.
The rest is known, so keep only the necessary information.
The reset structures make sense if we want userspace to control the
reset state (which we do), but I'd still remove them now and reintroduce
with the userspace interface later -- we could probably have just a
single reset state per VM, instead of a reset state for each VCPU.
Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 <rkrcmar@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
arch/riscv/include/asm/kvm_aia.h | 3 --
arch/riscv/include/asm/kvm_host.h | 12 ++++---
arch/riscv/kvm/aia_device.c | 4 +--
arch/riscv/kvm/vcpu.c | 58 +++++++++++++++++--------------
arch/riscv/kvm/vcpu_sbi.c | 9 +++--
5 files changed, 44 insertions(+), 42 deletions(-)
diff --git a/arch/riscv/include/asm/kvm_aia.h b/arch/riscv/include/asm/kvm_=
aia.h
index 1f37b600ca47..3b643b9efc07 100644
--- a/arch/riscv/include/asm/kvm_aia.h
+++ b/arch/riscv/include/asm/kvm_aia.h
@@ -63,9 +63,6 @@ struct kvm_vcpu_aia {
/* CPU AIA CSR context of Guest VCPU */
struct kvm_vcpu_aia_csr guest_csr;
=20
- /* CPU AIA CSR context upon Guest VCPU reset */
- struct kvm_vcpu_aia_csr guest_reset_csr;
-
/* Guest physical address of IMSIC for this VCPU */
gpa_t imsic_addr;
=20
diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm=
_host.h
index 0e9c2fab6378..0c8c9c05af91 100644
--- a/arch/riscv/include/asm/kvm_host.h
+++ b/arch/riscv/include/asm/kvm_host.h
@@ -193,6 +193,12 @@ struct kvm_vcpu_smstateen_csr {
unsigned long sstateen0;
};
=20
+struct kvm_vcpu_reset_state {
+ spinlock_t lock;
+ unsigned long pc;
+ unsigned long a1;
+};
+
struct kvm_vcpu_arch {
/* VCPU ran at least once */
bool ran_atleast_once;
@@ -227,12 +233,8 @@ struct kvm_vcpu_arch {
/* CPU Smstateen CSR context of Guest VCPU */
struct kvm_vcpu_smstateen_csr smstateen_csr;
=20
- /* CPU context upon Guest VCPU reset */
- struct kvm_cpu_context guest_reset_context;
- spinlock_t reset_cntx_lock;
+ struct kvm_vcpu_reset_state reset_state;
=20
- /* CPU CSR context upon Guest VCPU reset */
- struct kvm_vcpu_csr guest_reset_csr;
=20
/*
* VCPU interrupts
diff --git a/arch/riscv/kvm/aia_device.c b/arch/riscv/kvm/aia_device.c
index 39cd26af5a69..43e472ff3e1a 100644
--- a/arch/riscv/kvm/aia_device.c
+++ b/arch/riscv/kvm/aia_device.c
@@ -526,12 +526,10 @@ int kvm_riscv_vcpu_aia_update(struct kvm_vcpu *vcpu)
void kvm_riscv_vcpu_aia_reset(struct kvm_vcpu *vcpu)
{
struct kvm_vcpu_aia_csr *csr =3D &vcpu->arch.aia_context.guest_csr;
- struct kvm_vcpu_aia_csr *reset_csr =3D
- &vcpu->arch.aia_context.guest_reset_csr;
=20
if (!kvm_riscv_aia_available())
return;
- memcpy(csr, reset_csr, sizeof(*csr));
+ memset(csr, 0, sizeof(*csr));
=20
/* Proceed only if AIA was initialized successfully */
if (!kvm_riscv_aia_initialized(vcpu->kvm))
diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c
index 2fb75288ecfe..b8485c1c1ce4 100644
--- a/arch/riscv/kvm/vcpu.c
+++ b/arch/riscv/kvm/vcpu.c
@@ -51,13 +51,40 @@ const struct kvm_stats_header kvm_vcpu_stats_header =3D=
{
sizeof(kvm_vcpu_stats_desc),
};
=20
-static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu)
+static void kvm_riscv_vcpu_context_reset(struct kvm_vcpu *vcpu)
{
struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr;
- struct kvm_vcpu_csr *reset_csr =3D &vcpu->arch.guest_reset_csr;
struct kvm_cpu_context *cntx =3D &vcpu->arch.guest_context;
- struct kvm_cpu_context *reset_cntx =3D &vcpu->arch.guest_reset_context;
+ struct kvm_vcpu_reset_state *reset_state =3D &vcpu->arch.reset_state;
void *vector_datap =3D cntx->vector.datap;
+
+ memset(cntx, 0, sizeof(*cntx));
+ memset(csr, 0, sizeof(*csr));
+
+ /* Restore datap as it's not a part of the guest context. */
+ cntx->vector.datap =3D vector_datap;
+
+ /* Load SBI reset values */
+ cntx->a0 =3D vcpu->vcpu_id;
+
+ spin_lock(&reset_state->lock);
+ cntx->sepc =3D reset_state->pc;
+ cntx->a1 =3D reset_state->a1;
+ spin_unlock(&reset_state->lock);
+
+ /* Setup reset state of shadow SSTATUS and HSTATUS CSRs */
+ cntx->sstatus =3D SR_SPP | SR_SPIE;
+
+ cntx->hstatus |=3D HSTATUS_VTW;
+ cntx->hstatus |=3D HSTATUS_SPVP;
+ cntx->hstatus |=3D HSTATUS_SPV;
+
+ /* By default, make CY, TM, and IR counters accessible in VU mode */
+ csr->scounteren =3D 0x7;
+}
+
+static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu)
+{
bool loaded;
=20
/**
@@ -72,16 +99,10 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu)
=20
vcpu->arch.last_exit_cpu =3D -1;
=20
- memcpy(csr, reset_csr, sizeof(*csr));
-
- spin_lock(&vcpu->arch.reset_cntx_lock);
- memcpy(cntx, reset_cntx, sizeof(*cntx));
- spin_unlock(&vcpu->arch.reset_cntx_lock);
+ kvm_riscv_vcpu_context_reset(vcpu);
=20
kvm_riscv_vcpu_fp_reset(vcpu);
=20
- /* Restore datap as it's not a part of the guest context. */
- cntx->vector.datap =3D vector_datap;
kvm_riscv_vcpu_vector_reset(vcpu);
=20
kvm_riscv_vcpu_timer_reset(vcpu);
@@ -113,8 +134,6 @@ int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned i=
nt id)
int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
{
int rc;
- struct kvm_cpu_context *cntx;
- struct kvm_vcpu_csr *reset_csr =3D &vcpu->arch.guest_reset_csr;
=20
spin_lock_init(&vcpu->arch.mp_state_lock);
=20
@@ -134,24 +153,11 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
/* Setup VCPU hfence queue */
spin_lock_init(&vcpu->arch.hfence_lock);
=20
- /* Setup reset state of shadow SSTATUS and HSTATUS CSRs */
- spin_lock_init(&vcpu->arch.reset_cntx_lock);
-
- spin_lock(&vcpu->arch.reset_cntx_lock);
- cntx =3D &vcpu->arch.guest_reset_context;
- cntx->sstatus =3D SR_SPP | SR_SPIE;
- cntx->hstatus =3D 0;
- cntx->hstatus |=3D HSTATUS_VTW;
- cntx->hstatus |=3D HSTATUS_SPVP;
- cntx->hstatus |=3D HSTATUS_SPV;
- spin_unlock(&vcpu->arch.reset_cntx_lock);
+ spin_lock_init(&vcpu->arch.reset_state.lock);
=20
if (kvm_riscv_vcpu_alloc_vector_context(vcpu))
return -ENOMEM;
=20
- /* By default, make CY, TM, and IR counters accessible in VU mode */
- reset_csr->scounteren =3D 0x7;
-
/* Setup VCPU timer */
kvm_riscv_vcpu_timer_init(vcpu);
=20
diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c
index f58368f7df1d..3d7955e05cc3 100644
--- a/arch/riscv/kvm/vcpu_sbi.c
+++ b/arch/riscv/kvm/vcpu_sbi.c
@@ -159,11 +159,10 @@ void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu =
*vcpu,
void kvm_riscv_vcpu_sbi_request_reset(struct kvm_vcpu *vcpu,
unsigned long pc, unsigned long a1)
{
- spin_lock(&vcpu->arch.reset_cntx_lock);
- vcpu->arch.guest_reset_context.sepc =3D pc;
- vcpu->arch.guest_reset_context.a0 =3D vcpu->vcpu_id;
- vcpu->arch.guest_reset_context.a1 =3D a1;
- spin_unlock(&vcpu->arch.reset_cntx_lock);
+ spin_lock(&vcpu->arch.reset_state.lock);
+ vcpu->arch.reset_state.pc =3D pc;
+ vcpu->arch.reset_state.a1 =3D a1;
+ spin_unlock(&vcpu->arch.reset_state.lock);
=20
kvm_make_request(KVM_REQ_VCPU_RESET, vcpu);
}
--=20
2.48.1