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[31.30.173.141]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec366a699sm15541695e9.38.2025.04.03.04.32.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Apr 2025 04:32:11 -0700 (PDT) From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= To: kvm-riscv@lists.infradead.org Cc: kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andrew Jones , Mayuresh Chitale Subject: [PATCH 1/5] KVM: RISC-V: refactor vector state reset Date: Thu, 3 Apr 2025 13:25:20 +0200 Message-ID: <20250403112522.1566629-4-rkrcmar@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250403112522.1566629-3-rkrcmar@ventanamicro.com> References: <20250403112522.1566629-3-rkrcmar@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Do not depend on the reset structures. vector.datap is a kernel memory pointer that needs to be preserved as it is not a part of the guest vector data. Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 --- arch/riscv/include/asm/kvm_vcpu_vector.h | 6 ++---- arch/riscv/kvm/vcpu.c | 5 ++++- arch/riscv/kvm/vcpu_vector.c | 13 +++++++------ 3 files changed, 13 insertions(+), 11 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_vector.h b/arch/riscv/include/= asm/kvm_vcpu_vector.h index 27f5bccdd8b0..57a798a4cb0d 100644 --- a/arch/riscv/include/asm/kvm_vcpu_vector.h +++ b/arch/riscv/include/asm/kvm_vcpu_vector.h @@ -33,8 +33,7 @@ void kvm_riscv_vcpu_guest_vector_restore(struct kvm_cpu_c= ontext *cntx, unsigned long *isa); void kvm_riscv_vcpu_host_vector_save(struct kvm_cpu_context *cntx); void kvm_riscv_vcpu_host_vector_restore(struct kvm_cpu_context *cntx); -int kvm_riscv_vcpu_alloc_vector_context(struct kvm_vcpu *vcpu, - struct kvm_cpu_context *cntx); +int kvm_riscv_vcpu_alloc_vector_context(struct kvm_vcpu *vcpu); void kvm_riscv_vcpu_free_vector_context(struct kvm_vcpu *vcpu); #else =20 @@ -62,8 +61,7 @@ static inline void kvm_riscv_vcpu_host_vector_restore(str= uct kvm_cpu_context *cn { } =20 -static inline int kvm_riscv_vcpu_alloc_vector_context(struct kvm_vcpu *vcp= u, - struct kvm_cpu_context *cntx) +static inline int kvm_riscv_vcpu_alloc_vector_context(struct kvm_vcpu *vcp= u) { return 0; } diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 60d684c76c58..2fb75288ecfe 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -57,6 +57,7 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) struct kvm_vcpu_csr *reset_csr =3D &vcpu->arch.guest_reset_csr; struct kvm_cpu_context *cntx =3D &vcpu->arch.guest_context; struct kvm_cpu_context *reset_cntx =3D &vcpu->arch.guest_reset_context; + void *vector_datap =3D cntx->vector.datap; bool loaded; =20 /** @@ -79,6 +80,8 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) =20 kvm_riscv_vcpu_fp_reset(vcpu); =20 + /* Restore datap as it's not a part of the guest context. */ + cntx->vector.datap =3D vector_datap; kvm_riscv_vcpu_vector_reset(vcpu); =20 kvm_riscv_vcpu_timer_reset(vcpu); @@ -143,7 +146,7 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) cntx->hstatus |=3D HSTATUS_SPV; spin_unlock(&vcpu->arch.reset_cntx_lock); =20 - if (kvm_riscv_vcpu_alloc_vector_context(vcpu, cntx)) + if (kvm_riscv_vcpu_alloc_vector_context(vcpu)) return -ENOMEM; =20 /* By default, make CY, TM, and IR counters accessible in VU mode */ diff --git a/arch/riscv/kvm/vcpu_vector.c b/arch/riscv/kvm/vcpu_vector.c index d92d1348045c..a5f88cb717f3 100644 --- a/arch/riscv/kvm/vcpu_vector.c +++ b/arch/riscv/kvm/vcpu_vector.c @@ -22,6 +22,9 @@ void kvm_riscv_vcpu_vector_reset(struct kvm_vcpu *vcpu) struct kvm_cpu_context *cntx =3D &vcpu->arch.guest_context; =20 cntx->sstatus &=3D ~SR_VS; + + cntx->vector.vlenb =3D riscv_v_vsize / 32; + if (riscv_isa_extension_available(isa, v)) { cntx->sstatus |=3D SR_VS_INITIAL; WARN_ON(!cntx->vector.datap); @@ -70,13 +73,11 @@ void kvm_riscv_vcpu_host_vector_restore(struct kvm_cpu_= context *cntx) __kvm_riscv_vector_restore(cntx); } =20 -int kvm_riscv_vcpu_alloc_vector_context(struct kvm_vcpu *vcpu, - struct kvm_cpu_context *cntx) +int kvm_riscv_vcpu_alloc_vector_context(struct kvm_vcpu *vcpu) { - cntx->vector.datap =3D kmalloc(riscv_v_vsize, GFP_KERNEL); - if (!cntx->vector.datap) + vcpu->arch.guest_context.vector.datap =3D kzalloc(riscv_v_vsize, GFP_KERN= EL); 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[31.30.173.141]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec3429f67sm16500145e9.7.2025.04.03.04.32.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Apr 2025 04:32:13 -0700 (PDT) From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= To: kvm-riscv@lists.infradead.org Cc: kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andrew Jones , Mayuresh Chitale Subject: [PATCH 2/5] KVM: RISC-V: refactor sbi reset request Date: Thu, 3 Apr 2025 13:25:21 +0200 Message-ID: <20250403112522.1566629-5-rkrcmar@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250403112522.1566629-3-rkrcmar@ventanamicro.com> References: <20250403112522.1566629-3-rkrcmar@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The same code is used twice and SBI reset sets only two variables. Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 2 ++ arch/riscv/kvm/vcpu_sbi.c | 12 ++++++++++++ arch/riscv/kvm/vcpu_sbi_hsm.c | 13 +------------ arch/riscv/kvm/vcpu_sbi_system.c | 10 +--------- 4 files changed, 16 insertions(+), 21 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index 4ed6203cdd30..aaaa81355276 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -55,6 +55,8 @@ void kvm_riscv_vcpu_sbi_forward(struct kvm_vcpu *vcpu, st= ruct kvm_run *run); void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu *vcpu, struct kvm_run *run, u32 type, u64 flags); +void kvm_riscv_vcpu_sbi_request_reset(struct kvm_vcpu *vcpu, + unsigned long pc, unsigned long a1); int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run); int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index d1c83a77735e..f58368f7df1d 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -156,6 +156,18 @@ void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu *= vcpu, run->exit_reason =3D KVM_EXIT_SYSTEM_EVENT; } =20 +void kvm_riscv_vcpu_sbi_request_reset(struct kvm_vcpu *vcpu, + unsigned long pc, unsigned long a1) +{ + spin_lock(&vcpu->arch.reset_cntx_lock); + vcpu->arch.guest_reset_context.sepc =3D pc; + vcpu->arch.guest_reset_context.a0 =3D vcpu->vcpu_id; + vcpu->arch.guest_reset_context.a1 =3D a1; + spin_unlock(&vcpu->arch.reset_cntx_lock); + + kvm_make_request(KVM_REQ_VCPU_RESET, vcpu); +} + int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run) { struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; diff --git a/arch/riscv/kvm/vcpu_sbi_hsm.c b/arch/riscv/kvm/vcpu_sbi_hsm.c index 3070bb31745d..f26207f84bab 100644 --- a/arch/riscv/kvm/vcpu_sbi_hsm.c +++ b/arch/riscv/kvm/vcpu_sbi_hsm.c @@ -15,7 +15,6 @@ =20 static int kvm_sbi_hsm_vcpu_start(struct kvm_vcpu *vcpu) { - struct kvm_cpu_context *reset_cntx; struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; struct kvm_vcpu *target_vcpu; unsigned long target_vcpuid =3D cp->a0; @@ -32,17 +31,7 @@ static int kvm_sbi_hsm_vcpu_start(struct kvm_vcpu *vcpu) goto out; } =20 - spin_lock(&target_vcpu->arch.reset_cntx_lock); - reset_cntx =3D &target_vcpu->arch.guest_reset_context; - /* start address */ - reset_cntx->sepc =3D cp->a1; - /* target vcpu id to start */ - reset_cntx->a0 =3D target_vcpuid; - /* private data passed from kernel */ - reset_cntx->a1 =3D cp->a2; - spin_unlock(&target_vcpu->arch.reset_cntx_lock); - - kvm_make_request(KVM_REQ_VCPU_RESET, target_vcpu); + kvm_riscv_vcpu_sbi_request_reset(target_vcpu, cp->a1, cp->a2); =20 __kvm_riscv_vcpu_power_on(target_vcpu); =20 diff --git a/arch/riscv/kvm/vcpu_sbi_system.c b/arch/riscv/kvm/vcpu_sbi_sys= tem.c index bc0ebba89003..359be90b0fc5 100644 --- a/arch/riscv/kvm/vcpu_sbi_system.c +++ b/arch/riscv/kvm/vcpu_sbi_system.c @@ -13,7 +13,6 @@ static int kvm_sbi_ext_susp_handler(struct kvm_vcpu *vcpu= , struct kvm_run *run, struct kvm_vcpu_sbi_return *retdata) { struct kvm_cpu_context *cp =3D &vcpu->arch.guest_context; - struct kvm_cpu_context *reset_cntx; unsigned long funcid =3D cp->a6; unsigned long hva, i; struct kvm_vcpu *tmp; @@ -45,14 +44,7 @@ static int kvm_sbi_ext_susp_handler(struct kvm_vcpu *vcp= u, struct kvm_run *run, } } =20 - spin_lock(&vcpu->arch.reset_cntx_lock); - reset_cntx =3D &vcpu->arch.guest_reset_context; - reset_cntx->sepc =3D cp->a1; - reset_cntx->a0 =3D vcpu->vcpu_id; - reset_cntx->a1 =3D cp->a2; - spin_unlock(&vcpu->arch.reset_cntx_lock); - - kvm_make_request(KVM_REQ_VCPU_RESET, vcpu); + kvm_riscv_vcpu_sbi_request_reset(vcpu, cp->a1, cp->a2); =20 /* userspace provides the suspend implementation */ kvm_riscv_vcpu_sbi_forward(vcpu, run); --=20 2.48.1 From nobody Thu Apr 10 22:41:52 2025 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22BBB24C076 for ; Thu, 3 Apr 2025 11:32:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal: i=1; 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[31.30.173.141]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c301a7045sm1584106f8f.39.2025.04.03.04.32.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Apr 2025 04:32:14 -0700 (PDT) From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= To: kvm-riscv@lists.infradead.org Cc: kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andrew Jones , Mayuresh Chitale Subject: [PATCH 3/5] KVM: RISC-V: remove unnecessary SBI reset state Date: Thu, 3 Apr 2025 13:25:22 +0200 Message-ID: <20250403112522.1566629-6-rkrcmar@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250403112522.1566629-3-rkrcmar@ventanamicro.com> References: <20250403112522.1566629-3-rkrcmar@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The SBI reset state has only two variables -- pc and a1. The rest is known, so keep only the necessary information. The reset structures make sense if we want userspace to control the reset state (which we do), but I'd still remove them now and reintroduce with the userspace interface later -- we could probably have just a single reset state per VM, instead of a reset state for each VCPU. Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 --- arch/riscv/include/asm/kvm_aia.h | 3 -- arch/riscv/include/asm/kvm_host.h | 12 ++++--- arch/riscv/kvm/aia_device.c | 4 +-- arch/riscv/kvm/vcpu.c | 58 +++++++++++++++++-------------- arch/riscv/kvm/vcpu_sbi.c | 9 +++-- 5 files changed, 44 insertions(+), 42 deletions(-) diff --git a/arch/riscv/include/asm/kvm_aia.h b/arch/riscv/include/asm/kvm_= aia.h index 1f37b600ca47..3b643b9efc07 100644 --- a/arch/riscv/include/asm/kvm_aia.h +++ b/arch/riscv/include/asm/kvm_aia.h @@ -63,9 +63,6 @@ struct kvm_vcpu_aia { /* CPU AIA CSR context of Guest VCPU */ struct kvm_vcpu_aia_csr guest_csr; =20 - /* CPU AIA CSR context upon Guest VCPU reset */ - struct kvm_vcpu_aia_csr guest_reset_csr; - /* Guest physical address of IMSIC for this VCPU */ gpa_t imsic_addr; =20 diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm= _host.h index 0e9c2fab6378..0c8c9c05af91 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -193,6 +193,12 @@ struct kvm_vcpu_smstateen_csr { unsigned long sstateen0; }; =20 +struct kvm_vcpu_reset_state { + spinlock_t lock; + unsigned long pc; + unsigned long a1; +}; + struct kvm_vcpu_arch { /* VCPU ran at least once */ bool ran_atleast_once; @@ -227,12 +233,8 @@ struct kvm_vcpu_arch { /* CPU Smstateen CSR context of Guest VCPU */ struct kvm_vcpu_smstateen_csr smstateen_csr; =20 - /* CPU context upon Guest VCPU reset */ - struct kvm_cpu_context guest_reset_context; - spinlock_t reset_cntx_lock; + struct kvm_vcpu_reset_state reset_state; =20 - /* CPU CSR context upon Guest VCPU reset */ - struct kvm_vcpu_csr guest_reset_csr; =20 /* * VCPU interrupts diff --git a/arch/riscv/kvm/aia_device.c b/arch/riscv/kvm/aia_device.c index 39cd26af5a69..43e472ff3e1a 100644 --- a/arch/riscv/kvm/aia_device.c +++ b/arch/riscv/kvm/aia_device.c @@ -526,12 +526,10 @@ int kvm_riscv_vcpu_aia_update(struct kvm_vcpu *vcpu) void kvm_riscv_vcpu_aia_reset(struct kvm_vcpu *vcpu) { struct kvm_vcpu_aia_csr *csr =3D &vcpu->arch.aia_context.guest_csr; - struct kvm_vcpu_aia_csr *reset_csr =3D - &vcpu->arch.aia_context.guest_reset_csr; =20 if (!kvm_riscv_aia_available()) return; - memcpy(csr, reset_csr, sizeof(*csr)); + memset(csr, 0, sizeof(*csr)); =20 /* Proceed only if AIA was initialized successfully */ if (!kvm_riscv_aia_initialized(vcpu->kvm)) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 2fb75288ecfe..b8485c1c1ce4 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -51,13 +51,40 @@ const struct kvm_stats_header kvm_vcpu_stats_header =3D= { sizeof(kvm_vcpu_stats_desc), }; =20 -static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) +static void kvm_riscv_vcpu_context_reset(struct kvm_vcpu *vcpu) { struct kvm_vcpu_csr *csr =3D &vcpu->arch.guest_csr; - struct kvm_vcpu_csr *reset_csr =3D &vcpu->arch.guest_reset_csr; struct kvm_cpu_context *cntx =3D &vcpu->arch.guest_context; - struct kvm_cpu_context *reset_cntx =3D &vcpu->arch.guest_reset_context; + struct kvm_vcpu_reset_state *reset_state =3D &vcpu->arch.reset_state; void *vector_datap =3D cntx->vector.datap; + + memset(cntx, 0, sizeof(*cntx)); + memset(csr, 0, sizeof(*csr)); + + /* Restore datap as it's not a part of the guest context. */ + cntx->vector.datap =3D vector_datap; + + /* Load SBI reset values */ + cntx->a0 =3D vcpu->vcpu_id; + + spin_lock(&reset_state->lock); + cntx->sepc =3D reset_state->pc; + cntx->a1 =3D reset_state->a1; + spin_unlock(&reset_state->lock); + + /* Setup reset state of shadow SSTATUS and HSTATUS CSRs */ + cntx->sstatus =3D SR_SPP | SR_SPIE; + + cntx->hstatus |=3D HSTATUS_VTW; + cntx->hstatus |=3D HSTATUS_SPVP; + cntx->hstatus |=3D HSTATUS_SPV; + + /* By default, make CY, TM, and IR counters accessible in VU mode */ + csr->scounteren =3D 0x7; +} + +static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) +{ bool loaded; =20 /** @@ -72,16 +99,10 @@ static void kvm_riscv_reset_vcpu(struct kvm_vcpu *vcpu) =20 vcpu->arch.last_exit_cpu =3D -1; =20 - memcpy(csr, reset_csr, sizeof(*csr)); - - spin_lock(&vcpu->arch.reset_cntx_lock); - memcpy(cntx, reset_cntx, sizeof(*cntx)); - spin_unlock(&vcpu->arch.reset_cntx_lock); + kvm_riscv_vcpu_context_reset(vcpu); =20 kvm_riscv_vcpu_fp_reset(vcpu); =20 - /* Restore datap as it's not a part of the guest context. */ - cntx->vector.datap =3D vector_datap; kvm_riscv_vcpu_vector_reset(vcpu); =20 kvm_riscv_vcpu_timer_reset(vcpu); @@ -113,8 +134,6 @@ int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned i= nt id) int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) { int rc; - struct kvm_cpu_context *cntx; - struct kvm_vcpu_csr *reset_csr =3D &vcpu->arch.guest_reset_csr; =20 spin_lock_init(&vcpu->arch.mp_state_lock); =20 @@ -134,24 +153,11 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) /* Setup VCPU hfence queue */ spin_lock_init(&vcpu->arch.hfence_lock); =20 - /* Setup reset state of shadow SSTATUS and HSTATUS CSRs */ - spin_lock_init(&vcpu->arch.reset_cntx_lock); - - spin_lock(&vcpu->arch.reset_cntx_lock); - cntx =3D &vcpu->arch.guest_reset_context; - cntx->sstatus =3D SR_SPP | SR_SPIE; - cntx->hstatus =3D 0; - cntx->hstatus |=3D HSTATUS_VTW; - cntx->hstatus |=3D HSTATUS_SPVP; - cntx->hstatus |=3D HSTATUS_SPV; - spin_unlock(&vcpu->arch.reset_cntx_lock); + spin_lock_init(&vcpu->arch.reset_state.lock); =20 if (kvm_riscv_vcpu_alloc_vector_context(vcpu)) return -ENOMEM; =20 - /* By default, make CY, TM, and IR counters accessible in VU mode */ - reset_csr->scounteren =3D 0x7; - /* Setup VCPU timer */ kvm_riscv_vcpu_timer_init(vcpu); =20 diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index f58368f7df1d..3d7955e05cc3 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -159,11 +159,10 @@ void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu = *vcpu, void kvm_riscv_vcpu_sbi_request_reset(struct kvm_vcpu *vcpu, unsigned long pc, unsigned long a1) { - spin_lock(&vcpu->arch.reset_cntx_lock); - vcpu->arch.guest_reset_context.sepc =3D pc; - vcpu->arch.guest_reset_context.a0 =3D vcpu->vcpu_id; - vcpu->arch.guest_reset_context.a1 =3D a1; - spin_unlock(&vcpu->arch.reset_cntx_lock); + spin_lock(&vcpu->arch.reset_state.lock); + vcpu->arch.reset_state.pc =3D pc; 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[31.30.173.141]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c3020d6b1sm1575928f8f.62.2025.04.03.04.32.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Apr 2025 04:32:14 -0700 (PDT) From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= To: kvm-riscv@lists.infradead.org Cc: kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andrew Jones , Mayuresh Chitale Subject: [PATCH 4/5] KVM: RISC-V: reset VCPU state when becoming runnable Date: Thu, 3 Apr 2025 13:25:23 +0200 Message-ID: <20250403112522.1566629-7-rkrcmar@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250403112522.1566629-3-rkrcmar@ventanamicro.com> References: <20250403112522.1566629-3-rkrcmar@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Beware, this patch is "breaking" the userspace interface, because it fixes a KVM/QEMU bug where the boot VCPU is not being reset by KVM. The VCPU reset paths are inconsistent right now. KVM resets VCPUs that are brought up by KVM-accelerated SBI calls, but does nothing for VCPUs brought up through ioctls. We need to perform a KVM reset even when the VCPU is started through an ioctl. This patch is one of the ways we can achieve it. Assume that userspace has no business setting the post-reset state. KVM is de-facto the SBI implementation, as the SBI HSM acceleration cannot be disabled and userspace cannot control the reset state, so KVM should be in full control of the post-reset state. Do not reset the pc and a1 registers, because SBI reset is expected to provide them and KVM has no idea what these registers should be -- only the userspace knows where it put the data. An important consideration is resume. Userspace might want to start with non-reset state. Check ran_atleast_once to allow this, because KVM-SBI HSM creates some VCPUs as STOPPED. The drawback is that userspace can still start the boot VCPU with an incorrect reset state, because there is no way to distinguish a freshly reset new VCPU on the KVM side (userspace might set some values by mistake) from a restored VCPU (userspace must set all values). The advantage of this solution is that it fixes current QEMU and makes some sense with the assumption that KVM implements SBI HSM. I do not like it too much, so I'd be in favor of a different solution if we can still afford to drop support for current userspaces. For a cleaner solution, we should add interfaces to perform the KVM-SBI reset request on userspace demand. I think it would also be much better if userspace was in control of the post-reset state. Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 --- arch/riscv/include/asm/kvm_host.h | 1 + arch/riscv/include/asm/kvm_vcpu_sbi.h | 3 +++ arch/riscv/kvm/vcpu.c | 9 +++++++++ arch/riscv/kvm/vcpu_sbi.c | 21 +++++++++++++++++++-- 4 files changed, 32 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/kvm_host.h b/arch/riscv/include/asm/kvm= _host.h index 0c8c9c05af91..9bbf8c4a286b 100644 --- a/arch/riscv/include/asm/kvm_host.h +++ b/arch/riscv/include/asm/kvm_host.h @@ -195,6 +195,7 @@ struct kvm_vcpu_smstateen_csr { =20 struct kvm_vcpu_reset_state { spinlock_t lock; + bool active; unsigned long pc; unsigned long a1; }; diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm= /kvm_vcpu_sbi.h index aaaa81355276..2c334a87e02a 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -57,6 +57,9 @@ void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu *vcp= u, u32 type, u64 flags); void kvm_riscv_vcpu_sbi_request_reset(struct kvm_vcpu *vcpu, unsigned long pc, unsigned long a1); +void __kvm_riscv_vcpu_set_reset_state(struct kvm_vcpu *vcpu, + unsigned long pc, unsigned long a1); +void kvm_riscv_vcpu_sbi_request_reset_from_userspace(struct kvm_vcpu *vcpu= ); int kvm_riscv_vcpu_sbi_return(struct kvm_vcpu *vcpu, struct kvm_run *run); int kvm_riscv_vcpu_set_reg_sbi_ext(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index b8485c1c1ce4..4578863a39e3 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -58,6 +58,11 @@ static void kvm_riscv_vcpu_context_reset(struct kvm_vcpu= *vcpu) struct kvm_vcpu_reset_state *reset_state =3D &vcpu->arch.reset_state; void *vector_datap =3D cntx->vector.datap; =20 + spin_lock(&reset_state->lock); + if (!reset_state->active) + __kvm_riscv_vcpu_set_reset_state(vcpu, cntx->sepc, cntx->a1); + spin_unlock(&reset_state->lock); + memset(cntx, 0, sizeof(*cntx)); memset(csr, 0, sizeof(*csr)); =20 @@ -520,6 +525,10 @@ int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *v= cpu, =20 switch (mp_state->mp_state) { case KVM_MP_STATE_RUNNABLE: + if (riscv_vcpu_supports_sbi_ext(vcpu, KVM_RISCV_SBI_EXT_HSM) && + vcpu->arch.ran_atleast_once && + kvm_riscv_vcpu_stopped(vcpu)) + kvm_riscv_vcpu_sbi_request_reset_from_userspace(vcpu); WRITE_ONCE(vcpu->arch.mp_state, *mp_state); break; case KVM_MP_STATE_STOPPED: diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 3d7955e05cc3..77f9f0bd3842 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -156,12 +156,29 @@ void kvm_riscv_vcpu_sbi_system_reset(struct kvm_vcpu = *vcpu, run->exit_reason =3D KVM_EXIT_SYSTEM_EVENT; } =20 +/* must be called with held vcpu->arch.reset_state.lock */ +void __kvm_riscv_vcpu_set_reset_state(struct kvm_vcpu *vcpu, + unsigned long pc, unsigned long a1) +{ + vcpu->arch.reset_state.active =3D true; + vcpu->arch.reset_state.pc =3D pc; + vcpu->arch.reset_state.a1 =3D a1; +} + void kvm_riscv_vcpu_sbi_request_reset(struct kvm_vcpu *vcpu, unsigned long pc, unsigned long a1) { spin_lock(&vcpu->arch.reset_state.lock); - vcpu->arch.reset_state.pc =3D pc; - vcpu->arch.reset_state.a1 =3D a1; + __kvm_riscv_vcpu_set_reset_state(vcpu, pc, a1); + spin_unlock(&vcpu->arch.reset_state.lock); + + kvm_make_request(KVM_REQ_VCPU_RESET, vcpu); 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[31.30.173.141]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ec169b4e4sm19424775e9.20.2025.04.03.04.32.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Apr 2025 04:32:16 -0700 (PDT) From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= To: kvm-riscv@lists.infradead.org Cc: kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Andrew Jones , Mayuresh Chitale Subject: [PATCH 5/5] KVM: RISC-V: reset smstateen CSRs Date: Thu, 3 Apr 2025 13:25:24 +0200 Message-ID: <20250403112522.1566629-8-rkrcmar@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250403112522.1566629-3-rkrcmar@ventanamicro.com> References: <20250403112522.1566629-3-rkrcmar@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Not resetting smstateen is a potential security hole, because VU might be able to access state that VS does not properly context-switch. Fixes: 81f0f314fec9 ("RISCV: KVM: Add sstateen0 context save/restore") Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 --- arch/riscv/kvm/vcpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 4578863a39e3..ac0fa50bc489 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -65,6 +65,7 @@ static void kvm_riscv_vcpu_context_reset(struct kvm_vcpu = *vcpu) =20 memset(cntx, 0, sizeof(*cntx)); memset(csr, 0, sizeof(*csr)); + memset(&vcpu->arch.smstateen_csr, 0, sizeof(vcpu->arch.smstateen_csr)); =20 /* Restore datap as it's not a part of the guest context. */ cntx->vector.datap =3D vector_datap; --=20 2.48.1