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From: Michal Wilczynski <m.wilczynski@samsung.com>
To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org,
wefu@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com,
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Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Michal
Wilczynski <m.wilczynski@samsung.com>, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org>, Conor Dooley <conor.dooley@microchip.com>
Subject: [PATCH v7 1/3] dt-bindings: clock: thead: Add TH1520 VO clock
controller
Date: Thu, 3 Apr 2025 11:44:23 +0200
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eZrT3DUp//4sPmYrW7UtuOvg3sefw52mndvuwJvVdrnzxxm5iV/0nMWnl3pyyf92VC7IaSyJ
iOmXq36/YnnatbMGVne/vuj29Lp5Wuri/I5ADY/Jtz78UTOWeNH4eUfmX+u3py28pm4NVjw9
oep4RAzr3xWnVm+5wJL928nyYNaFK+Y6v5ybeHPTAmK4Fe/+OnDibsB1l9kfNi7JTP4Q3H7w
zeqql1t3XuYX0dLZvp5nweb05ay2xyryzCN7Dx6Vf8Zwbz3fiibRe9oXWldNMOq89qrp4Q/e
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2SASMhLXul+yQNjCEn+udbFBFL1ilDi58RZYEZuAkcSD5fNZQRIiAheYJHatWw02illgMpPE
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XnJ+7iZGYPxvO/Zz8w7Gea8+6h1iZOJgPMQowcGsJMJbqPU2XYg3JbGyKrUoP76oNCe1+BCj
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References: <20250403094425.876981-1-m.wilczynski@samsung.com>
<CGME20250403094431eucas1p21412dff1c24aae077fdfeef08e0f802b@eucas1p2.samsung.com>
Add device tree bindings for the TH1520 Video Output (VO) subsystem
clock controller. The VO sub-system manages clock gates for multimedia
components including HDMI, MIPI, and GPU.
Document the VIDEO_PLL requirements for the VO clock controller, which
receives its input from the AP clock controller. The VIDEO_PLL is a
Silicon Creations Sigma-Delta (integer) PLL typically running at 792 MHz
with maximum FOUTVCO of 2376 MHz.
This binding complements the existing AP sub-system clock controller
which manages CPU, DPU, GMAC and TEE PLLs.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Reviewed-by: Drew Fustini <drew@pdp7.com>
---
.../bindings/clock/thead,th1520-clk-ap.yaml | 17 ++++++++--
.../dt-bindings/clock/thead,th1520-clk-ap.h | 34 +++++++++++++++++++
2 files changed, 48 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.ya=
ml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
index 0129bd0ba4b3..9d058c00ab3d 100644
--- a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
+++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
@@ -8,7 +8,8 @@ title: T-HEAD TH1520 AP sub-system clock controller
=20
description: |
The T-HEAD TH1520 AP sub-system clock controller configures the
- CPU, DPU, GMAC and TEE PLLs.
+ CPU, DPU, GMAC and TEE PLLs. Additionally the VO subsystem configures
+ the clock gates for the HDMI, MIPI and the GPU.
=20
SoC reference manual
https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH15=
20%20System%20User%20Manual.pdf
@@ -20,14 +21,24 @@ maintainers:
=20
properties:
compatible:
- const: thead,th1520-clk-ap
+ enum:
+ - thead,th1520-clk-ap
+ - thead,th1520-clk-vo
=20
reg:
maxItems: 1
=20
clocks:
items:
- - description: main oscillator (24MHz)
+ - description: |
+ One input clock:
+ - For "thead,th1520-clk-ap": the clock input must be the 24 MHz
+ main oscillator.
+ - For "thead,th1520-clk-vo": the clock input must be the VIDEO_P=
LL,
+ which is configured by the AP clock controller. According to t=
he
+ TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL
+ (integer PLL) typically running at 792 MHz (FOUTPOSTDIV), with
+ a maximum FOUTVCO of 2376 MHz.
=20
"#clock-cells":
const: 1
diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-b=
indings/clock/thead,th1520-clk-ap.h
index a199784b3512..09a9aa7b3ab1 100644
--- a/include/dt-bindings/clock/thead,th1520-clk-ap.h
+++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h
@@ -93,4 +93,38 @@
#define CLK_SRAM3 83
#define CLK_PLL_GMAC_100M 84
#define CLK_UART_SCLK 85
+
+/* VO clocks */
+#define CLK_AXI4_VO_ACLK 0
+#define CLK_GPU_MEM 1
+#define CLK_GPU_CORE 2
+#define CLK_GPU_CFG_ACLK 3
+#define CLK_DPU_PIXELCLK0 4
+#define CLK_DPU_PIXELCLK1 5
+#define CLK_DPU_HCLK 6
+#define CLK_DPU_ACLK 7
+#define CLK_DPU_CCLK 8
+#define CLK_HDMI_SFR 9
+#define CLK_HDMI_PCLK 10
+#define CLK_HDMI_CEC 11
+#define CLK_MIPI_DSI0_PCLK 12
+#define CLK_MIPI_DSI1_PCLK 13
+#define CLK_MIPI_DSI0_CFG 14
+#define CLK_MIPI_DSI1_CFG 15
+#define CLK_MIPI_DSI0_REFCLK 16
+#define CLK_MIPI_DSI1_REFCLK 17
+#define CLK_HDMI_I2S 18
+#define CLK_X2H_DPU1_ACLK 19
+#define CLK_X2H_DPU_ACLK 20
+#define CLK_AXI4_VO_PCLK 21
+#define CLK_IOPMP_VOSYS_DPU_PCLK 22
+#define CLK_IOPMP_VOSYS_DPU1_PCLK 23
+#define CLK_IOPMP_VOSYS_GPU_PCLK 24
+#define CLK_IOPMP_DPU1_ACLK 25
+#define CLK_IOPMP_DPU_ACLK 26
+#define CLK_IOPMP_GPU_ACLK 27
+#define CLK_MIPIDSI0_PIXCLK 28
+#define CLK_MIPIDSI1_PIXCLK 29
+#define CLK_HDMI_PIXCLK 30
+
#endif
--=20
2.34.1
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From: Michal Wilczynski <m.wilczynski@samsung.com>
To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org,
wefu@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, jszhang@kernel.org,
p.zabel@pengutronix.de, m.szyprowski@samsung.com
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Michal
Wilczynski <m.wilczynski@samsung.com>
Subject: [PATCH v7 2/3] clk: thead: Add clock support for VO subsystem in
T-HEAD TH1520 SoC
Date: Thu, 3 Apr 2025 11:44:24 +0200
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KMHBrCTCW6j1Nl2INyWxsiq1KD++qDQntfgQozQHi5I476L9relCAumJJanZqakFqUUwWSYO
TqkGJsknEt/cvENiDFiqFidPYQ62iYkqLm6+fKoxRu1a4lF3xr0uT895BjVMeF8ruMzs7lwV
eYUpAkYOySqPjYKnR/889EklvHnB1qQHSqo7L6x//PZJc2iXqt3f9Fe/r743E+OxmLGK42/N
hbI3k48Kfzh1hi2U9f3qp2zdc0pXeGUYTKsP2v32OgvHBv57ERw5a9h5g95Pe2bN0fduWWEC
d2zWS/ntLL9yjgnfdW7W092uHK3O0JxZn/lXxvzvw205yxfrlVe/vT4rS+Ch8XeRrdPmFTxY
U2nw+ObG4oI3e/8JeLXNmLL4b6XhkQ0Fn0WTFbgv6xWdF3VZPfXnJ/t/bi1bz3SmnFzCMuuj
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WP91PpPFxVOuFnfvnWCxeHm5h9mibRa/xf89O9gt/l3byGLRsn8Ki4OIx/sbreweb16+ZPE4
3PGF3ePeiWmsHptWdbJ5bF5S79Gy9hiTR/9fA4/3+66yefRtWcXocan5OrvH501yATxRejZF
+aUlqQoZ+cUltkrRhhZGeoaWFnpGJpZ6hsbmsVZGpkr6djYpqTmZZalF+nYJehm3bv1jLHgQ
UTHh+RGmBsZj3l2MnBwSAiYSb+ctYO1i5OIQEljKKHFq/W1miISMxLXulywQtrDEn2tdbBBF
rxglbjS3sIEk2ASMJB4snw/WLSJwgUli17rVTCAOs8A6Rokp23cwgVQJC0RLLFzfzApiswio
SnRe2gO2glfATuL1nj42iBXyEvsPngWLcwrYS2yY8pgRxBYCqvlzsx+qXlDi5MwnYCcxA9U3
b53NPIFRYBaS1CwkqQWMTKsYRVJLi3PTc4uN9IoTc4tL89L1kvNzNzECI3vbsZ9bdjCufPVR
7xAjEwfjIUYJDmYlEd5CrbfpQrwpiZVVqUX58UWlOanFhxhNge6eyCwlmpwPTC15JfGGZgam
hiZmlgamlmbGSuK8bFfOpwkJpCeWpGanphakFsH0MXFwSjUwzf/0V7dG68YWFrErclvfxUvK
3Q/k3hdl7blm2pz+RbHiU+5VXV3drcz2MDtMQGB+WPWkS5f+Gq20Kj5avvRgtGNJo1Tf+Tlu
q3z4LVZnT978rztgouOdArEJ6wWkdhsJ7a7mvWzVsGJbvbjFqkvf0vvCNxU08l2Rl3DKKVV8
tORTx77JQcWFu/d8bNDsFi76/8nxhphf5blWkdv2M3w4FPrqj4pNnvLVOEhK6dENK56ysg1z
w1pL2HNdlzNyR3Ut2s366U1X9c1lnz8zeC9ewrD5pqfbW8Nc5xcbQ28UTCiQczDpY/lnNz/B
5b6tn4RRW8HsKxM2PCo6+FHrtUsgh9JxK9tF6d2z0u6q8B9XYinOSDTUYi4qTgQAVL26GXUD
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References: <20250403094425.876981-1-m.wilczynski@samsung.com>
<CGME20250403094432eucas1p112aada697802092266bc36ef863f4299@eucas1p1.samsung.com>
The T-Head TH1520 SoC integrates a variety of clocks for its subsystems,
including the Application Processor (AP) and the Video Output (VO) [1].
Up until now, the T-Head clock driver only supported AP clocks.
Extend the driver to provide clock functionality for the VO subsystem.
At this stage, the focus is on implementing the VO clock gates, as these
are currently the most relevant and required components for enabling and
disabling the VO subsystem functionality. Future enhancements may
introduce additional VO-related clocks as necessary.
Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/T=
H1520%20System%20User%20Manual.pdf [1]
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Reviewed-by: Drew Fustini <drew@pdp7.com>
---
drivers/clk/thead/clk-th1520-ap.c | 196 +++++++++++++++++++++++++-----
1 file changed, 168 insertions(+), 28 deletions(-)
diff --git a/drivers/clk/thead/clk-th1520-ap.c b/drivers/clk/thead/clk-th15=
20-ap.c
index 4c9555fc6184..ebfb1d59401d 100644
--- a/drivers/clk/thead/clk-th1520-ap.c
+++ b/drivers/clk/thead/clk-th1520-ap.c
@@ -847,6 +847,67 @@ static CCU_GATE(CLK_SRAM1, sram1_clk, "sram1", axi_acl=
k_pd, 0x20c, BIT(3), 0);
static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2", axi_aclk_pd, 0x20c, BIT(2),=
0);
static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", axi_aclk_pd, 0x20c, BIT(1),=
0);
=20
+static CCU_GATE(CLK_AXI4_VO_ACLK, axi4_vo_aclk, "axi4-vo-aclk",
+ video_pll_clk_pd, 0x0, BIT(0), 0);
+static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk", video_pll_clk_=
pd,
+ 0x0, BIT(3), 0);
+static CCU_GATE(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk",
+ video_pll_clk_pd, 0x0, BIT(4), 0);
+static CCU_GATE(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk",
+ video_pll_clk_pd, 0x0, BIT(5), 0);
+static CCU_GATE(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk",
+ video_pll_clk_pd, 0x0, BIT(6), 0);
+static CCU_GATE(CLK_DPU_HCLK, dpu_hclk, "dpu-hclk", video_pll_clk_pd, 0x0,
+ BIT(7), 0);
+static CCU_GATE(CLK_DPU_ACLK, dpu_aclk, "dpu-aclk", video_pll_clk_pd, 0x0,
+ BIT(8), 0);
+static CCU_GATE(CLK_DPU_CCLK, dpu_cclk, "dpu-cclk", video_pll_clk_pd, 0x0,
+ BIT(9), 0);
+static CCU_GATE(CLK_HDMI_SFR, hdmi_sfr_clk, "hdmi-sfr-clk", video_pll_clk_=
pd,
+ 0x0, BIT(10), 0);
+static CCU_GATE(CLK_HDMI_PCLK, hdmi_pclk, "hdmi-pclk", video_pll_clk_pd, 0=
x0,
+ BIT(11), 0);
+static CCU_GATE(CLK_HDMI_CEC, hdmi_cec_clk, "hdmi-cec-clk", video_pll_clk_=
pd,
+ 0x0, BIT(12), 0);
+static CCU_GATE(CLK_MIPI_DSI0_PCLK, mipi_dsi0_pclk, "mipi-dsi0-pclk",
+ video_pll_clk_pd, 0x0, BIT(13), 0);
+static CCU_GATE(CLK_MIPI_DSI1_PCLK, mipi_dsi1_pclk, "mipi-dsi1-pclk",
+ video_pll_clk_pd, 0x0, BIT(14), 0);
+static CCU_GATE(CLK_MIPI_DSI0_CFG, mipi_dsi0_cfg_clk, "mipi-dsi0-cfg-clk",
+ video_pll_clk_pd, 0x0, BIT(15), 0);
+static CCU_GATE(CLK_MIPI_DSI1_CFG, mipi_dsi1_cfg_clk, "mipi-dsi1-cfg-clk",
+ video_pll_clk_pd, 0x0, BIT(16), 0);
+static CCU_GATE(CLK_MIPI_DSI0_REFCLK, mipi_dsi0_refclk, "mipi-dsi0-refclk",
+ video_pll_clk_pd, 0x0, BIT(17), 0);
+static CCU_GATE(CLK_MIPI_DSI1_REFCLK, mipi_dsi1_refclk, "mipi-dsi1-refclk",
+ video_pll_clk_pd, 0x0, BIT(18), 0);
+static CCU_GATE(CLK_HDMI_I2S, hdmi_i2s_clk, "hdmi-i2s-clk", video_pll_clk_=
pd,
+ 0x0, BIT(19), 0);
+static CCU_GATE(CLK_X2H_DPU1_ACLK, x2h_dpu1_aclk, "x2h-dpu1-aclk",
+ video_pll_clk_pd, 0x0, BIT(20), 0);
+static CCU_GATE(CLK_X2H_DPU_ACLK, x2h_dpu_aclk, "x2h-dpu-aclk",
+ video_pll_clk_pd, 0x0, BIT(21), 0);
+static CCU_GATE(CLK_AXI4_VO_PCLK, axi4_vo_pclk, "axi4-vo-pclk",
+ video_pll_clk_pd, 0x0, BIT(22), 0);
+static CCU_GATE(CLK_IOPMP_VOSYS_DPU_PCLK, iopmp_vosys_dpu_pclk,
+ "iopmp-vosys-dpu-pclk", video_pll_clk_pd, 0x0, BIT(23), 0);
+static CCU_GATE(CLK_IOPMP_VOSYS_DPU1_PCLK, iopmp_vosys_dpu1_pclk,
+ "iopmp-vosys-dpu1-pclk", video_pll_clk_pd, 0x0, BIT(24), 0);
+static CCU_GATE(CLK_IOPMP_VOSYS_GPU_PCLK, iopmp_vosys_gpu_pclk,
+ "iopmp-vosys-gpu-pclk", video_pll_clk_pd, 0x0, BIT(25), 0);
+static CCU_GATE(CLK_IOPMP_DPU1_ACLK, iopmp_dpu1_aclk, "iopmp-dpu1-aclk",
+ video_pll_clk_pd, 0x0, BIT(27), 0);
+static CCU_GATE(CLK_IOPMP_DPU_ACLK, iopmp_dpu_aclk, "iopmp-dpu-aclk",
+ video_pll_clk_pd, 0x0, BIT(28), 0);
+static CCU_GATE(CLK_IOPMP_GPU_ACLK, iopmp_gpu_aclk, "iopmp-gpu-aclk",
+ video_pll_clk_pd, 0x0, BIT(29), 0);
+static CCU_GATE(CLK_MIPIDSI0_PIXCLK, mipi_dsi0_pixclk, "mipi-dsi0-pixclk",
+ video_pll_clk_pd, 0x0, BIT(30), 0);
+static CCU_GATE(CLK_MIPIDSI1_PIXCLK, mipi_dsi1_pixclk, "mipi-dsi1-pixclk",
+ video_pll_clk_pd, 0x0, BIT(31), 0);
+static CCU_GATE(CLK_HDMI_PIXCLK, hdmi_pixclk, "hdmi-pixclk", video_pll_clk=
_pd,
+ 0x4, BIT(0), 0);
+
static CLK_FIXED_FACTOR_HW(gmac_pll_clk_100m, "gmac-pll-clk-100m",
&gmac_pll_clk.common.hw, 10, 1, 0);
=20
@@ -963,7 +1024,38 @@ static struct ccu_common *th1520_gate_clks[] =3D {
&sram3_clk.common,
};
=20
-#define NR_CLKS (CLK_UART_SCLK + 1)
+static struct ccu_common *th1520_vo_gate_clks[] =3D {
+ &axi4_vo_aclk.common,
+ &gpu_core_clk.common,
+ &gpu_cfg_aclk.common,
+ &dpu0_pixelclk.common,
+ &dpu1_pixelclk.common,
+ &dpu_hclk.common,
+ &dpu_aclk.common,
+ &dpu_cclk.common,
+ &hdmi_sfr_clk.common,
+ &hdmi_pclk.common,
+ &hdmi_cec_clk.common,
+ &mipi_dsi0_pclk.common,
+ &mipi_dsi1_pclk.common,
+ &mipi_dsi0_cfg_clk.common,
+ &mipi_dsi1_cfg_clk.common,
+ &mipi_dsi0_refclk.common,
+ &mipi_dsi1_refclk.common,
+ &hdmi_i2s_clk.common,
+ &x2h_dpu1_aclk.common,
+ &x2h_dpu_aclk.common,
+ &axi4_vo_pclk.common,
+ &iopmp_vosys_dpu_pclk.common,
+ &iopmp_vosys_dpu1_pclk.common,
+ &iopmp_vosys_gpu_pclk.common,
+ &iopmp_dpu1_aclk.common,
+ &iopmp_dpu_aclk.common,
+ &iopmp_gpu_aclk.common,
+ &mipi_dsi0_pixclk.common,
+ &mipi_dsi1_pixclk.common,
+ &hdmi_pixclk.common
+};
=20
static const struct regmap_config th1520_clk_regmap_config =3D {
.reg_bits =3D 32,
@@ -972,8 +1064,44 @@ static const struct regmap_config th1520_clk_regmap_c=
onfig =3D {
.fast_io =3D true,
};
=20
+struct th1520_plat_data {
+ struct ccu_common **th1520_pll_clks;
+ struct ccu_common **th1520_div_clks;
+ struct ccu_common **th1520_mux_clks;
+ struct ccu_common **th1520_gate_clks;
+
+ int nr_clks;
+ int nr_pll_clks;
+ int nr_div_clks;
+ int nr_mux_clks;
+ int nr_gate_clks;
+};
+
+static const struct th1520_plat_data th1520_ap_platdata =3D {
+ .th1520_pll_clks =3D th1520_pll_clks,
+ .th1520_div_clks =3D th1520_div_clks,
+ .th1520_mux_clks =3D th1520_mux_clks,
+ .th1520_gate_clks =3D th1520_gate_clks,
+
+ .nr_clks =3D CLK_UART_SCLK + 1,
+
+ .nr_pll_clks =3D ARRAY_SIZE(th1520_pll_clks),
+ .nr_div_clks =3D ARRAY_SIZE(th1520_div_clks),
+ .nr_mux_clks =3D ARRAY_SIZE(th1520_mux_clks),
+ .nr_gate_clks =3D ARRAY_SIZE(th1520_gate_clks),
+};
+
+static const struct th1520_plat_data th1520_vo_platdata =3D {
+ .th1520_gate_clks =3D th1520_vo_gate_clks,
+
+ .nr_clks =3D CLK_HDMI_PIXCLK + 1,
+
+ .nr_gate_clks =3D ARRAY_SIZE(th1520_vo_gate_clks),
+};
+
static int th1520_clk_probe(struct platform_device *pdev)
{
+ const struct th1520_plat_data *plat_data;
struct device *dev =3D &pdev->dev;
struct clk_hw_onecell_data *priv;
=20
@@ -982,11 +1110,16 @@ static int th1520_clk_probe(struct platform_device *=
pdev)
struct clk_hw *hw;
int ret, i;
=20
- priv =3D devm_kzalloc(dev, struct_size(priv, hws, NR_CLKS), GFP_KERNEL);
+ plat_data =3D device_get_match_data(&pdev->dev);
+ if (!plat_data)
+ return dev_err_probe(&pdev->dev, -ENODEV,
+ "No device match data found\n");
+
+ priv =3D devm_kzalloc(dev, struct_size(priv, hws, plat_data->nr_clks), GF=
P_KERNEL);
if (!priv)
return -ENOMEM;
=20
- priv->num =3D NR_CLKS;
+ priv->num =3D plat_data->nr_clks;
=20
base =3D devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
@@ -996,35 +1129,35 @@ static int th1520_clk_probe(struct platform_device *=
pdev)
if (IS_ERR(map))
return PTR_ERR(map);
=20
- for (i =3D 0; i < ARRAY_SIZE(th1520_pll_clks); i++) {
- struct ccu_pll *cp =3D hw_to_ccu_pll(&th1520_pll_clks[i]->hw);
+ for (i =3D 0; i < plat_data->nr_pll_clks; i++) {
+ struct ccu_pll *cp =3D hw_to_ccu_pll(&plat_data->th1520_pll_clks[i]->hw);
=20
- th1520_pll_clks[i]->map =3D map;
+ plat_data->th1520_pll_clks[i]->map =3D map;
=20
- ret =3D devm_clk_hw_register(dev, &th1520_pll_clks[i]->hw);
+ ret =3D devm_clk_hw_register(dev, &plat_data->th1520_pll_clks[i]->hw);
if (ret)
return ret;
=20
priv->hws[cp->common.clkid] =3D &cp->common.hw;
}
=20
- for (i =3D 0; i < ARRAY_SIZE(th1520_div_clks); i++) {
- struct ccu_div *cd =3D hw_to_ccu_div(&th1520_div_clks[i]->hw);
+ for (i =3D 0; i < plat_data->nr_div_clks; i++) {
+ struct ccu_div *cd =3D hw_to_ccu_div(&plat_data->th1520_div_clks[i]->hw);
=20
- th1520_div_clks[i]->map =3D map;
+ plat_data->th1520_div_clks[i]->map =3D map;
=20
- ret =3D devm_clk_hw_register(dev, &th1520_div_clks[i]->hw);
+ ret =3D devm_clk_hw_register(dev, &plat_data->th1520_div_clks[i]->hw);
if (ret)
return ret;
=20
priv->hws[cd->common.clkid] =3D &cd->common.hw;
}
=20
- for (i =3D 0; i < ARRAY_SIZE(th1520_mux_clks); i++) {
- struct ccu_mux *cm =3D hw_to_ccu_mux(&th1520_mux_clks[i]->hw);
+ for (i =3D 0; i < plat_data->nr_mux_clks; i++) {
+ struct ccu_mux *cm =3D hw_to_ccu_mux(&plat_data->th1520_mux_clks[i]->hw);
const struct clk_init_data *init =3D cm->common.hw.init;
=20
- th1520_mux_clks[i]->map =3D map;
+ plat_data->th1520_mux_clks[i]->map =3D map;
hw =3D devm_clk_hw_register_mux_parent_data_table(dev,
init->name,
init->parent_data,
@@ -1040,10 +1173,10 @@ static int th1520_clk_probe(struct platform_device =
*pdev)
priv->hws[cm->common.clkid] =3D hw;
}
=20
- for (i =3D 0; i < ARRAY_SIZE(th1520_gate_clks); i++) {
- struct ccu_gate *cg =3D hw_to_ccu_gate(&th1520_gate_clks[i]->hw);
+ for (i =3D 0; i < plat_data->nr_gate_clks; i++) {
+ struct ccu_gate *cg =3D hw_to_ccu_gate(&plat_data->th1520_gate_clks[i]->=
hw);
=20
- th1520_gate_clks[i]->map =3D map;
+ plat_data->th1520_gate_clks[i]->map =3D map;
=20
hw =3D devm_clk_hw_register_gate_parent_data(dev,
cg->common.hw.init->name,
@@ -1057,19 +1190,21 @@ static int th1520_clk_probe(struct platform_device =
*pdev)
priv->hws[cg->common.clkid] =3D hw;
}
=20
- ret =3D devm_clk_hw_register(dev, &osc12m_clk.hw);
- if (ret)
- return ret;
- priv->hws[CLK_OSC12M] =3D &osc12m_clk.hw;
+ if (plat_data =3D=3D &th1520_ap_platdata) {
+ ret =3D devm_clk_hw_register(dev, &osc12m_clk.hw);
+ if (ret)
+ return ret;
+ priv->hws[CLK_OSC12M] =3D &osc12m_clk.hw;
=20
- ret =3D devm_clk_hw_register(dev, &gmac_pll_clk_100m.hw);
- if (ret)
- return ret;
- priv->hws[CLK_PLL_GMAC_100M] =3D &gmac_pll_clk_100m.hw;
+ ret =3D devm_clk_hw_register(dev, &gmac_pll_clk_100m.hw);
+ if (ret)
+ return ret;
+ priv->hws[CLK_PLL_GMAC_100M] =3D &gmac_pll_clk_100m.hw;
=20
- ret =3D devm_clk_hw_register(dev, &emmc_sdio_ref_clk.hw);
- if (ret)
- return ret;
+ ret =3D devm_clk_hw_register(dev, &emmc_sdio_ref_clk.hw);
+ if (ret)
+ return ret;
+ }
=20
ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, priv);
if (ret)
@@ -1081,6 +1216,11 @@ static int th1520_clk_probe(struct platform_device *=
pdev)
static const struct of_device_id th1520_clk_match[] =3D {
{
.compatible =3D "thead,th1520-clk-ap",
+ .data =3D &th1520_ap_platdata,
+ },
+ {
+ .compatible =3D "thead,th1520-clk-vo",
+ .data =3D &th1520_vo_platdata,
},
{ /* sentinel */ },
};
--=20
2.34.1
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From: Michal Wilczynski <m.wilczynski@samsung.com>
To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org,
wefu@redhat.com, paul.walmsley@sifive.com, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, jszhang@kernel.org,
p.zabel@pengutronix.de, m.szyprowski@samsung.com
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Michal
Wilczynski <m.wilczynski@samsung.com>
Subject: [PATCH v7 3/3] riscv: dts: thead: Add device tree VO clock
controller
Date: Thu, 3 Apr 2025 11:44:25 +0200
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References: <20250403094425.876981-1-m.wilczynski@samsung.com>
<CGME20250403094433eucas1p2da03e00ef674c1f5aa8d41f2a7371319@eucas1p2.samsung.com>
VO clocks reside in a different address space from the AP clocks on the
T-HEAD SoC. Add the device tree node of a clock-controller to handle
VO address space as well.
Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
Reviewed-by: Drew Fustini <drew@pdp7.com>
---
arch/riscv/boot/dts/thead/th1520.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th=
ead/th1520.dtsi
index 527336417765..d4cba0713cab 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -489,6 +489,13 @@ clk: clock-controller@ffef010000 {
#clock-cells =3D <1>;
};
=20
+ clk_vo: clock-controller@ffef528050 {
+ compatible =3D "thead,th1520-clk-vo";
+ reg =3D <0xff 0xef528050 0x0 0xfb0>;
+ clocks =3D <&clk CLK_VIDEO_PLL>;
+ #clock-cells =3D <1>;
+ };
+
dmac0: dma-controller@ffefc00000 {
compatible =3D "snps,axi-dma-1.01a";
reg =3D <0xff 0xefc00000 0x0 0x1000>;
--=20
2.34.1