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From: bo.kong <bo.kong@mediatek.com>
To: Rob Herring <robh@kernel.org>, AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>, Mauro Carvalho Chehab
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CC: <zhaoyuan.chen@mediatek.com>, <Teddy.Chen@mediatek.com>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: [PATCH v5 2/4] arm64: dts: mt8188: add aie node
Date: Thu, 3 Apr 2025 15:38:34 +0800
Message-ID: <20250403074005.21472-3-bo.kong@mediatek.com>
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From: Bo Kong <Bo.Kong@mediatek.com>
Add aie node and related node
Signed-off-by: Bo Kong <Bo.Kong@mediatek.com>
---
Changes in v5:
1.Modify the name of clock, change _ to -.
Changes in v4:
None
Changes in v3:
1. Remove dts non-MMIO nodes
Changes in v2:
1. Add AIE node and related node
---
arch/arm64/boot/dts/mediatek/mt8188.dtsi | 33 ++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts=
/mediatek/mt8188.dtsi
index 69a8423d3858..641de110321a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -2330,12 +2330,45 @@ imgsys_wpe1: clock-controller@15220000 {
#clock-cells =3D <1>;
};
=20
+ aie: aie@15310000 {
+ compatible =3D "mediatek,mt8188-aie";
+ reg =3D <0 0x15310000 0 0x1000>;
+ interrupts =3D <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,larb =3D <&larb12>;
+ iommus =3D <&vpp_iommu M4U_PORT_L12_FDVT_RDA_0>,
+ <&vpp_iommu M4U_PORT_L12_FDVT_RDB_0>,
+ <&vpp_iommu M4U_PORT_L12_FDVT_WRA_0>,
+ <&vpp_iommu M4U_PORT_L12_FDVT_WRB_0>;
+ power-domains =3D <&spm MT8188_POWER_DOMAIN_IPE>;
+ clocks =3D <&imgsys CLK_IMGSYS_MAIN_IPE>,
+ <&ipesys CLK_IPE_FDVT>,
+ <&ipesys CLK_IPE_SMI_LARB12>,
+ <&ipesys CLK_IPESYS_TOP>;
+ clock-names =3D "img-ipe",
+ "ipe-fdvt",
+ "ipe-smi-larb12",
+ "ipe-top";
+ };
+
ipesys: clock-controller@15330000 {
compatible =3D "mediatek,mt8188-ipesys";
reg =3D <0 0x15330000 0 0x1000>;
#clock-cells =3D <1>;
};
=20
+ larb12: larb@15340000 {
+ compatible =3D "mediatek,mt8188-smi-larb";
+ reg =3D <0 0x15340000 0 0x1000>;
+ mediatek,larb-id =3D <SMI_L12_ID>;
+ mediatek,smi =3D <&vpp_smi_common>;
+ mediatek,smi-sub-comm =3D <&smi_img1>;
+ mediatek,smi-sub-comm-inport =3D <0>;
+ clocks =3D <&imgsys CLK_IMGSYS_MAIN_IPE>,
+ <&ipesys CLK_IPE_SMI_LARB12>;
+ clock-names =3D "apb", "smi";
+ power-domains =3D <&spm MT8188_POWER_DOMAIN_IPE>;
+ };
+
imgsys_wpe2: clock-controller@15520000 {
compatible =3D "mediatek,mt8188-imgsys-wpe2";
reg =3D <0 0x15520000 0 0x1000>;
--=20
2.45.2