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[81.240.10.146]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5f087714e11sm417236a12.6.2025.04.02.22.52.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Apr 2025 22:52:12 -0700 (PDT) From: Philippe Simons To: Boris Brezillon , Rob Herring , Steven Price , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Philipp Zabel Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, Andre Przywara , =?UTF-8?q?Jernej=20=C5=A0krabec?= Subject: [PATCH v2 1/3] drm/panfrost: Add PM runtime flag Date: Thu, 3 Apr 2025 07:52:08 +0200 Message-ID: <20250403055210.54486-2-simons.philippe@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250403055210.54486-1-simons.philippe@gmail.com> References: <20250403055210.54486-1-simons.philippe@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When the GPU is the only device attached to a single power domain, core genpd disable and enable it when gpu enter and leave runtime suspend. Some power-domain requires a sequence before disabled, and the reverse when enabled. Add GPU_PM_RT flag, and implement in panfrost_device_runtime_suspend/resume. Reviewed-by: Steven Price Signed-off-by: Philippe Simons --- drivers/gpu/drm/panfrost/panfrost_device.c | 33 ++++++++++++++++++++++ drivers/gpu/drm/panfrost/panfrost_device.h | 3 ++ 2 files changed, 36 insertions(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/p= anfrost/panfrost_device.c index a45e4addcc19..93d48e97ce10 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.c +++ b/drivers/gpu/drm/panfrost/panfrost_device.c @@ -406,11 +406,36 @@ void panfrost_device_reset(struct panfrost_device *pf= dev) static int panfrost_device_runtime_resume(struct device *dev) { struct panfrost_device *pfdev =3D dev_get_drvdata(dev); + int ret; + + if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) { + ret =3D reset_control_deassert(pfdev->rstc); + if (ret) + return ret; + + ret =3D clk_enable(pfdev->clock); + if (ret) + goto err_clk; + + if (pfdev->bus_clock) { + ret =3D clk_enable(pfdev->bus_clock); + if (ret) + goto err_bus_clk; + } + } =20 panfrost_device_reset(pfdev); panfrost_devfreq_resume(pfdev); =20 return 0; + +err_bus_clk: + if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) + clk_disable(pfdev->clock); +err_clk: + if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) + reset_control_assert(pfdev->rstc); + return ret; } =20 static int panfrost_device_runtime_suspend(struct device *dev) @@ -426,6 +451,14 @@ static int panfrost_device_runtime_suspend(struct devi= ce *dev) panfrost_gpu_suspend_irq(pfdev); panfrost_gpu_power_off(pfdev); =20 + if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) { + if (pfdev->bus_clock) + clk_disable(pfdev->bus_clock); + + clk_disable(pfdev->clock); + reset_control_assert(pfdev->rstc); + } + return 0; } =20 diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/p= anfrost/panfrost_device.h index cffcb0ac7c11..861555ceea65 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.h +++ b/drivers/gpu/drm/panfrost/panfrost_device.h @@ -36,10 +36,13 @@ enum panfrost_drv_comp_bits { * enum panfrost_gpu_pm - Supported kernel power management features * @GPU_PM_CLK_DIS: Allow disabling clocks during system suspend * @GPU_PM_VREG_OFF: Allow turning off regulators during system suspend + * @GPU_PM_RT: Allow disabling clocks and asserting the reset control duri= ng + * system runtime suspend */ enum panfrost_gpu_pm { GPU_PM_CLK_DIS, GPU_PM_VREG_OFF, + GPU_PM_RT }; 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[81.240.10.146]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5f087714e11sm417236a12.6.2025.04.02.22.52.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Apr 2025 22:52:14 -0700 (PDT) From: Philippe Simons To: Boris Brezillon , Rob Herring , Steven Price , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Philipp Zabel Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, Andre Przywara , =?UTF-8?q?Jernej=20=C5=A0krabec?= Subject: [PATCH v2 2/3] drm/panfrost: add h616 compatible string Date: Thu, 3 Apr 2025 07:52:09 +0200 Message-ID: <20250403055210.54486-3-simons.philippe@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250403055210.54486-1-simons.philippe@gmail.com> References: <20250403055210.54486-1-simons.philippe@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Tie the Allwinner compatible string to the GPU_PM_RT feature bits that will toggle the clocks and the reset line whenever the power domain is changing state. Signed-off-by: Philippe Simons --- drivers/gpu/drm/panfrost/panfrost_drv.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panf= rost/panfrost_drv.c index 0f3935556ac7..9470c04c5487 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -776,6 +776,13 @@ static const struct panfrost_compatible default_data = =3D { .pm_domain_names =3D NULL, }; =20 +static const struct panfrost_compatible allwinner_h616_data =3D { + .num_supplies =3D ARRAY_SIZE(default_supplies) - 1, + .supply_names =3D default_supplies, + .num_pm_domains =3D 1, + .pm_features =3D BIT(GPU_PM_RT), +}; + static const struct panfrost_compatible amlogic_data =3D { .num_supplies =3D ARRAY_SIZE(default_supplies) - 1, .supply_names =3D default_supplies, @@ -859,6 +866,7 @@ static const struct of_device_id dt_match[] =3D { { .compatible =3D "mediatek,mt8186-mali", .data =3D &mediatek_mt8186_data= }, { .compatible =3D "mediatek,mt8188-mali", .data =3D &mediatek_mt8188_data= }, { .compatible =3D "mediatek,mt8192-mali", .data =3D &mediatek_mt8192_data= }, + { .compatible =3D "allwinner,sun50i-h616-mali", .data =3D &allwinner_h616= _data }, {} }; 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[81.240.10.146]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5f087714e11sm417236a12.6.2025.04.02.22.52.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Apr 2025 22:52:14 -0700 (PDT) From: Philippe Simons To: Boris Brezillon , Rob Herring , Steven Price , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Philipp Zabel Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, Andre Przywara , =?UTF-8?q?Jernej=20=C5=A0krabec?= Subject: [PATCH v2 3/3] drm/panfrost: reorder pd/clk/rst sequence Date: Thu, 3 Apr 2025 07:52:10 +0200 Message-ID: <20250403055210.54486-4-simons.philippe@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250403055210.54486-1-simons.philippe@gmail.com> References: <20250403055210.54486-1-simons.philippe@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" According to Mali manuals, the powerup sequence should be enable pd, asserting the reset then enabling the clock and the reverse for powerdown. Signed-off-by: Philippe Simons Tested-by: John Williams --- drivers/gpu/drm/panfrost/panfrost_device.c | 38 +++++++++++----------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/p= anfrost/panfrost_device.c index 93d48e97ce10..5d35076b2e6d 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.c +++ b/drivers/gpu/drm/panfrost/panfrost_device.c @@ -209,10 +209,20 @@ int panfrost_device_init(struct panfrost_device *pfde= v) =20 spin_lock_init(&pfdev->cycle_counter.lock); =20 + err =3D panfrost_pm_domain_init(pfdev); + if (err) + return err; + + err =3D panfrost_reset_init(pfdev); + if (err) { + dev_err(pfdev->dev, "reset init failed %d\n", err); + goto out_pm_domain; + } + err =3D panfrost_clk_init(pfdev); if (err) { dev_err(pfdev->dev, "clk init failed %d\n", err); - return err; + goto out_reset; } =20 err =3D panfrost_devfreq_init(pfdev); @@ -229,25 +239,15 @@ int panfrost_device_init(struct panfrost_device *pfde= v) goto out_devfreq; } =20 - err =3D panfrost_reset_init(pfdev); - if (err) { - dev_err(pfdev->dev, "reset init failed %d\n", err); - goto out_regulator; - } - - err =3D panfrost_pm_domain_init(pfdev); - if (err) - goto out_reset; - pfdev->iomem =3D devm_platform_ioremap_resource(pfdev->pdev, 0); if (IS_ERR(pfdev->iomem)) { err =3D PTR_ERR(pfdev->iomem); - goto out_pm_domain; + goto out_regulator; } =20 err =3D panfrost_gpu_init(pfdev); if (err) - goto out_pm_domain; + goto out_regulator; =20 err =3D panfrost_mmu_init(pfdev); if (err) @@ -268,16 +268,16 @@ int panfrost_device_init(struct panfrost_device *pfde= v) panfrost_mmu_fini(pfdev); out_gpu: panfrost_gpu_fini(pfdev); -out_pm_domain: - panfrost_pm_domain_fini(pfdev); -out_reset: - panfrost_reset_fini(pfdev); out_regulator: panfrost_regulator_fini(pfdev); out_devfreq: panfrost_devfreq_fini(pfdev); out_clk: panfrost_clk_fini(pfdev); +out_reset: + panfrost_reset_fini(pfdev); +out_pm_domain: + panfrost_pm_domain_fini(pfdev); return err; } =20 @@ -287,11 +287,11 @@ void panfrost_device_fini(struct panfrost_device *pfd= ev) panfrost_job_fini(pfdev); panfrost_mmu_fini(pfdev); panfrost_gpu_fini(pfdev); - panfrost_pm_domain_fini(pfdev); - panfrost_reset_fini(pfdev); panfrost_devfreq_fini(pfdev); panfrost_regulator_fini(pfdev); panfrost_clk_fini(pfdev); + panfrost_reset_fini(pfdev); + panfrost_pm_domain_fini(pfdev); } =20 #define PANFROST_EXCEPTION(id) \ --=20 2.49.0