From nobody Mon Feb 9 19:53:47 2026 Received: from out-170.mta1.migadu.com (out-170.mta1.migadu.com [95.215.58.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BB191FCFF2 for ; Thu, 3 Apr 2025 20:34:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.170 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743712487; cv=none; b=ac3KxXVi86m3Aw7OSBWGXaE/2PY9bfK9rMLEeb//e7C5vZERBiXZClLqW0yUJXs4AjOggSvc5Ab6J2xHLJ0ySTInIBFF00GHh9wgHhpaRQKaZsNT3ggXFMXwvX26RkkCPBM01KKUiqgUDYDtS5Ap6Dz2Ya2f+Td3jW/ikqL0Dbo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743712487; c=relaxed/simple; bh=acATyRUbnpdnRgGAcaAXJ3uINgKjESC2cn6Yqi7GuBg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VHOR7qiBf/+2TnGnH7Nf4ZOc+yUymPerPdbi8Y3m4728NGS8SOdmwCpi8txrpkvFyeI8bD6AK47c91Qgosv4rW0ZUUDLMZAE85gmCJ8bopqm3LAe62cPjPZMFNnMGLMZaG4CI8xE7wGmx/ghKDiwQRV09vgmVXHa7pB8uLSbPOw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=iencinas.com; spf=pass smtp.mailfrom=iencinas.com; dkim=pass (2048-bit key) header.d=iencinas.com header.i=@iencinas.com header.b=MIwNf3ea; arc=none smtp.client-ip=95.215.58.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=iencinas.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iencinas.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=iencinas.com header.i=@iencinas.com header.b="MIwNf3ea" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=iencinas.com; s=key1; t=1743712482; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uD5iR3j3WFLeggCmYAp0dLJAKr7cyaVudV3J9Ga4myY=; b=MIwNf3eaBPBrPG9omxufAUV6tnp5q3ry1N627DcdtUnMzfiH67FN+ZUm12lE2dQVJVcjiB bVZjU2tDudJbqxqc0ig1fsk1ti9GkNNbfEUmnqClXrVzOaOJz4JImFPCTJJ5WkBl968Bf1 8QZScsUZwv/RnH+AELw1It1J4QmMxg5SBRqAEnw2YJATgdsSie8QNRXnB2SAxGKGeCdgZU MamUC6LihnbhVDyj1xCzw3rbsqExVOW1/u4kyMKzLyvQx08MVZhaTOnqONnt/kiQbAyrYq povq+FHVJouPcG32144mW5tOJKBiWbMzBL7Ex204tZIR77KFOlAYzLRjRTC46w== From: Ignacio Encinas Date: Thu, 03 Apr 2025 22:34:18 +0200 Subject: [PATCH v3 2/2] riscv: introduce asm/swab.h Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250403-riscv-swab-v3-2-3bf705d80e33@iencinas.com> References: <20250403-riscv-swab-v3-0-3bf705d80e33@iencinas.com> In-Reply-To: <20250403-riscv-swab-v3-0-3bf705d80e33@iencinas.com> To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Arnd Bergmann Cc: Eric Biggers , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kernel-mentees@lists.linux.dev, skhan@linuxfoundation.org, Zhihang Shao , =?utf-8?q?Bj=C3=B6rn_T=C3=B6pel?= , linux-arch@vger.kernel.org, Ignacio Encinas X-Migadu-Flow: FLOW_OUT Implement endianness swap macros for RISC-V. Use the rev8 instruction when Zbb is available. Otherwise, rely on the default mask-and-shift implementation. Signed-off-by: Ignacio Encinas --- arch/riscv/include/asm/swab.h | 43 +++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 43 insertions(+) diff --git a/arch/riscv/include/asm/swab.h b/arch/riscv/include/asm/swab.h new file mode 100644 index 000000000000..7352e8405a99 --- /dev/null +++ b/arch/riscv/include/asm/swab.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef _ASM_RISCV_SWAB_H +#define _ASM_RISCV_SWAB_H + +#include +#include +#include +#include +#include + +#if defined(CONFIG_RISCV_ISA_ZBB) && !defined(NO_ALTERNATIVE) + +#define ARCH_SWAB(size) \ +static __always_inline unsigned long __arch_swab##size(__u##size value) \ +{ \ + unsigned long x =3D value; \ + \ + if (riscv_has_extension_likely(RISCV_ISA_EXT_ZBB)) { \ + asm volatile (".option push\n" \ + ".option arch,+zbb\n" \ + "rev8 %0, %1\n" \ + ".option pop\n" \ + : "=3Dr" (x) : "r" (x)); \ + return x >> (BITS_PER_LONG - size); \ + } \ + return ___constant_swab##size(value); \ +} + +#ifdef CONFIG_64BIT +ARCH_SWAB(64) +#define __arch_swab64 __arch_swab64 +#endif + +ARCH_SWAB(32) +#define __arch_swab32 __arch_swab32 + +ARCH_SWAB(16) +#define __arch_swab16 __arch_swab16 + +#undef ARCH_SWAB + +#endif /* defined(CONFIG_RISCV_ISA_ZBB) && !defined(NO_ALTERNATIVE) */ +#endif /* _ASM_RISCV_SWAB_H */ --=20 2.49.0