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From: Xianwei Zhao via B4 Relay <devnull+xianwei.zhao.amlogic.com@kernel.org>
Date: Thu, 03 Apr 2025 16:33:15 +0800
Subject: [PATCH v3 2/2] dts: arm64: amlogic: add a5 pinctrl node
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Message-Id: <20250403-a5-pinctrl-v3-2-a8c067e22295@amlogic.com>
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From: Xianwei Zhao <xianwei.zhao@amlogic.com>
Add pinctrl device to support Amlogic A5.
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
---
arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi | 90 +++++++++++++++++++++++++=
++++
1 file changed, 90 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi b/arch/arm64/boot/=
dts/amlogic/amlogic-a5.dtsi
index 32ed1776891b..844302db2133 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-a5.dtsi
@@ -4,6 +4,7 @@
*/
=20
#include "amlogic-a4-common.dtsi"
+#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
#include <dt-bindings/power/amlogic,a5-pwrc.h>
/ {
cpus {
@@ -50,6 +51,95 @@ pwrc: power-controller {
};
=20
&apb {
+ periphs_pinctrl: pinctrl@4000 {
+ compatible =3D "amlogic,pinctrl-a5",
+ "amlogic,pinctrl-a4";
+ #address-cells =3D <2>;
+ #size-cells =3D <2>;
+ ranges =3D <0x0 0x0 0x0 0x4000 0x0 0x300>;
+
+ gpioz: gpio@c0 {
+ reg =3D <0x0 0xc0 0x0 0x40>,
+ <0x0 0x18 0x0 0x8>;
+ reg-names =3D "gpio", "mux";
+ gpio-controller;
+ #gpio-cells =3D <2>;
+ gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_Z<<8) 16>;
+ };
+
+ gpiox: gpio@100 {
+ reg =3D <0x0 0x100 0x0 0x40>,
+ <0x0 0xc 0x0 0xc>;
+ reg-names =3D "gpio", "mux";
+ gpio-controller;
+ #gpio-cells =3D <2>;
+ gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_X<<8) 20>;
+ };
+
+ gpiot: gpio@140 {
+ reg =3D <0x0 0x140 0x0 0x40>,
+ <0x0 0x2c 0x0 0x8>;
+ reg-names =3D "gpio", "mux";
+ gpio-controller;
+ #gpio-cells =3D <2>;
+ gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_T<<8) 14>;
+ };
+
+ gpiod: gpio@180 {
+ reg =3D <0x0 0x180 0x0 0x40>,
+ <0x0 0x40 0x0 0x8>;
+ reg-names =3D "gpio", "mux";
+ gpio-controller;
+ #gpio-cells =3D <2>;
+ gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_D<<8) 16>;
+ };
+
+ gpioe: gpio@1c0 {
+ reg =3D <0x0 0x1c0 0x0 0x40>,
+ <0x0 0x48 0x0 0x4>;
+ reg-names =3D "gpio", "mux";
+ gpio-controller;
+ #gpio-cells =3D <2>;
+ gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_E<<8) 2>;
+ };
+
+ gpioc: gpio@200 {
+ reg =3D <0x0 0x200 0x0 0x40>,
+ <0x0 0x24 0x0 0x8>;
+ reg-names =3D "gpio", "mux";
+ gpio-controller;
+ #gpio-cells =3D <2>;
+ gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_C<<8) 11>;
+ };
+
+ gpiob: gpio@240 {
+ reg =3D <0x0 0x240 0x0 0x40>,
+ <0x0 0x0 0x0 0x8>;
+ reg-names =3D "gpio", "mux";
+ gpio-controller;
+ #gpio-cells =3D <2>;
+ gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_B<<8) 14>;
+ };
+
+ gpioh: gpio@280 {
+ reg =3D <0x0 0x280 0x0 0x40>,
+ <0x0 0x4c 0x0 0x4>;
+ reg-names =3D "gpio", "mux";
+ gpio-controller;
+ #gpio-cells =3D <2>;
+ gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_H<<8) 5>;
+ };
+
+ gpio_test_n: gpio@2c0 {
+ reg =3D <0x0 0x2c0 0x0 0x40>,
+ <0x0 0x3c 0x0 0x4>;
+ reg-names =3D "gpio", "mux";
+ gpio-controller;
+ #gpio-cells =3D <2>;
+ gpio-ranges =3D <&periphs_pinctrl 0 (AMLOGIC_GPIO_TEST_N<<8) 1>;
+ };
+ };
+
gpio_intc: interrupt-controller@4080 {
compatible =3D "amlogic,a5-gpio-intc",
"amlogic,meson-gpio-intc";
--=20
2.37.1