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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4791b1446e1sm427021cf.73.2025.04.02.16.25.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Apr 2025 16:25:56 -0700 (PDT) From: Gregory Price To: linux-cxl@vger.kernel.org Cc: linux-kernel@vger.kernel.org, kernel-team@meta.com, dan.j.williams@intel.com, vishal.l.verma@intel.com, dave.jiang@intel.com, dave@stgolabs.net, jonathan.cameron@huawei.com, alison.schofield@intel.com, ira.weiny@intel.com Subject: [PATCH v2] cxl: core/region - ignore interleave granularity when ways=1 Date: Wed, 2 Apr 2025 19:25:52 -0400 Message-ID: <20250402232552.999634-1-gourry@gourry.net> X-Mailer: git-send-email 2.49.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When validating decoder IW/IG when setting up regions, the granularity is irrelevant when iw=3D1 - all accesses will always route to the only target anyway - so all ig values are "correct". Loosen the requirement that `ig =3D (parent_iw * parent_ig)` when iw=3D1. On some Zen5 platforms, the platform BIOS specifies a 256-byte interleave granularity window for host bridges when there is only one target downstream. This leads to Linux rejecting the configuration of a region with a x2 root with two x1 hostbridges. Decoder Programming: root - iw:2 ig:256 hb1 - iw:1 ig:256 (Linux expects 512) hb2 - iw:1 ig:256 (Linux expects 512) ep1 - iw:2 ig:256 ep2 - iw:2 ig:256 This change allows all decoders downstream of a passthrough decoder to also be configured as passthrough (iw:1 ig:X), but still disallows downstream decoders from applying subsequent interleaves. e.g. in the above example if there was another decoder south of hb1 attempting to interleave 2 endpoints - Linux would enforce hb1.ig=3D512 because the southern decoder would have iw:2 and require ig=3Dpig*piw. Signed-off-by: Gregory Price Reviewed-by: Dave Jiang Reviewed-by: Dan Williams Reviewed-by: Davidlohr Bueso Reviewed-by: Jonathan Cameron Tested-by: Li Zhijian --- drivers/cxl/core/region.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index 04bc6cad092c..dec262eadf9a 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1553,7 +1553,7 @@ static int cxl_port_setup_targets(struct cxl_port *po= rt, =20 if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags)) { if (cxld->interleave_ways !=3D iw || - cxld->interleave_granularity !=3D ig || + (iw > 1 && cxld->interleave_granularity !=3D ig) || cxled->spa_range.start !=3D p->res->start || cxled->spa_range.end !=3D p->res->end || ((cxld->flags & CXL_DECODER_F_ENABLE) =3D=3D 0)) { --=20 2.47.1