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[92.26.98.202]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c0b66a8d4sm17424016f8f.45.2025.04.02.10.25.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Apr 2025 10:25:00 -0700 (PDT) From: Andrew Cooper To: LKML Cc: Andrew Cooper , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" Subject: [PATCH v2] x86/idle: Remove MFENCEs for X86_BUG_CLFLUSH_MONITOR Date: Wed, 2 Apr 2025 18:24:58 +0100 Message-Id: <20250402172458.1378112-1-andrew.cooper3@citrix.com> X-Mailer: git-send-email 2.39.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit 7e98b7192046 ("x86, idle: Use static_cpu_has() for CLFLUSH workaround, add barriers") adds barriers, justified with: ... and add memory barriers around it since the documentation is explicit that CLFLUSH is only ordered with respect to MFENCE. This also triggered the same adjustment in commit f8e617f45829 ("sched/idle/x86: Optimize unnecessary mwait_idle() resched IPIs") during development, although it failed to get the static_cpu_has_bug= () treatment. X86_BUG_CLFLUSH_MONITOR (a.k.a the AAI65 errata) is specific to Intel CPUs, and the SDM currently states: Executions of the CLFLUSH instruction are ordered with respect to each other and with respect to writes, locked read-modify-write instructions, and fence instructions[1]. With footnote 1 reading: Earlier versions of this manual specified that executions of the CLFLUSH instruction were ordered only by the MFENCE instruction. All processors implementing the CLFLUSH instruction also order it relative to the other operations enumerated above. i.e. The SDM was incorrect at the time, and barriers should not have been inserted. Double checking the original AAI65 errata (not available from intel.com any more) shows no mention of barriers either. Note: If this were a general codepath, the MFENCEs would be needed, because AMD CPUs of the same vintage do sport otherwise-unordered CLFLUSHs. Furthermore, use a plain alternative, rather than static_cpu_has_bug() and/= or no optimisation. The workaround is a single instruction. Use an explicit %rax pointer rather than a general memory operand, because MONITOR takes the pointer implicitly in the same way. Link: https://web.archive.org/web/20090219054841/http://download.intel.com/= design/xeon/specupdt/32033601.pdf Fixes: 7e98b7192046 ("x86, idle: Use static_cpu_has() for CLFLUSH workaroun= d, add barriers") Fixes: f8e617f45829 ("sched/idle/x86: Optimize unnecessary mwait_idle() res= ched IPIs") Signed-off-by: Andrew Cooper Acked-by: Dave Hansen --- CC: Thomas Gleixner CC: Ingo Molnar CC: Borislav Petkov CC: Dave Hansen CC: x86@kernel.org CC: "H. Peter Anvin" CC: linux-kernel@vger.kernel.org v2: * Fix the same pattern in mwait_idle() too * Expand on why we're not using a general memory operand. --- arch/x86/include/asm/mwait.h | 11 +++++------ arch/x86/kernel/process.c | 10 ++++------ 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/mwait.h b/arch/x86/include/asm/mwait.h index ce857ef54cf1..108d25bd4597 100644 --- a/arch/x86/include/asm/mwait.h +++ b/arch/x86/include/asm/mwait.h @@ -116,13 +116,12 @@ static __always_inline void __sti_mwait(unsigned long= eax, unsigned long ecx) static __always_inline void mwait_idle_with_hints(unsigned long eax, unsig= ned long ecx) { if (static_cpu_has_bug(X86_BUG_MONITOR) || !current_set_polling_and_test(= )) { - if (static_cpu_has_bug(X86_BUG_CLFLUSH_MONITOR)) { - mb(); - clflush((void *)¤t_thread_info()->flags); - mb(); - } =20 - __monitor((void *)¤t_thread_info()->flags, 0, 0); + const void *addr =3D ¤t_thread_info()->flags; + + alternative_input("", "clflush (%[addr])", X86_BUG_CLFLUSH_MONITOR, + [addr] "a" (addr)); + __monitor(addr, 0, 0); =20 if (!need_resched()) { if (ecx & 1) { diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 91f6ff618852..a1a41b3d94d2 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -907,13 +907,11 @@ static __init bool prefer_mwait_c1_over_halt(void) static __cpuidle void mwait_idle(void) { if (!current_set_polling_and_test()) { - if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) { - mb(); /* quirk */ - clflush((void *)¤t_thread_info()->flags); - mb(); /* quirk */ - } + const void *addr =3D ¤t_thread_info()->flags; =20 - __monitor((void *)¤t_thread_info()->flags, 0, 0); + alternative_input("", "clflush (%[addr])", X86_BUG_CLFLUSH_MONITOR, + [addr] "a" (addr)); + __monitor(addr, 0, 0); if (!need_resched()) { __sti_mwait(0, 0); raw_local_irq_disable(); base-commit: acc4d5ff0b61eb1715c498b6536c38c1feb7f3c1 --=20 2.39.5