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From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
To: tomm.merciai@gmail.com
Cc: linux-renesas-soc@vger.kernel.org,
biju.das.jz@bp.renesas.com,
Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>,
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linux-kernel@vger.kernel.org
Subject: [PATCH 1/4] clk: renesas: r9a09g047: Add clock and reset entries for
GE3D
Date: Wed, 2 Apr 2025 15:11:38 +0200
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Add CLK_PLLVDO_GPU along with the necessary clock and reset entries for
GE3D.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/r9a09g047-cpg.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a0=
9g047-cpg.c
index e9cf4342d0cfb..2aa1e0aa4d36d 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -41,6 +41,7 @@ enum clk_ids {
CLK_PLLDTY_ACPU_DIV4,
CLK_PLLDTY_DIV16,
CLK_PLLVDO_CRU0,
+ CLK_PLLVDO_GPU,
=20
/* Module Clocks */
MOD_CLK_BASE,
@@ -96,6 +97,7 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __=
initconst =3D {
DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16),
=20
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dta=
ble_2_4),
+ DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtabl=
e_2_64),
=20
/* Core Clocks */
DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
@@ -185,6 +187,12 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[]=
__initconst =3D {
BUS_MSTOP(9, BIT(4))),
DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10,
BUS_MSTOP(2, BIT(15))),
+ DEF_MOD("ge3d_clk", CLK_PLLVDO_GPU, 15, 0, 7, 16,
+ BUS_MSTOP(3, BIT(4))),
+ DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
+ BUS_MSTOP(3, BIT(4))),
+ DEF_MOD("ge3d_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18,
+ BUS_MSTOP(3, BIT(4))),
};
=20
static const struct rzv2h_reset r9a09g047_resets[] __initconst =3D {
@@ -214,6 +222,9 @@ static const struct rzv2h_reset r9a09g047_resets[] __in=
itconst =3D {
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */
+ DEF_RST(13, 13, 6, 14), /* GE3D_0_RESETN */
+ DEF_RST(13, 14, 6, 15), /* GE3D_0_AXI_RESETN */
+ DEF_RST(13, 15, 6, 16), /* GE3D_0_ACE_RESETN */
};
=20
const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst =3D {
--=20
2.43.0
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From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
To: tomm.merciai@gmail.com
Cc: linux-renesas-soc@vger.kernel.org,
biju.das.jz@bp.renesas.com,
Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>,
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dri-devel@lists.freedesktop.org,
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linux-clk@vger.kernel.org
Subject: [PATCH 2/4] dt-bindings: gpu: mali-bifrost: Add compatible for RZ/G3E
SoC
Date: Wed, 2 Apr 2025 15:11:39 +0200
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Add a compatible string for the Renesas RZ/G3E SoC variants that
include a Mali-G52 GPU. These variants share the same restrictions on
interrupts, clocks, and power domains as the RZ/G2L SoC, so extend
the existing schema validation accordingly.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/=
Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
index 019bd28a29f19..e25478f2ce521 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
@@ -25,6 +25,7 @@ properties:
- realtek,rtd1619-mali
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
+ - renesas,r9a09g047-mali
- renesas,r9a09g057-mali
- rockchip,px30-mali
- rockchip,rk3562-mali
@@ -145,6 +146,7 @@ allOf:
enum:
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
+ - renesas,r9a09g047-mali
- renesas,r9a09g057-mali
then:
properties:
--=20
2.43.0
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From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
To: tomm.merciai@gmail.com
Cc: linux-renesas-soc@vger.kernel.org,
biju.das.jz@bp.renesas.com,
Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
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Stephen Boyd <sboyd@kernel.org>,
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linux-clk@vger.kernel.org
Subject: [PATCH 3/4] arm64: dts: renesas: r9a09g047: Add Mali-G52 GPU node
Date: Wed, 2 Apr 2025 15:11:40 +0200
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Add Mali-G52 GPU node to SoC DTSI.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/d=
ts/renesas/r9a09g047.dtsi
index 4bc0b77f721ab..9ab83e949c0ea 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -105,6 +105,35 @@ L3_CA55: cache-controller-0 {
};
};
=20
+ gpu_opp_table: opp-table-1 {
+ compatible =3D "operating-points-v2";
+
+ opp-630000000 {
+ opp-hz =3D /bits/ 64 <630000000>;
+ opp-microvolt =3D <800000>;
+ };
+
+ opp-315000000 {
+ opp-hz =3D /bits/ 64 <315000000>;
+ opp-microvolt =3D <800000>;
+ };
+
+ opp-157500000 {
+ opp-hz =3D /bits/ 64 <157500000>;
+ opp-microvolt =3D <800000>;
+ };
+
+ opp-78750000 {
+ opp-hz =3D /bits/ 64 <78750000>;
+ opp-microvolt =3D <800000>;
+ };
+
+ opp-19687500 {
+ opp-hz =3D /bits/ 64 <19687500>;
+ opp-microvolt =3D <800000>;
+ };
+ };
+
psci {
compatible =3D "arm,psci-1.0", "arm,psci-0.2";
method =3D "smc";
@@ -491,6 +520,26 @@ i2c8: i2c@11c01000 {
status =3D "disabled";
};
=20
+ gpu: gpu@14850000 {
+ compatible =3D "renesas,r9a09g047-mali",
+ "arm,mali-bifrost";
+ reg =3D <0x0 0x14850000 0x0 0x10000>;
+ interrupts =3D <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names =3D "job", "mmu", "gpu", "event";
+ clocks =3D <&cpg CPG_MOD 0xf0>,
+ <&cpg CPG_MOD 0xf1>,
+ <&cpg CPG_MOD 0xf2>;
+ clock-names =3D "gpu", "bus", "bus_ace";
+ power-domains =3D <&cpg>;
+ resets =3D <&cpg 0xdd>, <&cpg 0xde>, <&cpg 0xdf>;
+ reset-names =3D "rst", "axi_rst", "ace_rst";
+ operating-points-v2 =3D <&gpu_opp_table>;
+ status =3D "disabled";
+ };
+
gic: interrupt-controller@14900000 {
compatible =3D "arm,gic-v3";
reg =3D <0x0 0x14900000 0 0x20000>,
--=20
2.43.0
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From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
To: tomm.merciai@gmail.com
Cc: linux-renesas-soc@vger.kernel.org,
biju.das.jz@bp.renesas.com,
Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
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Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org
Subject: [PATCH 4/4] arm64: dts: renesas: rzg3e-smarc-som: Enable Mali-G52
Date: Wed, 2 Apr 2025 15:11:41 +0200
Message-ID: <20250402131142.1270701-5-tommaso.merciai.xr@bp.renesas.com>
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Enable Mali-G52 (GPU) node on RZ/G3E SMARC SoM board.
Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi b/arch/arm64/=
boot/dts/renesas/rzg3e-smarc-som.dtsi
index 72b42a81bcf34..5c4596dea2160 100644
--- a/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3e-smarc-som.dtsi
@@ -45,6 +45,16 @@ reg_3p3v: regulator-3p3v {
regulator-boot-on;
regulator-always-on;
};
+
+ reg_vdd0p8v_others: regulator-vdd0p8v-others {
+ compatible =3D "regulator-fixed";
+
+ regulator-name =3D "fixed-0.8V";
+ regulator-min-microvolt =3D <800000>;
+ regulator-max-microvolt =3D <800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
};
=20
&audio_extal_clk {
@@ -123,6 +133,11 @@ sd2-pwen {
};
};
=20
+&gpu {
+ status =3D "okay";
+ mali-supply =3D <®_vdd0p8v_others>;
+};
+
&qextal_clk {
clock-frequency =3D <24000000>;
};
--=20
2.43.0